1 /* soc.h: Definitions for Sparc SUNW,soc Fibre Channel Sbus driver.
3 * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
13 /* Hardware structures and constants first {{{ */
16 volatile u32 cfg
; /* Config Register */
17 volatile u32 sae
; /* Slave Access Error Register */
18 volatile u32 cmd
; /* Command & Status Register */
19 volatile u32 imask
; /* Interrupt Mask Register */
23 #define SOC_CFG_EXT_RAM_BANK_MASK 0x07000000
24 #define SOC_CFG_EEPROM_BANK_MASK 0x00030000
25 #define SOC_CFG_BURST64_MASK 0x00000700
26 #define SOC_CFG_SBUS_PARITY_TEST 0x00000020
27 #define SOC_CFG_SBUS_PARITY_CHECK 0x00000010
28 #define SOC_CFG_SBUS_ENHANCED 0x00000008
29 #define SOC_CFG_BURST_MASK 0x00000007
31 #define SOC_CFG_BURST_4 0x00000000
32 #define SOC_CFG_BURST_16 0x00000004
33 #define SOC_CFG_BURST_32 0x00000005
34 #define SOC_CFG_BURST_64 0x00000006
36 /* Slave Access Error Register */
37 #define SOC_SAE_ALIGNMENT 0x00000004
38 #define SOC_SAE_UNSUPPORTED 0x00000002
39 #define SOC_SAE_PARITY 0x00000001
41 /* Command & Status Register */
42 #define SOC_CMD_RSP_QALL 0x000f0000
43 #define SOC_CMD_RSP_Q0 0x00010000
44 #define SOC_CMD_RSP_Q1 0x00020000
45 #define SOC_CMD_RSP_Q2 0x00040000
46 #define SOC_CMD_RSP_Q3 0x00080000
47 #define SOC_CMD_REQ_QALL 0x00000f00
48 #define SOC_CMD_REQ_Q0 0x00000100
49 #define SOC_CMD_REQ_Q1 0x00000200
50 #define SOC_CMD_REQ_Q2 0x00000400
51 #define SOC_CMD_REQ_Q3 0x00000800
52 #define SOC_CMD_SAE 0x00000080
53 #define SOC_CMD_INTR_PENDING 0x00000008
54 #define SOC_CMD_NON_QUEUED 0x00000004
55 #define SOC_CMD_IDLE 0x00000002
56 #define SOC_CMD_SOFT_RESET 0x00000001
58 /* Interrupt Mask Register */
59 #define SOC_IMASK_RSP_QALL 0x000f0000
60 #define SOC_IMASK_RSP_Q0 0x00010000
61 #define SOC_IMASK_RSP_Q1 0x00020000
62 #define SOC_IMASK_RSP_Q2 0x00040000
63 #define SOC_IMASK_RSP_Q3 0x00080000
64 #define SOC_IMASK_REQ_QALL 0x00000f00
65 #define SOC_IMASK_REQ_Q0 0x00000100
66 #define SOC_IMASK_REQ_Q1 0x00000200
67 #define SOC_IMASK_REQ_Q2 0x00000400
68 #define SOC_IMASK_REQ_Q3 0x00000800
69 #define SOC_IMASK_SAE 0x00000080
70 #define SOC_IMASK_NON_QUEUED 0x00000004
72 #define SOC_INTR(s, cmd) \
73 (((cmd & SOC_CMD_RSP_QALL) | ((~cmd) & SOC_CMD_REQ_QALL)) \
76 #define SOC_SETIMASK(s, i) \
77 (s)->imask = (i); (s)->regs->imask = (i)
81 * This is a 64KB register area. It accepts only halfword access.
82 * That's why here are the following inline functions...
87 /* Get 32bit number from XRAM */
88 static inline u32
xram_get_32 (xram_p x
)
90 return (((u32
)*x
) << 16) | (x
[1]);
93 /* Like the above, but when we don't care about the high 16 bits */
94 static inline u32
xram_get_32low (xram_p x
)
99 static inline u8
xram_get_8 (xram_p x
)
102 x
= (xram_p
)((long)x
- 1);
105 return (u8
)(*x
>> 8);
108 static inline void xram_copy_from (void *p
, xram_p x
, int len
)
110 for (len
>>= 2; len
> 0; len
--, x
+= 2) {
111 *((u32
*)p
)++ = (((u32
)(*x
)) << 16) | (x
[1]);
115 static inline void xram_copy_to (xram_p x
, void *p
, int len
)
118 for (len
>>= 2; len
> 0; len
--, x
+= 2) {
125 static inline void xram_bzero (xram_p x
, int len
)
127 for (len
>>= 1; len
> 0; len
--) *x
++ = 0;
132 /* These two are in sizeof(u16) units */
133 #define SOC_CQ_REQ_OFFSET 0x100
134 #define SOC_CQ_RSP_OFFSET 0x110
144 #define SOC_PORT_A 0x0000 /* From/To Port A */
145 #define SOC_PORT_B 0x0001 /* From/To Port A */
146 #define SOC_FC_HDR 0x0002 /* Contains FC Header */
147 #define SOC_NORSP 0x0004 /* Don't generate response nor interrupt */
148 #define SOC_NOINT 0x0008 /* Generate response but not interrupt */
149 #define SOC_XFERRDY 0x0010 /* Generate XFERRDY */
150 #define SOC_IGNOREPARAM 0x0020 /* Ignore PARAM field in the FC header */
151 #define SOC_COMPLETE 0x0040 /* Command completed */
152 #define SOC_UNSOLICITED 0x0080 /* For request this is the packet to establish unsolicited pools, */
153 /* for rsp this is unsolicited packet */
154 #define SOC_STATUS 0x0100 /* State change (on/off line) */
169 #define SOC_CQTYPE_OUTBOUND 0x01
170 #define SOC_CQTYPE_INBOUND 0x02
171 #define SOC_CQTYPE_SIMPLE 0x03
172 #define SOC_CQTYPE_IO_WRITE 0x04
173 #define SOC_CQTYPE_IO_READ 0x05
174 #define SOC_CQTYPE_UNSOLICITED 0x06
175 #define SOC_CQTYPE_DIAG 0x07
176 #define SOC_CQTYPE_OFFLINE 0x08
177 #define SOC_CQTYPE_RESPONSE 0x10
178 #define SOC_CQTYPE_INLINE 0x20
180 #define SOC_CQFLAGS_CONT 0x01
181 #define SOC_CQFLAGS_FULL 0x02
182 #define SOC_CQFLAGS_BADHDR 0x04
183 #define SOC_CQFLAGS_BADPKT 0x08
200 #define SOC_ONLINE 0x10
201 #define SOC_OFFLINE 0x11
202 #define SOC_TIMEOUT 0x12
203 #define SOC_OVERRUN 0x13
204 #define SOC_UNKOWN_CQ_TYPE 0x20
205 #define SOC_BAD_SEG_CNT 0x21
206 #define SOC_MAX_XCHG_EXCEEDED 0x22
207 #define SOC_BAD_XID 0x23
208 #define SOC_XCHG_BUSY 0x24
209 #define SOC_BAD_POOL_ID 0x25
210 #define SOC_INSUFFICIENT_CQES 0x26
211 #define SOC_ALLOC_FAIL 0x27
212 #define SOC_BAD_SID 0x28
213 #define SOC_NO_SEG_INIT 0x29
229 /* Now our software structures and constants we use to drive the beast {{{ */
231 #define SOC_CQ_REQ0_SIZE 4
232 #define SOC_CQ_REQ1_SIZE 64
233 #define SOC_CQ_RSP0_SIZE 8
234 #define SOC_CQ_RSP1_SIZE 4
236 #define SOC_SOLICITED_RSP_Q 0
237 #define SOC_UNSOLICITED_RSP_Q 1
242 /* This must come first */
250 soc_hw_cq
*hw_cq
; /* Related XRAM cq */
259 soc_port port
[2]; /* Every SOC has one or two FC ports */
260 soc_cq req
[2]; /* Request CQs */
261 soc_cq rsp
[2]; /* Response CQs */
263 struct soc_regs
*regs
;
266 u32 imask
; /* Our copy of regs->imask */
267 u32 cfg
; /* Our copy of regs->cfg */
268 char serv_params
[80];
270 int curr_port
; /* Which port will have priority to fcp_queue_empty */
275 #endif /* !(__SOC_H) */