1 /* $Id: hfc_2bs0.c,v 1.9 1999/07/01 08:11:36 keil Exp $
3 * specific routines for CCD's HFC 2BS0
5 * Author Karsten Keil (keil@isdn4linux.de)
9 * Revision 1.9 1999/07/01 08:11:36 keil
10 * Common HiSax version for 2.0, 2.1, 2.2 and 2.3 kernel
12 * Revision 1.8 1998/11/15 23:54:43 keil
15 * Revision 1.7 1998/09/30 22:24:46 keil
16 * Fix missing line in setstack*
18 * Revision 1.6 1998/08/13 23:36:28 keil
19 * HiSax 3.1 - don't work stable with current LinkLevel
21 * Revision 1.5 1998/05/25 12:57:54 keil
22 * HiSax golden code from certification, Don't use !!!
23 * No leased lines, no X75, but many changes.
25 * Revision 1.4 1998/02/12 23:07:29 keil
26 * change for 2.1.86 (removing FREE_READ/FREE_WRITE from [dev]_kfree_skb()
28 * Revision 1.3 1997/11/06 17:13:35 keil
31 * Revision 1.2 1997/10/29 19:04:47 keil
34 * Revision 1.1 1997/09/11 17:31:33 keil
35 * Common part for HFC 2BS0 based cards
40 #define __NO_VERSION__
45 #include <linux/interrupt.h>
48 WaitForBusy(struct IsdnCardState
*cs
)
56 while (!(cs
->BC_Read_Reg(cs
, HFC_STATUS
, 0) & HFC_BUSY
) && to
) {
57 val
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2
|
58 (cs
->hw
.hfc
.cip
& 3));
64 printk(KERN_WARNING
"HiSax: waitforBusy timeout\n");
71 WaitNoBusy(struct IsdnCardState
*cs
)
75 while ((cs
->BC_Read_Reg(cs
, HFC_STATUS
, 0) & HFC_BUSY
) && to
) {
80 printk(KERN_WARNING
"HiSax: waitforBusy timeout\n");
87 GetFreeFifoBytes(struct BCState
*bcs
)
91 if (bcs
->hw
.hfc
.f1
== bcs
->hw
.hfc
.f2
)
92 return (bcs
->cs
->hw
.hfc
.fifosize
);
93 s
= bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] - bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f2
];
95 s
+= bcs
->cs
->hw
.hfc
.fifosize
;
96 s
= bcs
->cs
->hw
.hfc
.fifosize
- s
;
101 ReadZReg(struct BCState
*bcs
, u_char reg
)
106 val
= 256 * bcs
->cs
->BC_Read_Reg(bcs
->cs
, HFC_DATA
, reg
| HFC_CIP
| HFC_Z_HIGH
);
108 val
+= bcs
->cs
->BC_Read_Reg(bcs
->cs
, HFC_DATA
, reg
| HFC_CIP
| HFC_Z_LOW
);
113 hfc_sched_event(struct BCState
*bcs
, int event
)
115 bcs
->event
|= 1 << event
;
116 queue_task(&bcs
->tqueue
, &tq_immediate
);
117 mark_bh(IMMEDIATE_BH
);
121 hfc_clear_fifo(struct BCState
*bcs
)
123 struct IsdnCardState
*cs
= bcs
->cs
;
129 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
130 debugl1(cs
, "hfc_clear_fifo");
133 cip
= HFC_CIP
| HFC_F1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
134 if ((cip
& 0xc3) != (cs
->hw
.hfc
.cip
& 0xc3)) {
135 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cip
, cip
);
139 f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
140 cip
= HFC_CIP
| HFC_F2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
142 f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
143 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
144 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
146 while (((f1
!= f2
) || (z1
!= z2
)) && cnt
--) {
147 if (cs
->debug
& L1_DEB_HSCX
)
148 debugl1(cs
, "hfc clear %d f1(%d) f2(%d)",
149 bcs
->channel
, f1
, f2
);
152 rcnt
+= cs
->hw
.hfc
.fifosize
;
155 if (cs
->debug
& L1_DEB_HSCX
)
156 debugl1(cs
, "hfc clear %d z1(%x) z2(%x) cnt(%d)",
157 bcs
->channel
, z1
, z2
, rcnt
);
158 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
160 while ((idx
< rcnt
) && WaitNoBusy(cs
)) {
161 cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
166 cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
167 HFC_CHANNEL(bcs
->channel
));
170 cip
= HFC_CIP
| HFC_F1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
172 f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
173 cip
= HFC_CIP
| HFC_F2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
175 f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
176 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
177 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
179 restore_flags(flags
);
184 static struct sk_buff
186 hfc_empty_fifo(struct BCState
*bcs
, int count
)
190 struct IsdnCardState
*cs
= bcs
->cs
;
195 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
196 debugl1(cs
, "hfc_empty_fifo");
198 if (count
> HSCX_BUFMAX
+ 3) {
199 if (cs
->debug
& L1_DEB_WARN
)
200 debugl1(cs
, "hfc_empty_fifo: incoming packet too large");
201 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
202 while ((idx
++ < count
) && WaitNoBusy(cs
))
203 cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
205 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
206 HFC_CHANNEL(bcs
->channel
));
211 if (cs
->debug
& L1_DEB_WARN
)
212 debugl1(cs
, "hfc_empty_fifo: incoming packet too small");
213 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
214 while ((idx
++ < count
) && WaitNoBusy(cs
))
215 cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
217 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
218 HFC_CHANNEL(bcs
->channel
));
222 if (!(skb
= dev_alloc_skb(count
- 3)))
223 printk(KERN_WARNING
"HFC: receive out of memory\n");
226 ptr
= skb_put(skb
, count
- 3);
228 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
229 while ((idx
< count
- 3) && WaitNoBusy(cs
)) {
230 *ptr
++ = cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
233 if (idx
!= count
- 3) {
234 debugl1(cs
, "RFIFO BUSY error");
235 printk(KERN_WARNING
"HFC FIFO channel %d BUSY Error\n", bcs
->channel
);
236 idev_kfree_skb(skb
, FREE_READ
);
238 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
239 HFC_CHANNEL(bcs
->channel
));
244 chksum
= (cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
) << 8);
246 chksum
+= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
248 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
249 if (cs
->debug
& L1_DEB_HSCX
)
250 debugl1(cs
, "hfc_empty_fifo %d chksum %x stat %x",
251 bcs
->channel
, chksum
, stat
);
253 debugl1(cs
, "FIFO CRC error");
254 idev_kfree_skb(skb
, FREE_READ
);
258 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
259 HFC_CHANNEL(bcs
->channel
));
266 hfc_fill_fifo(struct BCState
*bcs
)
268 struct IsdnCardState
*cs
= bcs
->cs
;
276 if (bcs
->tx_skb
->len
<= 0)
281 cip
= HFC_CIP
| HFC_F1
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
);
282 if ((cip
& 0xc3) != (cs
->hw
.hfc
.cip
& 0xc3)) {
283 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cip
, cip
);
287 bcs
->hw
.hfc
.f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
288 cip
= HFC_CIP
| HFC_F2
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
);
290 bcs
->hw
.hfc
.f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
291 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] = ReadZReg(bcs
, HFC_Z1
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
));
292 if (cs
->debug
& L1_DEB_HSCX
)
293 debugl1(cs
, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
294 bcs
->channel
, bcs
->hw
.hfc
.f1
, bcs
->hw
.hfc
.f2
,
295 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
]);
296 fcnt
= bcs
->hw
.hfc
.f1
- bcs
->hw
.hfc
.f2
;
300 if (cs
->debug
& L1_DEB_HSCX
)
301 debugl1(cs
, "hfc_fill_fifo more as 30 frames");
302 restore_flags(flags
);
305 count
= GetFreeFifoBytes(bcs
);
306 if (cs
->debug
& L1_DEB_HSCX
)
307 debugl1(cs
, "hfc_fill_fifo %d count(%ld/%d)",
308 bcs
->channel
, bcs
->tx_skb
->len
,
310 if (count
< bcs
->tx_skb
->len
) {
311 if (cs
->debug
& L1_DEB_HSCX
)
312 debugl1(cs
, "hfc_fill_fifo no fifo mem");
313 restore_flags(flags
);
316 cip
= HFC_CIP
| HFC_FIFO_IN
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
);
318 while ((idx
< bcs
->tx_skb
->len
) && WaitNoBusy(cs
))
319 cs
->BC_Write_Reg(cs
, HFC_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
++]);
320 if (idx
!= bcs
->tx_skb
->len
) {
321 debugl1(cs
, "FIFO Send BUSY error");
322 printk(KERN_WARNING
"HFC S FIFO channel %d BUSY Error\n", bcs
->channel
);
324 count
= bcs
->tx_skb
->len
;
325 bcs
->tx_cnt
-= count
;
326 if (PACKET_NOACK
== bcs
->tx_skb
->pkt_type
)
328 idev_kfree_skb(bcs
->tx_skb
, FREE_WRITE
);
332 cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F1_INC
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
));
333 if (bcs
->st
->lli
.l1writewakeup
&& (count
>= 0))
334 bcs
->st
->lli
.l1writewakeup(bcs
->st
, count
);
335 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
337 restore_flags(flags
);
342 main_irq_hfc(struct BCState
*bcs
)
345 struct IsdnCardState
*cs
= bcs
->cs
;
348 int receive
, transmit
, count
= 5;
355 cip
= HFC_CIP
| HFC_F1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
356 if ((cip
& 0xc3) != (cs
->hw
.hfc
.cip
& 0xc3)) {
357 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cip
, cip
);
361 f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
362 cip
= HFC_CIP
| HFC_F2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
364 f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
366 if (cs
->debug
& L1_DEB_HSCX
)
367 debugl1(cs
, "hfc rec %d f1(%d) f2(%d)",
368 bcs
->channel
, f1
, f2
);
370 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
371 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
374 rcnt
+= cs
->hw
.hfc
.fifosize
;
376 if (cs
->debug
& L1_DEB_HSCX
)
377 debugl1(cs
, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
378 bcs
->channel
, z1
, z2
, rcnt
);
380 if ((skb
= hfc_empty_fifo(bcs
, rcnt
))) {
381 skb_queue_tail(&bcs
->rqueue
, skb
);
382 hfc_sched_event(bcs
, B_RCVBUFREADY
);
387 restore_flags(flags
);
392 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
394 if (test_bit(BC_FLG_BUSY
, &bcs
->Flag
))
397 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
399 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
401 if (test_bit(BC_FLG_BUSY
, &bcs
->Flag
))
405 hfc_sched_event(bcs
, B_XMTBUFREADY
);
408 restore_flags(flags
);
409 if ((receive
|| transmit
) && count
)
415 mode_hfc(struct BCState
*bcs
, int mode
, int bc
)
417 struct IsdnCardState
*cs
= bcs
->cs
;
419 if (cs
->debug
& L1_DEB_HSCX
)
420 debugl1(cs
, "HFC 2BS0 mode %d bchan %d/%d",
421 mode
, bc
, bcs
->channel
);
428 cs
->hw
.hfc
.isac_spcr
&= ~0x03;
430 cs
->hw
.hfc
.isac_spcr
&= ~0x0c;
432 case (L1_MODE_TRANS
):
434 cs
->hw
.hfc
.ctmt
|= 1;
435 cs
->hw
.hfc
.isac_spcr
&= ~0x03;
436 cs
->hw
.hfc
.isac_spcr
|= 0x02;
438 cs
->hw
.hfc
.ctmt
|= 2;
439 cs
->hw
.hfc
.isac_spcr
&= ~0x0c;
440 cs
->hw
.hfc
.isac_spcr
|= 0x08;
445 cs
->hw
.hfc
.ctmt
&= ~1;
446 cs
->hw
.hfc
.isac_spcr
&= ~0x03;
447 cs
->hw
.hfc
.isac_spcr
|= 0x02;
449 cs
->hw
.hfc
.ctmt
&= ~2;
450 cs
->hw
.hfc
.isac_spcr
&= ~0x0c;
451 cs
->hw
.hfc
.isac_spcr
|= 0x08;
455 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cs
->hw
.hfc
.ctmt
, cs
->hw
.hfc
.ctmt
);
456 cs
->writeisac(cs
, ISAC_SPCR
, cs
->hw
.hfc
.isac_spcr
);
462 hfc_l2l1(struct PStack
*st
, int pr
, void *arg
)
464 struct sk_buff
*skb
= arg
;
468 case (PH_DATA
| REQUEST
):
471 if (st
->l1
.bcs
->tx_skb
) {
472 skb_queue_tail(&st
->l1
.bcs
->squeue
, skb
);
473 restore_flags(flags
);
475 st
->l1
.bcs
->tx_skb
= skb
;
476 test_and_set_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
477 st
->l1
.bcs
->cs
->BC_Send_Data(st
->l1
.bcs
);
478 restore_flags(flags
);
481 case (PH_PULL
| INDICATION
):
482 if (st
->l1
.bcs
->tx_skb
) {
483 printk(KERN_WARNING
"hfc_l2l1: this shouldn't happen\n");
488 test_and_set_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
489 st
->l1
.bcs
->tx_skb
= skb
;
490 st
->l1
.bcs
->cs
->BC_Send_Data(st
->l1
.bcs
);
491 restore_flags(flags
);
493 case (PH_PULL
| REQUEST
):
494 if (!st
->l1
.bcs
->tx_skb
) {
495 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
496 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
498 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
500 case (PH_ACTIVATE
| REQUEST
):
501 test_and_set_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
502 mode_hfc(st
->l1
.bcs
, st
->l1
.mode
, st
->l1
.bc
);
503 l1_msg_b(st
, pr
, arg
);
505 case (PH_DEACTIVATE
| REQUEST
):
506 l1_msg_b(st
, pr
, arg
);
508 case (PH_DEACTIVATE
| CONFIRM
):
509 test_and_clear_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
510 test_and_clear_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
511 mode_hfc(st
->l1
.bcs
, 0, st
->l1
.bc
);
512 st
->l1
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
519 close_hfcstate(struct BCState
*bcs
)
521 mode_hfc(bcs
, 0, bcs
->channel
);
522 if (test_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
523 discard_queue(&bcs
->rqueue
);
524 discard_queue(&bcs
->squeue
);
526 idev_kfree_skb(bcs
->tx_skb
, FREE_WRITE
);
528 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
531 test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
);
535 open_hfcstate(struct IsdnCardState
*cs
, struct BCState
*bcs
)
537 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
538 skb_queue_head_init(&bcs
->rqueue
);
539 skb_queue_head_init(&bcs
->squeue
);
542 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
549 setstack_hfc(struct PStack
*st
, struct BCState
*bcs
)
551 bcs
->channel
= st
->l1
.bc
;
552 if (open_hfcstate(st
->l1
.hardware
, bcs
))
555 st
->l2
.l2l1
= hfc_l2l1
;
556 setstack_manager(st
);
563 init_send(struct BCState
*bcs
)
567 if (!(bcs
->hw
.hfc
.send
= kmalloc(32 * sizeof(unsigned int), GFP_ATOMIC
))) {
569 "HiSax: No memory for hfc.send\n");
572 for (i
= 0; i
< 32; i
++)
573 bcs
->hw
.hfc
.send
[i
] = 0x1fff;
577 inithfc(struct IsdnCardState
*cs
)
579 init_send(&cs
->bcs
[0]);
580 init_send(&cs
->bcs
[1]);
581 cs
->BC_Send_Data
= &hfc_fill_fifo
;
582 cs
->bcs
[0].BC_SetStack
= setstack_hfc
;
583 cs
->bcs
[1].BC_SetStack
= setstack_hfc
;
584 cs
->bcs
[0].BC_Close
= close_hfcstate
;
585 cs
->bcs
[1].BC_Close
= close_hfcstate
;
586 mode_hfc(cs
->bcs
, 0, 0);
587 mode_hfc(cs
->bcs
+ 1, 0, 0);
591 releasehfc(struct IsdnCardState
*cs
)
593 if (cs
->bcs
[0].hw
.hfc
.send
) {
594 kfree(cs
->bcs
[0].hw
.hfc
.send
);
595 cs
->bcs
[0].hw
.hfc
.send
= NULL
;
597 if (cs
->bcs
[1].hw
.hfc
.send
) {
598 kfree(cs
->bcs
[1].hw
.hfc
.send
);
599 cs
->bcs
[1].hw
.hfc
.send
= NULL
;