i386/linux-2.3.21/drivers/isdn/hisax/hfc_pci.h

   1 /* $Id: hfc_pci.h,v 1.6 1999/08/28 21:04:29 werner Exp $
   2
   3  *  specific defines for CCD's HFC 2BDS0 PCI chips
   4  *
   5  * Author     Werner Cornelius (werner@isdn4linux.de)
   6  *
   7  * Copyright 1999  by Werner Cornelius (werner@isdn4linux.de)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2, or (at your option)
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  * $Log: hfc_pci.h,v $
  24  * Revision 1.6  1999/08/28 21:04:29  werner
  25  * Implemented full audio support (transparent mode)
  26  *
  27  * Revision 1.5  1999/08/09 19:13:34  werner
  28  * moved constant pci ids to pci id table
  29  *
  30  * Revision 1.4  1999/08/08 10:17:33  werner
  31  * added new PCI vendor and card ids for Manufacturer 0x1043
  32  *
  33  * Revision 1.3  1999/07/14 12:39:34  werner
  34  * Added changes for echo handling.
  35  *
  36  * Revision 1.2  1999/07/01 08:07:52  keil
  37  * Initial version
  38  *
  39  *
  40  *
  41  */
  42
  43 /*********************************************/
  44 /* thresholds for transparent B-channel mode */
  45 /* change mask and threshold simultaneously  */
  46 /*********************************************/
  47 #define HFCPCI_BTRANS_THRESHOLD 128
  48 #define HFCPCI_BTRANS_THRESMASK 0x00
  49
  50
  51
  52 /* defines for PCI config */
  53
  54 #define PCI_ENA_MEMIO    0x02
  55 #define PCI_ENA_MASTER   0x04
  56
  57
  58 /* GCI/IOM bus monitor registers */
  59
  60 #define HCFPCI_C_I       0x08
  61 #define HFCPCI_TRxR      0x0C
  62 #define HFCPCI_MON1_D    0x28
  63 #define HFCPCI_MON2_D    0x2C
  64
  65
  66 /* GCI/IOM bus timeslot registers */
  67
  68 #define HFCPCI_B1_SSL    0x80
  69 #define HFCPCI_B2_SSL    0x84
  70 #define HFCPCI_AUX1_SSL  0x88
  71 #define HFCPCI_AUX2_SSL  0x8C
  72 #define HFCPCI_B1_RSL    0x90
  73 #define HFCPCI_B2_RSL    0x94
  74 #define HFCPCI_AUX1_RSL  0x98
  75 #define HFCPCI_AUX2_RSL  0x9C
  76
  77 /* GCI/IOM bus data registers */
  78
  79 #define HFCPCI_B1_D      0xA0
  80 #define HFCPCI_B2_D      0xA4
  81 #define HFCPCI_AUX1_D    0xA8
  82 #define HFCPCI_AUX2_D    0xAC
  83
  84 /* GCI/IOM bus configuration registers */
  85
  86 #define HFCPCI_MST_EMOD  0xB4
  87 #define HFCPCI_MST_MODE  0xB8
  88 #define HFCPCI_CONNECT   0xBC
  89
  90
  91 /* Interrupt and status registers */
  92
  93 #define HFCPCI_FIFO_EN   0x44
  94 #define HFCPCI_TRM       0x48
  95 #define HFCPCI_B_MODE    0x4C
  96 #define HFCPCI_CHIP_ID   0x58
  97 #define HFCPCI_CIRM      0x60
  98 #define HFCPCI_CTMT      0x64
  99 #define HFCPCI_INT_M1    0x68
 100 #define HFCPCI_INT_M2    0x6C
 101 #define HFCPCI_INT_S1    0x78
 102 #define HFCPCI_INT_S2    0x7C
 103 #define HFCPCI_STATUS    0x70
 104
 105 /* S/T section registers */
 106
 107 #define HFCPCI_STATES    0xC0
 108 #define HFCPCI_SCTRL     0xC4
 109 #define HFCPCI_SCTRL_E   0xC8
 110 #define HFCPCI_SCTRL_R   0xCC
 111 #define HFCPCI_SQ        0xD0
 112 #define HFCPCI_CLKDEL    0xDC
 113 #define HFCPCI_B1_REC    0xF0
 114 #define HFCPCI_B1_SEND   0xF0
 115 #define HFCPCI_B2_REC    0xF4
 116 #define HFCPCI_B2_SEND   0xF4
 117 #define HFCPCI_D_REC     0xF8
 118 #define HFCPCI_D_SEND    0xF8
 119 #define HFCPCI_E_REC     0xFC
 120
 121
 122 /* bits in status register (READ) */
 123 #define HFCPCI_PCI_PROC   0x02
 124 #define HFCPCI_NBUSY      0x04
 125 #define HFCPCI_TIMER_ELAP 0x10
 126 #define HFCPCI_STATINT    0x20
 127 #define HFCPCI_FRAMEINT   0x40
 128 #define HFCPCI_ANYINT     0x80
 129
 130 /* bits in CTMT (Write) */
 131 #define HFCPCI_CLTIMER    0x80
 132 #define HFCPCI_TIM3_125   0x00
 133 #define HFCPCI_TIM25      0x10
 134 #define HFCPCI_TIM50      0x14
 135 #define HFCPCI_TIM400     0x18
 136 #define HFCPCI_TIM800     0x1C
 137 #define HFCPCI_AUTO_TIMER 0x20
 138 #define HFCPCI_TRANSB2    0x02
 139 #define HFCPCI_TRANSB1    0x01
 140
 141 /* bits in CIRM (Write) */
 142 #define HFCPCI_AUX_MSK    0x07
 143 #define HFCPCI_RESET      0x08
 144 #define HFCPCI_B1_REV     0x40
 145 #define HFCPCI_B2_REV     0x80
 146
 147 /* bits in INT_M1 and INT_S1 */
 148 #define HFCPCI_INTS_B1TRANS  0x01
 149 #define HFCPCI_INTS_B2TRANS  0x02
 150 #define HFCPCI_INTS_DTRANS   0x04
 151 #define HFCPCI_INTS_B1REC    0x08
 152 #define HFCPCI_INTS_B2REC    0x10
 153 #define HFCPCI_INTS_DREC     0x20
 154 #define HFCPCI_INTS_L1STATE  0x40
 155 #define HFCPCI_INTS_TIMER    0x80
 156
 157 /* bits in INT_M2 */
 158 #define HFCPCI_PROC_TRANS    0x01
 159 #define HFCPCI_GCI_I_CHG     0x02
 160 #define HFCPCI_GCI_MON_REC   0x04
 161 #define HFCPCI_IRQ_ENABLE    0x08
 162 #define HFCPCI_PMESEL        0x80
 163
 164 /* bits in STATES */
 165 #define HFCPCI_STATE_MSK     0x0F
 166 #define HFCPCI_LOAD_STATE    0x10
 167 #define HFCPCI_ACTIVATE      0x20
 168 #define HFCPCI_DO_ACTION     0x40
 169 #define HFCPCI_NT_G2_G3      0x80
 170
 171 /* bits in HFCD_MST_MODE */
 172 #define HFCPCI_MASTER        0x01
 173 #define HFCPCI_SLAVE         0x00
 174 /* remaining bits are for codecs control */
 175
 176 /* bits in HFCD_SCTRL */
 177 #define SCTRL_B1_ENA         0x01
 178 #define SCTRL_B2_ENA         0x02
 179 #define SCTRL_MODE_TE        0x00
 180 #define SCTRL_MODE_NT        0x04
 181 #define SCTRL_LOW_PRIO       0x08
 182 #define SCTRL_SQ_ENA         0x10
 183 #define SCTRL_TEST           0x20
 184 #define SCTRL_NONE_CAP       0x40
 185 #define SCTRL_PWR_DOWN       0x80
 186
 187 /* bits in SCTRL_E  */
 188 #define HFCPCI_AUTO_AWAKE    0x01
 189 #define HFCPCI_DBIT_1        0x04
 190 #define HFCPCI_IGNORE_COL    0x08
 191 #define HFCPCI_CHG_B1_B2     0x80
 192
 193 /****************************/
 194 /* bits in FIFO_EN register */
 195 /****************************/
 196 #define HFCPCI_FIFOEN_B1     0x03
 197 #define HFCPCI_FIFOEN_B2     0x0C
 198 #define HFCPCI_FIFOEN_DTX    0x10
 199 #define HFCPCI_FIFOEN_B2RX   0x08
 200
 201
 202 /***********************************/
 203 /* definitions of fifo memory area */
 204 /***********************************/
 205 #define MAX_D_FRAMES 15
 206 #define MAX_B_FRAMES 31
 207 #define B_SUB_VAL    0x200
 208 #define B_FIFO_SIZE  (0x2000 - B_SUB_VAL)
 209 #define D_FIFO_SIZE  512
 210 #define D_FREG_MASK  0xF
 211
 212 typedef struct {
 213     unsigned short z1;  /* Z1 pointer 16 Bit */
 214     unsigned short z2;  /* Z2 pointer 16 Bit */
 215   } z_type;
 216
 217 typedef struct {
 218     u_char data[D_FIFO_SIZE]; /* FIFO data space */
 219     u_char fill1[0x20A0-D_FIFO_SIZE]; /* reserved, do not use */
 220     u_char f1,f2; /* f pointers */
 221     u_char fill2[0x20C0-0x20A2]; /* reserved, do not use */
 222     z_type za[MAX_D_FRAMES+1]; /* mask index with D_FREG_MASK for access */
 223     u_char fill3[0x4000-0x2100]; /* align 16K */
 224   } dfifo_type;
 225
 226 typedef struct {
 227     z_type za[MAX_B_FRAMES+1]; /* only range 0x0..0x1F allowed */
 228     u_char f1,f2; /* f pointers */
 229     u_char fill[0x2100-0x2082]; /* alignment */
 230   } bzfifo_type;
 231
 232
 233 typedef union {
 234     struct {
 235       dfifo_type d_tx; /* D-send channel */
 236       dfifo_type d_rx; /* D-receive channel */
 237     } d_chan;
 238     struct {
 239       u_char fill1[0x200];
 240       u_char txdat_b1[B_FIFO_SIZE];
 241       bzfifo_type txbz_b1;
 242
 243       bzfifo_type txbz_b2;
 244       u_char txdat_b2[B_FIFO_SIZE];
 245
 246       u_char fill2[D_FIFO_SIZE];
 247
 248       u_char rxdat_b1[B_FIFO_SIZE];
 249       bzfifo_type rxbz_b1;
 250
 251       bzfifo_type rxbz_b2;
 252       u_char rxdat_b2[B_FIFO_SIZE];
 253     } b_chans;
 254     u_char fill[32768];
 255   } fifo_area;
 256
 257
 258 #define Write_hfc(a,b,c) (*(((u_char *)a->hw.hfcpci.pci_io)+b) = c)
 259 #define Read_hfc(a,b) (*(((u_char *)a->hw.hfcpci.pci_io)+b))
 260
 261 extern void main_irq_hcpci(struct BCState *bcs);
 262 extern void inithfcpci(struct IsdnCardState *cs);
 263 extern void releasehfcpci(struct IsdnCardState *cs);