i386/linux-2.3.21/include/asm-alpha/core_t2.h

   1 #ifndef __ALPHA_T2__H__
   2 #define __ALPHA_T2__H__
   3
   4 #include <linux/config.h>
   5 #include <linux/types.h>
   6 #include <asm/compiler.h>
   7
   8
   9 /*
  10  * T2 is the internal name for the core logic chipset which provides
  11  * memory controller and PCI access for the SABLE-based systems.
  12  *
  13  * This file is based on:
  14  *
  15  * SABLE I/O Specification
  16  * Revision/Update Information: 1.3
  17  *
  18  * jestabro@amt.tay1.dec.com Initial Version.
  19  *
  20  */
  21
  22 #define T2_MEM_R1_MASK 0x03ffffff  /* Mem sparse region 1 mask is 26 bits */
  23
  24 #define T2_DMA_WIN_BASE         (1UL*1024*1024*1024)
  25 #define T2_DMA_WIN_SIZE         (1UL*1024*1024*1024)
  26
  27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
  28 #define _GAMMA_BIAS             0x8000000000UL
  29
  30 #if defined(CONFIG_ALPHA_GENERIC)
  31 #define GAMMA_BIAS              alpha_mv.sys.t2.gamma_bias
  32 #elif defined(CONFIG_ALPHA_GAMMA)
  33 #define GAMMA_BIAS              _GAMMA_BIAS
  34 #else
  35 #define GAMMA_BIAS              0
  36 #endif
  37
  38 /*
  39  * Memory spaces:
  40  */
  41 #define T2_CONF                 (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
  42 #define T2_IO                   (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
  43 #define T2_SPARSE_MEM           (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
  44 #define T2_DENSE_MEM            (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
  45
  46 #define T2_IOCSR                (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
  47 #define T2_CERR1                (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
  48 #define T2_CERR2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
  49 #define T2_CERR3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
  50 #define T2_PERR1                (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
  51 #define T2_PERR2                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
  52 #define T2_PSCR                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
  53 #define T2_HAE_1                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
  54 #define T2_HAE_2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
  55 #define T2_HBASE                (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
  56 #define T2_WBASE1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
  57 #define T2_WMASK1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
  58 #define T2_TBASE1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
  59 #define T2_WBASE2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
  60 #define T2_WMASK2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
  61 #define T2_TBASE2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
  62 #define T2_TLBBR                (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
  63
  64 #define T2_HAE_3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
  65 #define T2_HAE_4                (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
  66
  67 #define T2_HAE_ADDRESS          T2_HAE_1
  68
  69 /*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
  70  3.8fff.ffff
  71  *
  72  *  +--------------+ 3 8000 0000
  73  *  | CPU 0 CSRs   |
  74  *  +--------------+ 3 8100 0000
  75  *  | CPU 1 CSRs   |
  76  *  +--------------+ 3 8200 0000
  77  *  | CPU 2 CSRs   |
  78  *  +--------------+ 3 8300 0000
  79  *  | CPU 3 CSRs   |
  80  *  +--------------+ 3 8400 0000
  81  *  | CPU Reserved |
  82  *  +--------------+ 3 8700 0000
  83  *  | Mem Reserved |
  84  *  +--------------+ 3 8800 0000
  85  *  | Mem 0 CSRs   |
  86  *  +--------------+ 3 8900 0000
  87  *  | Mem 1 CSRs   |
  88  *  +--------------+ 3 8a00 0000
  89  *  | Mem 2 CSRs   |
  90  *  +--------------+ 3 8b00 0000
  91  *  | Mem 3 CSRs   |
  92  *  +--------------+ 3 8c00 0000
  93  *  | Mem Reserved |
  94  *  +--------------+ 3 8e00 0000
  95  *  | PCI Bridge   |
  96  *  +--------------+ 3 8f00 0000
  97  *  | Expansion IO |
  98  *  +--------------+ 3 9000 0000
  99  *
 100  *
 101  */
 102 #define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
 103 #define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
 104 #define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
 105 #define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
 106 #define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
 107 #define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
 108 #define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
 109 #define T2_MEM3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
 110
 111
 112 /*
 113  * Sable CPU Module CSRS
 114  *
 115  * These are CSRs for hardware other than the CPU chip on the CPU module.
 116  * The CPU module has Backup Cache control logic, Cbus control logic, and
 117  * interrupt control logic on it.  There is a duplicate tag store to speed
 118  * up maintaining cache coherency.
 119  */
 120
 121 struct sable_cpu_csr {
 122   unsigned long bcc;     long fill_00[3]; /* Backup Cache Control */
 123   unsigned long bcce;    long fill_01[3]; /* Backup Cache Correctable Error */
 124   unsigned long bccea;   long fill_02[3]; /* B-Cache Corr Err Address Latch */
 125   unsigned long bcue;    long fill_03[3]; /* B-Cache Uncorrectable Error */
 126   unsigned long bcuea;   long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
 127   unsigned long dter;    long fill_05[3]; /* Duplicate Tag Error */
 128   unsigned long cbctl;   long fill_06[3]; /* CBus Control */
 129   unsigned long cbe;     long fill_07[3]; /* CBus Error */
 130   unsigned long cbeal;   long fill_08[3]; /* CBus Error Addr Latch low */
 131   unsigned long cbeah;   long fill_09[3]; /* CBus Error Addr Latch high */
 132   unsigned long pmbx;    long fill_10[3]; /* Processor Mailbox */
 133   unsigned long ipir;    long fill_11[3]; /* Inter-Processor Int Request */
 134   unsigned long sic;     long fill_12[3]; /* System Interrupt Clear */
 135   unsigned long adlk;    long fill_13[3]; /* Address Lock (LDxL/STxC) */
 136   unsigned long madrl;   long fill_14[3]; /* CBus Miss Address */
 137   unsigned long rev;     long fill_15[3]; /* CMIC Revision */
 138 };
 139
 140 /*
 141  * Data structure for handling T2 machine checks:
 142  */
 143 struct el_t2_frame_header {
 144         unsigned int    elcf_fid;       /* Frame ID (from above) */
 145         unsigned int    elcf_size;      /* Size of frame in bytes */
 146 };
 147
 148 struct el_t2_procdata_mcheck {
 149         unsigned long   elfmc_paltemp[32];      /* PAL TEMP REGS. */
 150         /* EV4-specific fields */
 151         unsigned long   elfmc_exc_addr; /* Addr of excepting insn. */
 152         unsigned long   elfmc_exc_sum;  /* Summary of arith traps. */
 153         unsigned long   elfmc_exc_mask; /* Exception mask (from exc_sum). */
 154         unsigned long   elfmc_iccsr;    /* IBox hardware enables. */
 155         unsigned long   elfmc_pal_base; /* Base address for PALcode. */
 156         unsigned long   elfmc_hier;     /* Hardware Interrupt Enable. */
 157         unsigned long   elfmc_hirr;     /* Hardware Interrupt Request. */
 158         unsigned long   elfmc_mm_csr;   /* D-stream fault info. */
 159         unsigned long   elfmc_dc_stat;  /* D-cache status (ECC/Parity Err). */
 160         unsigned long   elfmc_dc_addr;  /* EV3 Phys Addr for ECC/DPERR. */
 161         unsigned long   elfmc_abox_ctl; /* ABox Control Register. */
 162         unsigned long   elfmc_biu_stat; /* BIU Status. */
 163         unsigned long   elfmc_biu_addr; /* BUI Address. */
 164         unsigned long   elfmc_biu_ctl;  /* BIU Control. */
 165         unsigned long   elfmc_fill_syndrome; /* For correcting ECC errors. */
 166         unsigned long   elfmc_fill_addr;/* Cache block which was being read. */
 167         unsigned long   elfmc_va;       /* Effective VA of fault or miss. */
 168         unsigned long   elfmc_bc_tag;   /* Backup Cache Tag Probe Results. */
 169 };
 170
 171 /*
 172  * Sable processor specific Machine Check Data segment.
 173  */
 174
 175 struct el_t2_logout_header {
 176         unsigned int    elfl_size;      /* size in bytes of logout area. */
 177         int             elfl_sbz1:31;   /* Should be zero. */
 178         char            elfl_retry:1;   /* Retry flag. */
 179         unsigned int    elfl_procoffset; /* Processor-specific offset. */
 180         unsigned int    elfl_sysoffset;  /* Offset of system-specific. */
 181         unsigned int    elfl_error_type;        /* PAL error type code. */
 182         unsigned int    elfl_frame_rev;         /* PAL Frame revision. */
 183 };
 184 struct el_t2_sysdata_mcheck {
 185         unsigned long    elcmc_bcc;           /* CSR 0 */
 186         unsigned long    elcmc_bcce;          /* CSR 1 */
 187         unsigned long    elcmc_bccea;      /* CSR 2 */
 188         unsigned long    elcmc_bcue;          /* CSR 3 */
 189         unsigned long    elcmc_bcuea;      /* CSR 4 */
 190         unsigned long    elcmc_dter;          /* CSR 5 */
 191         unsigned long    elcmc_cbctl;      /* CSR 6 */
 192         unsigned long    elcmc_cbe;           /* CSR 7 */
 193         unsigned long    elcmc_cbeal;      /* CSR 8 */
 194         unsigned long    elcmc_cbeah;      /* CSR 9 */
 195         unsigned long    elcmc_pmbx;          /* CSR 10 */
 196         unsigned long    elcmc_ipir;          /* CSR 11 */
 197         unsigned long    elcmc_sic;           /* CSR 12 */
 198         unsigned long    elcmc_adlk;          /* CSR 13 */
 199         unsigned long    elcmc_madrl;      /* CSR 14 */
 200         unsigned long    elcmc_crrev4;     /* CSR 15 */
 201 };
 202
 203 /*
 204  * Sable memory error frame - sable pfms section 3.42
 205  */
 206 struct el_t2_data_memory {
 207         struct  el_t2_frame_header elcm_hdr;    /* ID$MEM-FERR = 0x08 */
 208         unsigned int  elcm_module;      /* Module id. */
 209         unsigned int  elcm_res04;       /* Reserved. */
 210         unsigned long elcm_merr;        /* CSR0: Error Reg 1. */
 211         unsigned long elcm_mcmd1;       /* CSR1: Command Trap 1. */
 212         unsigned long elcm_mcmd2;       /* CSR2: Command Trap 2. */
 213         unsigned long elcm_mconf;       /* CSR3: Configuration. */
 214         unsigned long elcm_medc1;       /* CSR4: EDC Status 1. */
 215         unsigned long elcm_medc2;       /* CSR5: EDC Status 2. */
 216         unsigned long elcm_medcc;       /* CSR6: EDC Control. */
 217         unsigned long elcm_msctl;       /* CSR7: Stream Buffer Control. */
 218         unsigned long elcm_mref;        /* CSR8: Refresh Control. */
 219         unsigned long elcm_filter;      /* CSR9: CRD Filter Control. */
 220 };
 221
 222
 223 /*
 224  * Sable other CPU error frame - sable pfms section 3.43
 225  */
 226 struct el_t2_data_other_cpu {
 227         short         elco_cpuid;       /* CPU ID */
 228         short         elco_res02[3];
 229         unsigned long elco_bcc; /* CSR 0 */
 230         unsigned long elco_bcce;        /* CSR 1 */
 231         unsigned long elco_bccea;       /* CSR 2 */
 232         unsigned long elco_bcue;        /* CSR 3 */
 233         unsigned long elco_bcuea;       /* CSR 4 */
 234         unsigned long elco_dter;        /* CSR 5 */
 235         unsigned long elco_cbctl;       /* CSR 6 */
 236         unsigned long elco_cbe; /* CSR 7 */
 237         unsigned long elco_cbeal;       /* CSR 8 */
 238         unsigned long elco_cbeah;       /* CSR 9 */
 239         unsigned long elco_pmbx;        /* CSR 10 */
 240         unsigned long elco_ipir;        /* CSR 11 */
 241         unsigned long elco_sic; /* CSR 12 */
 242         unsigned long elco_adlk;        /* CSR 13 */
 243         unsigned long elco_madrl;       /* CSR 14 */
 244         unsigned long elco_crrev4;      /* CSR 15 */
 245 };
 246
 247 /*
 248  * Sable other CPU error frame - sable pfms section 3.44
 249  */
 250 struct el_t2_data_t2{
 251         struct el_t2_frame_header elct_hdr;     /* ID$T2-FRAME */
 252         unsigned long elct_iocsr;       /* IO Control and Status Register */
 253         unsigned long elct_cerr1;       /* Cbus Error Register 1 */
 254         unsigned long elct_cerr2;       /* Cbus Error Register 2 */
 255         unsigned long elct_cerr3;       /* Cbus Error Register 3 */
 256         unsigned long elct_perr1;       /* PCI Error Register 1 */
 257         unsigned long elct_perr2;       /* PCI Error Register 2 */
 258         unsigned long elct_hae0_1;      /* High Address Extension Register 1 */
 259         unsigned long elct_hae0_2;      /* High Address Extension Register 2 */
 260         unsigned long elct_hbase;       /* High Base Register */
 261         unsigned long elct_wbase1;      /* Window Base Register 1 */
 262         unsigned long elct_wmask1;      /* Window Mask Register 1 */
 263         unsigned long elct_tbase1;      /* Translated Base Register 1 */
 264         unsigned long elct_wbase2;      /* Window Base Register 2 */
 265         unsigned long elct_wmask2;      /* Window Mask Register 2 */
 266         unsigned long elct_tbase2;      /* Translated Base Register 2 */
 267         unsigned long elct_tdr0;        /* TLB Data Register 0 */
 268         unsigned long elct_tdr1;        /* TLB Data Register 1 */
 269         unsigned long elct_tdr2;        /* TLB Data Register 2 */
 270         unsigned long elct_tdr3;        /* TLB Data Register 3 */
 271         unsigned long elct_tdr4;        /* TLB Data Register 4 */
 272         unsigned long elct_tdr5;        /* TLB Data Register 5 */
 273         unsigned long elct_tdr6;        /* TLB Data Register 6 */
 274         unsigned long elct_tdr7;        /* TLB Data Register 7 */
 275 };
 276
 277 /*
 278  * Sable error log data structure - sable pfms section 3.40
 279  */
 280 struct el_t2_data_corrected {
 281         unsigned long elcpb_biu_stat;
 282         unsigned long elcpb_biu_addr;
 283         unsigned long elcpb_biu_ctl;
 284         unsigned long elcpb_fill_syndrome;
 285         unsigned long elcpb_fill_addr;
 286         unsigned long elcpb_bc_tag;
 287 };
 288
 289 /*
 290  * Sable error log data structure
 291  * Note there are 4 memory slots on sable (see t2.h)
 292  */
 293 struct el_t2_frame_mcheck {
 294         struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */
 295         struct el_t2_logout_header elfmc_hdr;
 296         struct el_t2_procdata_mcheck elfmc_procdata;
 297         struct el_t2_sysdata_mcheck elfmc_sysdata;
 298         struct el_t2_data_t2 elfmc_t2data;
 299         struct el_t2_data_memory elfmc_memdata[4];
 300         struct el_t2_frame_header elfmc_footer; /* empty */
 301 };
 302
 303
 304 /*
 305  * Sable error log data structures on memory errors
 306  */
 307 struct el_t2_frame_corrected {
 308         struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */
 309         struct el_t2_logout_header elfcc_hdr;
 310         struct el_t2_data_corrected elfcc_procdata;
 311 /*      struct el_t2_data_t2 elfcc_t2data;              */
 312 /*      struct el_t2_data_memory elfcc_memdata[4];      */
 313         struct el_t2_frame_header elfcc_footer; /* empty */
 314 };
 315
 316
 317 #ifdef __KERNEL__
 318
 319 #ifndef __EXTERN_INLINE
 320 #define __EXTERN_INLINE extern inline
 321 #define __IO_EXTERN_INLINE
 322 #endif
 323
 324 /*
 325  * Translate physical memory address as seen on (PCI) bus into
 326  * a kernel virtual address and vv.
 327  */
 328
 329 __EXTERN_INLINE unsigned long t2_virt_to_bus(void * address)
 330 {
 331         return virt_to_phys(address) + T2_DMA_WIN_BASE;
 332 }
 333
 334 __EXTERN_INLINE void * t2_bus_to_virt(unsigned long address)
 335 {
 336         return phys_to_virt(address - T2_DMA_WIN_BASE);
 337 }
 338
 339 /*
 340  * I/O functions:
 341  *
 342  * T2 (the core logic PCI/memory support chipset for the SABLE
 343  * series of processors uses a sparse address mapping scheme to
 344  * get at PCI memory and I/O.
 345  */
 346
 347 #define vip     volatile int *
 348 #define vuip    volatile unsigned int *
 349
 350 __EXTERN_INLINE unsigned int t2_inb(unsigned long addr)
 351 {
 352         long result = *(vip) ((addr << 5) + T2_IO + 0x00);
 353         return __kernel_extbl(result, addr & 3);
 354 }
 355
 356 __EXTERN_INLINE void t2_outb(unsigned char b, unsigned long addr)
 357 {
 358         unsigned long w;
 359
 360         w = __kernel_insbl(b, addr & 3);
 361         *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
 362         mb();
 363 }
 364
 365 __EXTERN_INLINE unsigned int t2_inw(unsigned long addr)
 366 {
 367         long result = *(vip) ((addr << 5) + T2_IO + 0x08);
 368         return __kernel_extwl(result, addr & 3);
 369 }
 370
 371 __EXTERN_INLINE void t2_outw(unsigned short b, unsigned long addr)
 372 {
 373         unsigned long w;
 374
 375         w = __kernel_inswl(b, addr & 3);
 376         *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
 377         mb();
 378 }
 379
 380 __EXTERN_INLINE unsigned int t2_inl(unsigned long addr)
 381 {
 382         return *(vuip) ((addr << 5) + T2_IO + 0x18);
 383 }
 384
 385 __EXTERN_INLINE void t2_outl(unsigned int b, unsigned long addr)
 386 {
 387         *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
 388         mb();
 389 }
 390
 391
 392 /*
 393  * Memory functions.
 394  *
 395  * For reading and writing 8 and 16 bit quantities we need to
 396  * go through one of the three sparse address mapping regions
 397  * and use the HAE_MEM CSR to provide some bits of the address.
 398  * The following few routines use only sparse address region 1
 399  * which gives 1Gbyte of accessible space which relates exactly
 400  * to the amount of PCI memory mapping *into* system address space.
 401  * See p 6-17 of the specification but it looks something like this:
 402  *
 403  * 21164 Address:
 404  *
 405  *          3         2         1
 406  * 9876543210987654321098765432109876543210
 407  * 1ZZZZ0.PCI.QW.Address............BBLL
 408  *
 409  * ZZ = SBZ
 410  * BB = Byte offset
 411  * LL = Transfer length
 412  *
 413  * PCI Address:
 414  *
 415  * 3         2         1
 416  * 10987654321098765432109876543210
 417  * HHH....PCI.QW.Address........ 00
 418  *
 419  * HHH = 31:29 HAE_MEM CSR
 420  *
 421  */
 422
 423 __EXTERN_INLINE unsigned long t2_readb(unsigned long addr)
 424 {
 425         unsigned long result, msb;
 426
 427         msb = addr & 0xE0000000;
 428         addr &= T2_MEM_R1_MASK;
 429         set_hae(msb);
 430
 431         result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
 432         return __kernel_extbl(result, addr & 3);
 433 }
 434
 435 __EXTERN_INLINE unsigned long t2_readw(unsigned long addr)
 436 {
 437         unsigned long result, msb;
 438
 439         msb = addr & 0xE0000000;
 440         addr &= T2_MEM_R1_MASK;
 441         set_hae(msb);
 442
 443         result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
 444         return __kernel_extwl(result, addr & 3);
 445 }
 446
 447 /* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
 448 __EXTERN_INLINE unsigned long t2_readl(unsigned long addr)
 449 {
 450         unsigned long msb;
 451
 452         msb = addr & 0xE0000000;
 453         addr &= T2_MEM_R1_MASK;
 454         set_hae(msb);
 455
 456         return *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
 457 }
 458
 459 __EXTERN_INLINE unsigned long t2_readq(unsigned long addr)
 460 {
 461         unsigned long r0, r1, work, msb;
 462
 463         msb = addr & 0xE0000000;
 464         addr &= T2_MEM_R1_MASK;
 465         set_hae(msb);
 466
 467         work = (addr << 5) + T2_SPARSE_MEM + 0x18;
 468         r0 = *(vuip)(work);
 469         r1 = *(vuip)(work + (4 << 5));
 470         return r1 << 32 | r0;
 471 }
 472
 473 __EXTERN_INLINE void t2_writeb(unsigned char b, unsigned long addr)
 474 {
 475         unsigned long msb, w;
 476
 477         msb = addr & 0xE0000000;
 478         addr &= T2_MEM_R1_MASK;
 479         set_hae(msb);
 480
 481         w = __kernel_insbl(b, addr & 3);
 482         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
 483 }
 484
 485 __EXTERN_INLINE void t2_writew(unsigned short b, unsigned long addr)
 486 {
 487         unsigned long msb, w;
 488
 489         msb = addr & 0xE0000000;
 490         addr &= T2_MEM_R1_MASK;
 491         set_hae(msb);
 492
 493         w = __kernel_inswl(b, addr & 3);
 494         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
 495 }
 496
 497 /* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
 498 __EXTERN_INLINE void t2_writel(unsigned int b, unsigned long addr)
 499 {
 500         unsigned long msb;
 501
 502         msb = addr & 0xE0000000;
 503         addr &= T2_MEM_R1_MASK;
 504         set_hae(msb);
 505
 506         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
 507 }
 508
 509 __EXTERN_INLINE void t2_writeq(unsigned long b, unsigned long addr)
 510 {
 511         unsigned long msb, work;
 512
 513         msb = addr & 0xE0000000;
 514         addr &= T2_MEM_R1_MASK;
 515         set_hae(msb);
 516
 517         work = (addr << 5) + T2_SPARSE_MEM + 0x18;
 518         *(vuip)work = b;
 519         *(vuip)(work + (4 << 5)) = b >> 32;
 520 }
 521
 522 __EXTERN_INLINE unsigned long t2_ioremap(unsigned long addr)
 523 {
 524         return addr;
 525 }
 526
 527 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
 528 {
 529         return (long)addr >= 0;
 530 }
 531
 532 #undef vip
 533 #undef vuip
 534
 535 #ifdef __WANT_IO_DEF
 536
 537 #define virt_to_bus     t2_virt_to_bus
 538 #define bus_to_virt     t2_bus_to_virt
 539 #define __inb           t2_inb
 540 #define __inw           t2_inw
 541 #define __inl           t2_inl
 542 #define __outb          t2_outb
 543 #define __outw          t2_outw
 544 #define __outl          t2_outl
 545 #define __readb         t2_readb
 546 #define __readw         t2_readw
 547 #define __readl         t2_readl
 548 #define __readq         t2_readq
 549 #define __writeb        t2_writeb
 550 #define __writew        t2_writew
 551 #define __writel        t2_writel
 552 #define __writeq        t2_writeq
 553 #define __ioremap       t2_ioremap
 554 #define __is_ioaddr     t2_is_ioaddr
 555
 556 #define inb(port) \
 557   (__builtin_constant_p((port))?__inb(port):_inb(port))
 558 #define outb(x, port) \
 559   (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 560
 561 #endif /* __WANT_IO_DEF */
 562
 563 #ifdef __IO_EXTERN_INLINE
 564 #undef __EXTERN_INLINE
 565 #undef __IO_EXTERN_INLINE
 566 #endif
 567
 568 #endif /* __KERNEL__ */
 569
 570 #endif /* __ALPHA_T2__H__ */