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2 Introduction to GCC Inline Asm
6 http://www.geocities.com/SiliconValley/Ridge/2544/
8 Wed Sep 13 19:18:50 UTC
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11 * `as' and AT&T Syntax
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14 The GNU C Compiler uses the assembler `as' as a backend. This
15 assembler uses AT&T syntax. Here is a brief overview of the syntax.
16 For more information about `as', look in the system info
21 nemonic source, destination (opposite to intel syntax)
23 - as prefixes registers with `%', and prefixes numeric constants
26 - Effective addresses use the following general syntax;
28 SECTION:DISP(BASE, INDEX, SCALE)
30 As in other assemblers, any one or more of these components may be
31 ommited, within constraints of valid intel instruction syntax.
32 The above syntax was shamelessly copied from the info pages under
33 the i386 dependant features of as.
35 - As suffixes the assembler nemonics with a letter indicating the
36 operand sizes ('b' for byte, 'w' for word, 'l' for long word).
37 Read the info pages for more information such as suffixes for
38 floating point registers etc.
40 Example code (raw asm, not gcc inline)
41 --------------------------------------------------------------------
42 movl %eax, %ebx /* intel: mov ebx, eax */
43 movl $56, %esi /* intel: mov esi, 56 */
44 movl %ecx, $label(%edx,%ebx,$4) /* intel: mov [edx+ebx*4+4], ecx */
45 movb %ah, (%ebx) /* intel: mov [ebx], ah */
46 --------------------------------------------------------------------
48 Notice that as uses C comment syntax. As can also use `#' that
49 works the same way as `;' in most other intel assemblers.
51 Above code in inline asm
52 --------------------------------------------------------------------
53 __asm__ ("movl %eax, %ebx\n\t"
55 "movl %ecx, $label(%edx,%ebx,$4)\n\t"
57 --------------------------------------------------------------------
59 Notice that in the above example, the __ prefixing and suffixing asm
60 are not neccesary, but may prevent name conflicts in your program.
61 You can read more about this in [C enxtensions|extended asm] under
62 the info documentation for gcc.
64 Also notice the '\n\t' at the end of each line except the last, and
65 that each line is inclosed in quotes. This is because gcc sends
66 each as instruction to as as a string. The newline/tab combination
67 is required so that the lines are fed to as according to the correct
68 format (recall that each line in asssembler is indented one tab
69 stop, generally 8 characters).
71 You can also use labels from your C code (variable names and such).
72 In Linux, underscores prefixing C variables are not Necessary in
77 __asm__ ("movl Cvariable, %eax"); # Cvariable contents > eax
78 __asm__ ("movl $Cvariable, %ebx"); # ebx ---> Cvariable
81 Notice that in the documentation for DJGPP, it will say that the
82 underscore is necessary. The difference is do to the differences
83 between djgpp RDOFF format and Linux's ELF format. I am not
84 certain, but I think that the old Linux a.out object files also use
85 underscores (please contact me if you have comments on this).
88 ------------------------------------------------------------------------
90 The code in the above example will most probably cause conflicts
91 with the rest of your C code, especially with compiler optimizations
92 (recall that gcc is an optimizing compiler). Any registers used in
93 your code may be used to hold C variable data from the rest of your
94 program. You would not want to inadvertently modify the register
95 without telling gcc to take this into account when compiling. This
96 is where extended asm comes into play.
98 Extended asm allows you to specify input registers, output
99 registers, and clobbered registers as interface information to your
100 block of asm code. You can even allow gcc to choose actual physical
101 CPU registers automatically, that probably fit into gcc's
102 optimization scheme better. An example will demonstrate extended
106 --------------------------------------------------------------------
110 int operand1, operand2, sum, accumulator;
112 operand1 = rand (); operand2 = rand ();
114 __asm__ ("movl %1, %0\n\t"
116 : "=r" (sum) /* output operands */
117 : "r" (operand1), "r" (operand2) /* input operands */
118 : "0"); /* clobbered operands */
122 __asm__ ("addl %1, %0\n\t"
125 : "0" (accumulator), "g" (operand1), "r" (operand2)
129 --------------------------------------------------------------------
131 The first the line that begins with ':' specifies the output
132 operands, the second indicates the input operands, and the last
133 indicates the clobbered operands. the "r", "g", and "0" are
134 examples of constraints. Output constraints must be prefixed with
135 an '=', as in "=r" (= is a constraint modifier, indicating write
136 only). Input and output constraints must have its correspoding C
137 argument included with it enclosed in parenthisis (this must not be
138 done with the clobbered line, I figured this out after an hour of
139 fustration). "r" means assign a general register register for the
140 argument, "g" means to assign any register, memory or immediate
143 Notice the use of "0", "1", "2" etc. These are used to ensure that
144 when the same variable is indicated in more than one place in the
145 extended asm, that is variable is only `mapped' to one register. If
146 you had merely used another "r" for example, the compiler may or may
147 not assign this variable to the same register as before. You can
148 surmise from this that "0" refers to the first register assigned to
149 a variable, "1" the second etc. When these registers are used in
150 the asm code, they are refered to as "%0", "%1" etc.
152 Summary of constraints. (copied from the system info documentation
154 --------------------------------------------------------------------
157 A memory operand is allowed, with any kind of address that the
158 machine supports in general.
162 A memory operand is allowed, but only if the address is
163 "offsettable". This means that adding a small integer
164 (actually, the width in bytes of the operand, as determined by
165 its machine mode) may be added to the address and the result is
166 also a valid memory address.
168 For example, an address which is constant is offsettable; so is
169 an address that is the sum of a register and a constant (as long
170 as a slightly larger constant is also within the range of
171 address-offsets supported by the machine); but an autoincrement
172 or autodecrement address is not offsettable. More complicated
173 indirect/indexed addresses may or may not be offsettable
174 depending on the other addressing modes that the machine
177 Note that in an output operand which can be matched by another
178 operand, the constraint letter `o' is valid only when
179 accompanied by both `<' (if the target machine has predecrement
180 addressing) and `>' (if the target machine has preincrement
185 A memory operand that is not offsettable. In other words,
186 anything that would fit the `m' constraint but not the `o'
191 A memory operand with autodecrement addressing (either
192 predecrement or postdecrement) is allowed.
196 A memory operand with autoincrement addressing (either
197 preincrement or postincrement) is allowed.
201 A register operand is allowed provided that it is in a general
206 Other letters can be defined in machine-dependent fashion to
207 stand for particular classes of registers. `d', `a' and `f' are
208 defined on the 68000/68020 to stand for data, address and
209 floating point registers.
213 An immediate integer operand (one with constant value) is
214 allowed. This includes symbolic constants whose values will be
215 known only at assembly time.
219 An immediate integer operand with a known numeric value is
220 allowed. Many systems cannot support assembly-time constants
221 for operands less than a word wide. Constraints for these
222 operands should use `n' rather than `i'.
224 `I', `J', `K', ... `P'
226 Other letters in the range `I' through `P' may be defined in a
227 machine-dependent fashion to permit immediate integer operands
228 with explicit integer values in specified ranges. For example,
229 on the 68000, `I' is defined to stand for the range of values 1
230 to 8. This is the range permitted as a shift count in the shift
235 An immediate floating operand (expression code `const_double')
236 is allowed, but only if the target floating point format is the
237 same as that of the host machine (on which the compiler is
242 An immediate floating operand (expression code `const_double')
247 `G' and `H' may be defined in a machine-dependent fashion to
248 permit immediate floating operands in particular ranges of
253 An immediate integer operand whose value is not an explicit
256 This might appear strange; if an insn allows a constant operand
257 with a value not known at compile time, it certainly must allow
258 any known value. So why use `s' instead of `i'? Sometimes it
259 allows better code to be generated.
261 For example, on the 68000 in a fullword instruction it is
262 possible to use an immediate operand; but if the immediate value
263 is between -128 and 127, better code results from loading the
264 value into a register and using the register. This is because
265 the load into the register can be done with a `moveq'
266 instruction. We arrange for this to happen by defining the
267 letter `K' to mean "any integer outside the range -128 to 127",
268 and then specifying `Ks' in the operand constraints.
272 Any register, memory or immediate integer operand is allowed,
273 except for registers that are not general registers.
277 Any operand whatsoever is allowed, even if it does not satisfy
278 `general_operand'. This is normally used in the constraint of a
279 `match_scratch' when certain alternatives will not actually
280 require a scratch register.
282 `0', `1', `2', ... `9'
284 An operand that matches the specified operand number is allowed.
285 If a digit is used together with letters within the same
286 alternative, the digit should come last.
288 This is called a "matching constraint" and what it really means
289 is that the assembler has only a single operand that fills two
290 roles considered separate in the RTL insn. For example, an add
291 insn has two input operands and one output operand in the RTL,
292 but on most CISC machines an add instruction really has only two
293 operands, one of them an input-output operand:
297 Matching constraints are used in these circumstances. More
298 precisely, the two operands that match must include one
299 input-only operand and one output-only operand. Moreover, the
300 digit must be a smaller number than the number of the operand
301 that uses it in the constraint.
303 For operands to match in a particular case usually means that
304 they are identical-looking RTL expressions. But in a few
305 special cases specific kinds of dissimilarity are allowed. For
306 example, `*x' as an input operand will match `*x++' as an output
307 operand. For proper results in such cases, the output template
308 should always use the output-operand's number when printing the
313 An operand that is a valid memory address is allowed. This is
314 for "load address" and "push address" instructions.
316 `p' in the constraint must be accompanied by `address_operand'
317 as the predicate in the `match_operand'. This predicate
318 interprets the mode specified in the `match_operand' as the mode
319 of the memory reference for which the address would be valid.
321 `Q', `R', `S', ... `U'
323 Letters in the range `Q' through `U' may be defined in a
324 machine-dependent fashion to stand for arbitrary operand types.
325 The machine description macro `EXTRA_CONSTRAINT' is passed the
326 operand as its first argument and the constraint letter as its
329 A typical use for this would be to distinguish certain types of
330 memory references that affect other insn operands.
332 Do not define these constraint letters to accept register
333 references (`reg'); the reload pass does not expect this and
334 would not handle it properly.
336 In order to have valid assembler code, each operand must satisfy
337 its constraint. But a failure to do so does not prevent the
338 pattern from applying to an insn. Instead, it directs the
339 compiler to modify the code so that the constraint will be
340 satisfied. Usually this is done by copying an operand into a
343 Contrast, therefore, the two instruction patterns that follow:
346 [(set (match_operand:SI 0 "general_operand" "=r")
347 (plus:SI (match_dup 0)
348 (match_operand:SI 1 "general_operand" "r")))]
352 which has two operands, one of which must appear in two places,
356 [(set (match_operand:SI 0 "general_operand" "=r")
357 (plus:SI (match_operand:SI 1 "general_operand" "0")
358 (match_operand:SI 2 "general_operand" "r")))]
362 which has three operands, two of which are required by a
363 constraint to be identical. If we are considering an insn of
368 (plus:SI (reg:SI 6) (reg:SI 109)))
371 the first pattern would not apply at all, because this insn does
372 not contain two identical subexpressions in the right place.
373 The pattern would say, "That does not look like an add
374 instruction; try other patterns." The second pattern would say,
375 "Yes, that's an add instruction, but there is something wrong
376 with it." It would direct the reload pass of the compiler to
377 generate additional insns to make the constraint true. The
378 results might look like this:
381 (set (reg:SI 3) (reg:SI 6))
386 (plus:SI (reg:SI 3) (reg:SI 109)))
389 It is up to you to make sure that each operand, in each pattern,
390 has constraints that can handle any RTL expression that could be
391 present for that operand. (When multiple alternatives are in
392 use, each pattern must, for each possible combination of operand
393 expressions, have at least one alternative which can handle that
394 combination of operands.) The constraints don't need to *allow*
395 any possible operand--when this is the case, they do not
396 constrain--but they must at least point the way to reloading any
397 possible operand so that it will fit.
399 * If the constraint accepts whatever operands the predicate
400 permits, there is no problem: reloading is never necessary for
403 For example, an operand whose constraints permit everything
404 except registers is safe provided its predicate rejects
407 An operand whose predicate accepts only constant values is
408 safe provided its constraints include the letter `i'. If any
409 possible constant value is accepted, then nothing less than
410 `i' will do; if the predicate is more selective, then the
411 constraints may also be more selective.
413 * Any operand expression can be reloaded by copying it into a
414 register. So if an operand's constraints allow some kind of
415 register, it is certain to be safe. It need not permit all
416 classes of registers; the compiler knows how to copy a
417 register into another register of the proper class in order to
418 make an instruction valid.
420 * A nonoffsettable memory reference can be reloaded by copying
421 the address into a register. So if the constraint uses the
422 letter `o', all memory references are taken care of.
424 * A constant operand can be reloaded by allocating space in
425 memory to hold it as preinitialized data. Then the memory
426 reference can be used in place of the constant. So if the
427 constraint uses the letters `o' or `m', constant operands are
430 * If the constraint permits a constant and a pseudo register
431 used in an insn was not allocated to a hard register and is
432 equivalent to a constant, the register will be replaced with
433 the constant. If the predicate does not permit a constant and
434 the insn is re-recognized for some reason, the compiler will
435 crash. Thus the predicate must always recognize any objects
436 allowed by the constraint.
438 If the operand's predicate can recognize registers, but the
439 constraint does not permit them, it can make the compiler crash.
440 When this operand happens to be a register, the reload pass will
441 be stymied, because it does not know how to copy a register
442 temporarily into memory.
444 If the predicate accepts a unary operator, the constraint
445 applies to the operand. For example, the MIPS processor at ISA
446 level 3 supports an instruction which adds two registers in
447 `SImode' to produce a `DImode' result, but only if the registers
448 are correctly sign extended. This predicate for the input
449 operands accepts a `sign_extend' of an `SImode' register. Write
450 the constraint to indicate the type of register that is required
451 for the operand of the `sign_extend'.
452 ------------------------------------------------------------------------
454 The '=' in the "=r" is a constraint modifier, you can find more
455 information about constraint modifiers, in the gcc info under
456 Machine Descriptions : Constraints : Modifiers.
458 I strongly recommend reading more in the system info documentation.
459 If you haven't had much experience with the info reader (also
460 accesable through emacs), learn it, it is an excellent source of
463 The gcc info documentation also explains how to use a specific CPU
464 register for a constraint for various hardware including the i386.
465 You can find this information under [gcc : Machine Desc :
466 Constraints : Machine Constraints] in the info documentation.
468 You can specify specific registers in your constraints, e.g. "%eax".
470 * __asm__ __volatile__
471 ------------------------------------------------------------------------
473 Because of the compilers optimization mechanism, your code may not
474 appear at exactly in the location specified by the programmer. I
475 may even be interspersed with the rest of the code. To prevent
476 this, you can use __asm__ __volotile__ instead. Like the '__' for
477 asm, these are also not needed for volatile, but can prevent name
480 ========================================================================
481 comments and suggestions <deltak@telus.net>