i386/i386.reference/BT.htm

   1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
   2 <HTML>
   3 <HEAD>
   4 <TITLE>80386 Programmer's Reference Manual -- Opcode BT</TITLE>
   5 </HEAD>
   6 <BODY>
   7 <B>up:</B> <A HREF="c17.htm">
   8 Chapter 17 -- 80386 Instruction Set</A><BR>
   9 <B>prev:</B><A HREF="BSR.htm"> BSR Bit Scan Reverse</A><BR>
  10 <B>next:</B><A HREF="BTC.htm"> BTC Bit Test and Complement</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>BT -- Bit Test</H1>
  15
  16 <PRE>
  17 Opcode         Instruction     Clocks    Description
  18
  19 0F  A3         BT r/m16,r16    3/12      Save bit in carry flag
  20 0F  A3         BT r/m32,r32    3/12      Save bit in carry flag
  21 0F  BA /4 ib   BT r/m16,imm8   3/6       Save bit in carry flag
  22 0F  BA /4 ib   BT r/m32,imm8   3/6       Save bit in carry flag
  23 </PRE>
  24
  25 <H2>Operation</H2>
  26
  27 <PRE>
  28 CF := BIT[LeftSRC, RightSRC];
  29 </PRE>
  30
  31 <H2>Description</H2>
  32
  33 BT saves the value of the bit indicated by the base (first operand) and the
  34 bit offset (second operand) into the carry flag.
  35
  36 <H2>Flags Affected</H2>
  37
  38 CF as described above
  39
  40 <H2>Protected Mode Exceptions</H2>
  41
  42 #GP(0) for an illegal memory operand effective address in the CS, DS, ES,
  43 FS, or GS segments; #SS(0) for an illegal address in the SS segment;
  44 #PF(fault-code) for a page fault
  45
  46 <H2>Real Address Mode Exceptions</H2>
  47
  48 Interrupt 13 if any part of the operand would lie outside of the effective
  49 address space from 0 to 0FFFFH
  50
  51 <H2>Virtual 8086 Mode Exceptions</H2>
  52
  53 Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
  54
  55 <H2>Notes</H2>
  56
  57 The index of the selected bit can be given by the immediate constant in the
  58 instruction or by a value in a general register. Only an 8-bit immediate
  59 value is used in the instruction. This operand is taken modulo 32, so the
  60 range of immediate bit offsets is 0..31. This allows any bit within a
  61 register to be selected. For memory bit strings, this immediate field gives
  62 only the bit offset within a word or doubleword. Immediate bit offsets
  63 larger than 31 are supported by using the immediate bit offset field in
  64 combination with the displacement field of the memory operand. The low-order
  65 3 to 5 bits of the immediate bit offset are stored in the immediate bit
  66 offset field, and the high-order 27 to 29 bits are shifted and combined with
  67 the byte displacement in the addressing mode.
  68 <P>
  69 When accessing a bit in memory, the 80386 may access four bytes starting
  70 from the memory address given by:
  71 <PRE>
  72    Effective Address + (4 * (BitOffset DIV 32))
  73 </PRE>
  74 for a 32-bit operand size, or two bytes starting from the memory address
  75 given by:
  76 <PRE>
  77    Effective Address + (2 * (BitOffset DIV 16))
  78 </PRE>
  79 for a 16-bit operand size. It may do so even when only a single byte needs
  80 to be accessed in order to reach the given bit. You must therefore avoid
  81 referencing areas of memory close to address space holes. In particular,
  82 avoid references to memory-mapped I/O registers. Instead, use the
  83 <A HREF="MOV.htm">MOV</A>
  84 instructions to load from or store to these addresses, and use the register
  85 form of these instructions to manipulate the data.
  86
  87
  88 <P>
  89 <HR>
  90 <P>
  91 <B>up:</B> <A HREF="c17.htm">
  92 Chapter 17 -- 80386 Instruction Set</A><BR>
  93 <B>prev:</B><A HREF="BSR.htm"> BSR Bit Scan Reverse</A><BR>
  94 <B>next:</B><A HREF="BTC.htm"> BTC Bit Test and Complement</A>
  95 </BODY>