i386/i386.reference/LAR.htm

   1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
   2 <HTML>
   3 <HEAD>
   4 <TITLE>80386 Programmer's Reference Manual -- Opcode LAR</TITLE>
   5 </HEAD>
   6 <BODY>
   7 <B>up:</B> <A HREF="c17.htm">
   8 Chapter 17 -- 80386 Instruction Set</A><BR>
   9 <B>prev:</B><A HREF="LAHF.htm"> LAHF Load Flags into AH Register</A><BR>
  10 <B>next:</B><A HREF="LEA.htm"> LEA Load Effective Address</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>LAR -- Load Access Rights Byte</H1>
  15
  16 <PRE>
  17 Opcode        Instruction      Clocks      Description
  18
  19 0F  02 /r     LAR r16,r/m16    pm=15/16    r16 := r/m16 masked by FF00
  20 0F  02 /r     LAR r32,r/m32    pm=15/16    r32 := r/m32 masked by 00FxFF00
  21 </PRE>
  22
  23 <H2>Description</H2>
  24
  25 The LAR instruction stores a marked form of the second doubleword of
  26 the descriptor for the source selector if the selector is visible at the
  27 CPL (modified by the selector's RPL) and is a valid descriptor type. The
  28 destination register is loaded with the high-order doubleword of the
  29 descriptor masked by 00FxFF00, and ZF is set to 1. The x indicates that the
  30 four bits corresponding to the upper four bits of the limit are undefined in
  31 the value loaded by LAR. If the selector is invisible or of the wrong type,
  32 ZF is cleared.
  33 <P>
  34 If the 32-bit operand size is specified, the entire 32-bit value is loaded
  35 into the 32-bit destination register. If the 16-bit operand size is
  36 specified, the lower 16-bits of this value are stored in the 16-bit
  37 destination register.
  38 <P>
  39 All code and data segment descriptors are valid for LAR.
  40 <P>
  41 The valid special segment and gate descriptor types for LAR are given
  42 in the following table:
  43
  44 <PRE>
  45 Type   Name                     Valid/Invalid
  46
  47   0    Invalid                  Invalid
  48   1    Available 80286 TSS      Valid
  49   2    LDT                      Valid
  50   3    Busy 80286 TSS           Valid
  51   4    80286 call gate          Valid
  52   5    80286/80386 task gate    Valid
  53   6    80286 trap gate          Valid
  54   7    80286 interrupt gate     Valid
  55   8    Invalid                  Invalid
  56   9    Available 80386 TSS      Valid
  57   A    Invalid                  Invalid
  58   B    Busy 80386 TSS           Valid
  59   C    80386 call gate          Valid
  60   D    Invalid                  Invalid
  61   E    80386 trap gate          Valid
  62   F    80386 interrupt gate     Valid
  63 </PRE>
  64
  65 <H2>Flags Affected</H2>
  66
  67 ZF as described above
  68
  69 <H2>Protected Mode Exceptions</H2>
  70
  71 #GP(0) for an illegal memory operand effective address in the CS, DS,
  72 ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment;
  73 #PF(fault-code) for a page fault
  74
  75 <H2>Real Address Mode Exceptions</H2>
  76
  77 Interrupt 6; LAR is unrecognized in Real Address Mode
  78
  79 <H2>Virtual 8086 Mode Exceptions</H2>
  80
  81 Same exceptions as in Real Address Mode
  82
  83
  84 <P>
  85 <HR>
  86 <P>
  87 <B>up:</B> <A HREF="c17.htm">
  88 Chapter 17 -- 80386 Instruction Set</A><BR>
  89 <B>prev:</B><A HREF="LAHF.htm"> LAHF Load Flags into AH Register</A><BR>
  90 <B>next:</B><A HREF="LEA.htm"> LEA Load Effective Address</A>
  91 </BODY>