i386/i386.reference/LGDT.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Opcode LGDT</TITLE>
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   8 Chapter 17 -- 80386 Instruction Set</A><BR>
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  13 <P>
  14 <H1>LGDT/LIDT -- Load Global/Interrupt Descriptor Table Register</H1>
  15
  16 <PRE>
  17 Opcode       Instruction      Clocks        Description
  18
  19 0F  01 /2    LGDT m16&32      11            Load m into GDTR
  20 0F  01 /3    LIDT m16&32      11            Load m into IDTR
  21 </PRE>
  22
  23 <H2>Operation</H2>
  24
  25 <PRE>
  26 IF instruction = LIDT
  27 THEN
  28    IF OperandSize = 16
  29    THEN IDTR.Limit:Base := m16:24 (* 24 bits of base loaded *)
  30    ELSE IDTR.Limit:Base := m16:32
  31    FI;
  32 ELSE (* instruction = LGDT *)
  33    IF OperandSize = 16
  34    THEN GDTR.Limit:Base := m16:24 (* 24 bits of base loaded *)
  35    ELSE GDTR.Limit:Base := m16:32;
  36    FI;
  37 FI;
  38 </PRE>
  39
  40 <H2>Description</H2>
  41
  42 The LGDT and LIDT instructions load a linear base address and limit
  43 value from a six-byte data operand in memory into the GDTR or IDTR,
  44 respectively. If a 16-bit operand is used with LGDT or LIDT, the
  45 register is loaded with a 16-bit limit and a 24-bit base, and the
  46 high-order eight bits of the six-byte data operand are not used. If a 32-bit
  47 operand is used, a 16-bit limit and a 32-bit base is loaded; the high-order
  48 eight bits of the six-byte operand are used as high-order base address bits.
  49 <P>
  50 The
  51 <A HREF="SGDT.htm">SGDT</A> and
  52 <A HREF="SGDT.htm">SIDT</A> instructions always store into all 48 bits of the
  53 six-byte data operand. With the 80286, the upper eight bits are undefined
  54 after
  55 <A HREF="SGDT.htm">SGDT</A> or
  56 <A HREF="SGDT.htm">SIDT</A> is executed. With the 80386, the upper eight bits
  57 are written with the high-order eight address bits, for both a 16-bit
  58 operand and a 32-bit operand. If LGDT or LIDT is used with a 16-bit
  59 operand to load the register stored by SGDT or SIDT, the upper eight
  60 bits are stored as zeros.
  61 <P>
  62 LGDT and LIDT appear in operating system software; they are not used
  63 in application programs. They are the only instructions that directly load
  64 a linear address (i.e., not a segment relative address) in 80386 Protected
  65 Mode.
  66
  67 <H2>Flags Affected</H2>
  68
  69 None
  70
  71 <H2>Protected Mode Exceptions</H2>
  72
  73 #GP(0) if the current privilege level is not 0; #UD if the source operand
  74 is a register; #GP(0) for an illegal memory operand effective address in
  75 the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in
  76 the SS segment; #PF(fault-code) for a page fault
  77
  78 <H2>Real Address Mode Exceptions</H2>
  79
  80 Interrupt 13 if any part of the operand would lie outside of the effective
  81 address space from 0 to 0FFFFH; Interrupt 6 if the source operand is a
  82 register
  83
  84 <EM>
  85 <H3>Note</H3>
  86   These instructions are valid in Real Address Mode to allow
  87   power-up initialization for Protected Mode
  88 </EM>
  89
  90 <H2>Virtual 8086 Mode Exceptions</H2>
  91
  92 Same exceptions as in Real Address Mode; #PF(fault-code) for a page
  93 fault
  94
  95
  96 <P>
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  99 <B>up:</B> <A HREF="c17.htm">
 100 Chapter 17 -- 80386 Instruction Set</A><BR>
 101 <B>prev:</B><A HREF="LEAVE.htm"> LEAVE High Level Procedure Exit</A><BR>
 102 <B>next:</B><A HREF="LGS.htm"> LGS/LSS/LDS/LES/LFS Load Full Pointer</A>
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