i386/i386.reference/s02_05.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 2.5</TITLE>
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   8 Chapter 2 -- Basic Programming Model</A><BR>
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  13 <P>
  14 <H1>2.5  Operand Selection</H1>
  15 An instruction can act on zero or more operands, which are the data
  16 manipulated by the instruction. An example of a zero-operand instruction is
  17 <A HREF="NOP.html">NOP</A> (no operation). An operand can be in any of these locations:
  18 <UL>
  19 <LI> In the instruction itself (an immediate operand)
  20 <LI> In a register (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP in the case
  21 of 32-bit operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of
  22 16-bit operands; AH, AL, BH, BL, CH, CL, DH, or DL in the case of 8-bit
  23 operands; the segment registers; or the EFLAGS register for flag
  24 operations)
  25 <LI> In memory
  26 <LI> At an I/O port
  27 </UL>
  28 Immediate operands and operands in registers can be accessed more rapidly
  29 than operands in memory since memory operands must be fetched from memory.
  30 Register operands are available in the CPU. Immediate operands are also
  31 available in the CPU, because they are prefetched as part of the
  32 instruction.
  33 <P>
  34 Of the instructions that have operands, some specify operands implicitly;
  35 others specify operands explicitly; still others use a combination of
  36 implicit and explicit specification; for example:
  37 <DL>
  38 <DT>
  39 Implicit operand: <A HREF="AAM.htm">AAM</A>
  40 <DD>
  41 By definition, <A HREF="AAM.htm">AAM</A> (ASCII adjust for multiplication) operates on the
  42 contents of the AX register.
  43 <DT>
  44 Explicit operand: <A HREF="XCHG.htm">XCHG</A> EAX, EBX
  45 <DD>
  46 The operands to be exchanged are encoded in the instruction after the
  47 opcode.
  48 <DT>
  49 Implicit and explicit operands: <A HREF="PUSH.htm">PUSH</A> COUNTER
  50 <DD>
  51 The memory variable COUNTER (the explicit operand) is copied to the top of
  52 the stack (the implicit operand).
  53 </DL>
  54 Note that most instructions have implicit operands. All arithmetic
  55 instructions, for example, update the EFLAGS register.
  56 <P>
  57 An 80386 instruction can explicitly reference one or two operands.
  58 Two-operand instructions, such as <A HREF="MOV.htm">MOV</A>, <A HREF="ADD.htm">ADD</A>, <A HREF="XOR.htm">XOR</A>, etc., generally overwrite
  59 one of the two participating operands with the result. A distinction can
  60 thus be made between the source operand (the one unaffected by the
  61 operation) and the destination operand (the one overwritten by the result).
  62 <P>
  63 For most instructions, one of the two explicitly specified --
  64 the source or the -- be either in a register or in memory.
  65 The other operand must be in a register or be an immediate source operand.
  66 Thus, the explicit two-operand instructions of the 80386 permit operations
  67 of the following kinds:
  68 <UL>
  69 <LI> Register-to-register
  70 <LI> Register-to-memory
  71 <LI> Memory-to-register
  72 <LI> Immediate-to-register
  73 <LI> Immediate-to-memory
  74 </UL>
  75 <P>
  76 Certain string instructions and stack manipulation instructions, however,
  77 transfer data from memory to memory. Both operands of some string
  78 instructions are in memory and are implicitly specified. Push and pop stack
  79 operations allow transfer between memory operands and the memory-based
  80 stack.
  81
  82 <H2>2.5.1  Immediate Operands</H2>
  83 Certain instructions use data from the instruction itself as one (and
  84 sometimes two) of the operands. Such an operand is called an immediate
  85 operand. The operand may be 32-, 16-, or 8-bits long. For example:
  86 <PRE>
  87 <A HREF="SAL.htm">SHR</A> PATTERN, 2
  88 </PRE>
  89 One byte of the instruction holds the value 2, the number of bits by which
  90 to shift the variable PATTERN.
  91 <PRE>
  92 <A HREF="TEST.htm">TEST</A> PATTERN, 0FFFF00FFH
  93 </PRE>
  94 A doubleword of the instruction holds the mask that is used to test the
  95 variable PATTERN.
  96
  97 <H2>2.5.2  Register Operands</H2>
  98 Operands may be located in one of the 32-bit general registers (EAX, EBX,
  99 ECX, EDX, ESI, EDI, ESP, or EBP), in one of the 16-bit general registers
 100 (AX, BX, CX, DX, SI, DI, SP, or BP), or in one of the 8-bit general
 101 registers (AH, BH, CH, DH, AL, BL, CL,or DL).
 102 <P>
 103 The 80386 has instructions for referencing the segment registers (CS, DS,
 104 ES, SS, FS, GS). These instructions are used by applications programs only
 105 if systems designers have chosen a segmented memory model.
 106 <P>
 107 The 80386 also has instructions for referring to the flag register. The
 108 flags may be stored on the stack and restored from the stack. Certain
 109 instructions change the commonly modified flags directly in the EFLAGS
 110 register. Other flags that are seldom modified can be modified indirectly
 111 via the flags image in the stack.
 112
 113 <H2>2.5.3  Memory Operands</H2>
 114 Data-manipulation instructions that address operands in memory must specify
 115 (either directly or indirectly) the segment that contains the operand and
 116 the offset of the operand within the segment. However, for speed and compact
 117 instruction encoding, segment selectors are stored in the high speed segment
 118 registers. Therefore, data-manipulation instructions need to specify only
 119 the desired segment register and an offset in order to address a memory
 120 operand.
 121 <P>
 122 An 80386 data-manipulation instruction that accesses memory uses one of the
 123 following methods for specifying the offset of a memory operand within its
 124 segment:
 125 <OL>
 126 <LI>Most data-manipulation instructions that access memory contain a byte
 127 that explicitly specifies the addressing method for the operand. A
 128 byte, known as the modR/M byte, follows the opcode and specifies
 129 whether the operand is in a register or in memory. If the operand is
 130 in memory, the address is computed from a segment register and any of
 131 the following values: a base register, an index register, a scaling
 132 factor, a displacement. When an index register is used, the modR/M
 133 byte is also followed by another byte that identifies the index
 134 register and scaling factor. This addressing method is the
 135 most flexible.
 136
 137 <LI>A few data-manipulation instructions implicitly use specialized
 138 addressing methods:
 139 <UL>
 140 <LI> For a few short forms of
 141 <A HREF="MOV.htm">MOV</A> that implicitly use the EAX register,
 142 the offset of the operand is coded as a doubleword in the
 143 instruction. No base register, index register, or scaling factor
 144 are used.
 145 <LI> String operations implicitly address memory via DS:ESI,
 146 (<A HREF="MOVS.htm">MOVS</A>,
 147 <A HREF="CMPS.htm">CMPS</A>,
 148 <A HREF="OUTS.htm">OUTS</A>,
 149 <A HREF="LODS.htm">LODS</A>,
 150 <A HREF="SCAS.htm">SCAS</A>) or via ES:EDI
 151 (<A HREF="MOVS.htm">MOVS</A>,
 152 <A HREF="CMPS.htm">CMPS</A>,
 153 <A HREF="INS.htm">INS</A>,
 154 <A HREF="STOS.htm">STOS</A>).
 155
 156 <LI> Stack operations implicitly address operands via SS:ESP
 157 registers; e.g.,
 158 <A HREF="PUSH.htm">PUSH</A>,
 159 <A HREF="POP.htm">POP</A>,
 160 <A HREF="PUSHA.htm">PUSHA</A>,
 161 <A HREF="PUSHA.htm">PUSHAD</A>,
 162 <A HREF="POPA.htm">POPA</A>,
 163 <A HREF="POPA.htm">POPAD</A>,
 164 <A HREF="PUSHF.htm">PUSHF</A>,
 165 <A HREF="PUSHF.htm">PUSHFD</A>,
 166 <A HREF="POPF.htm">POPF</A>,
 167 <A HREF="POPF.htm">POPFD</A>,
 168 <A HREF="CALL.htm">CALL</A>,
 169 <A HREF="RET.htm">RET</A>,
 170 <A HREF="IRET.htm">IRET</A>,
 171 <A HREF="IRET.htm">IRETD</A>,
 172 exceptions, and interrupts.
 173 </UL>
 174 </OL>
 175
 176 <H3>2.5.3.1  Segment Selection</H3>
 177 Data-manipulation instructions need not explicitly specify which segment
 178 register is used. For all of these instructions, specification of a segment
 179 register is optional. For all memory accesses, if a segment is not
 180 explicitly specified by the instruction, the processor automatically chooses
 181 a segment register according to the rules of Table 2-1. (If systems
 182 designers have chosen a flat model of memory organization, the segment
 183 registers and the rules that the processor uses in choosing them are not
 184 apparent to applications programs.)
 185 <P>
 186 There is a close connection between the kind of memory reference and the
 187 segment in which that operand resides. As a rule, a memory reference implies
 188 the current data segment (i.e., the implicit segment selector is in DS).
 189 However, ESP and EBP are used to access items on the stack; therefore, when
 190 the ESP or EBP register is used as a base register, the current stack
 191 segment is implied (i.e., SS contains the selector).
 192 <P>
 193 Special instruction prefix elements may be used to override the default
 194 segment selection. Segment-override prefixes allow an explicit segment
 195 selection. The 80386 has a segment-override prefix for each of the segment
 196 registers. Only in the following special cases is there an implied segment
 197 selection that a segment prefix cannot override:
 198 <UL>
 199 <LI> The use of ES for destination strings in string instructions.
 200 <LI> The use of SS in stack instructions.
 201 <LI> The use of CS for instruction fetches.
 202 </UL>
 203 <P>
 204 <PRE>
 205 Table 2-1. Default Segment Register Selection Rules
 206
 207 Memory Reference Needed  Segment     Implicit Segment Selection Rule
 208 Register
 209 Used
 210
 211 Instructions             Code (CS)   Automatic with instruction prefetch
 212 Stack                    Stack (SS)  All stack pushes and pops. Any
 213 memory reference that uses ESP or
 214 EBP as a base register.
 215 Local Data               Data (DS)   All data references except when
 216 relative to stack or string
 217 destination.
 218 Destination Strings      Extra (ES)  Destination of string instructions.
 219 </PRE>
 220
 221 <H3>2.5.3.2  Effective-Address Computation</H3>
 222 The modR/M byte provides the most flexible of the addressing methods, and
 223 instructions that require a modR/M byte as the second byte of the
 224 instruction are the most common in the 80386 instruction set. For memory
 225 operands defined by modR/M, the offset within the desired segment is
 226 calculated by taking the sum of up to three components:
 227 <UL>
 228 <LI> A displacement element in the instruction.
 229 <LI> A base register.
 230 <LI> An index register. The index register may be automatically multiplied
 231 by a scaling factor of 2, 4, or 8.
 232 </UL>
 233 <P>
 234 The offset that results from adding these components is called an effective
 235 address. Each of these components of an effective address may have either a
 236 positive or negative value. If the sum of all the components exceeds 2^(32),
 237 the effective address is truncated to 32 bits.
 238 <A HREF="#fig2-10">Figure 2-10</A>
 239   illustrates the
 240 full set of possibilities for modR/M addressing.
 241 <P>
 242 The displacement component, because it is encoded in the instruction, is
 243 useful for fixed aspects of addressing; for example:
 244 <UL>
 245 <LI> Location of simple scalar operands.
 246 <LI> Beginning of a statically allocated array.
 247 <LI> Offset of an item within a record.
 248 </UL>
 249 The base and index components have similar functions. Both utilize the same
 250 set of general registers. Both can be used for aspects of addressing that
 251 are determined dynamically; for example:
 252 <UL>
 253 <LI> Location of procedure parameters and local variables in stack.
 254 <LI> The beginning of one record among several occurrences of the same
 255 record type or in an array of records.
 256 <LI> The beginning of one dimension of multiple dimension array.
 257 <LI> The beginning of a dynamically allocated array.
 258 </UL>
 259 The uses of general registers as base or index components differ in the
 260 following respects:
 261 <UL>
 262 <LI> ESP cannot be used as an index register.
 263 <LI> When ESP or EBP is used as the base register, the default segment is
 264 the one selected by SS. In all other cases the default segment is DS.
 265 </UL>
 266 The scaling factor permits efficient indexing into an array in the common
 267 cases when array elements are 2, 4, or 8 bytes wide. The shifting of the
 268 index register is done by the processor at the time the address is evaluated
 269 with no performance loss. This eliminates the need for a separate shift or
 270 multiply instruction.
 271 <P>
 272 The base, index, and displacement components may be used in any
 273 combination; any of these components may be null. A scale factor can be used
 274 only when an index is also used. Each possible combination is useful for
 275 data structures commonly used by programmers in high-level languages and
 276 assembly languages. Following are possible uses for some of the various
 277 combinations of address components.
 278 <DL>
 279 <DT>
 280 DISPLACEMENT
 281 <DD>
 282 The displacement alone indicates the offset of the operand. This
 283 combination is used to directly address a statically allocated scalar
 284 operand. An 8-bit, 16-bit, or 32-bit displacement can be used.
 285 <DT>
 286 BASE
 287 <DD>
 288 The offset of the operand is specified indirectly in one of the general
 289 registers, as for "based" variables.
 290 <DT>
 291 BASE + DISPLACEMENT
 292 <DD>
 293 A register and a displacement can be used together for two distinct
 294 purposes:
 295 <OL>
 296 <LI>Index into static array when element size is not 2, 4, or 8 bytes.
 297 The displacement component encodes the offset of the beginning of
 298 the array. The register holds the results of a calculation to
 299 determine the offset of a specific element within the array.
 300 <LI>Access item of a record. The displacement component locates an
 301 within record. The base register selects one of several
 302 occurrences of record, thereby providing a compact encoding for
 303 this common function.
 304 </OL>
 305 An important special case of this combination, is to access parameters
 306 in the procedure activation record in the stack.  In this case, EBP is
 307 the best choice for the base register, because when EBP is used as a
 308 base register, the processor automatically uses the stack segment
 309 register (SS) to locate the operand, thereby providing a compact
 310 encoding for this common function.
 311 <DT>
 312 (INDEX * SCALE) + DISPLACEMENT
 313 <DD>
 314 This combination provides efficient indexing into a static array when
 315 the element size is 2, 4, or 8 bytes. The displacement addresses the
 316 beginning of the array, the index register holds the subscript of the
 317 desired array element, and the processor automatically converts the
 318 subscript into an index by applying the scaling factor.
 319 <DT>
 320 BASE + INDEX + DISPLACEMENT
 321 <DD>
 322 Two registers used together support either a two-dimensional array (the
 323 displacement determining the beginning of the array) or one of several
 324 instances of an array of records (the displacement indicating an item
 325 in the record).
 326 <DT>
 327 BASE + (INDEX * SCALE) + DISPLACEMENT
 328 <DD>
 329 This combination provides efficient indexing of a two-dimensional array
 330 when the elements of the array are 2, 4, or 8 bytes wide.
 331 <P>
 332 <A NAME="fig2-10">
 333 <IMG align=center SRC="fig2-10.gif" border=0>
 334 <P>
 335 <HR>
 336 <P>
 337 <B>up:</B> <A HREF="c02.htm">
 338 Chapter 2 -- Basic Programming Model</A><BR>
 339 <B>prev:</B> <A HREF="s02_04.htm">2.4  Instruction Format</A><BR>
 340 <B>next:</B> <A HREF="s02_06.htm">2.6  Interrupts and Exceptions</A>
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