i386/i386.reference/s03_10.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 3.10</TITLE>
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   7 <B>up:</B> <A HREF="c03.htm">
   8 Chapter 3 -- Applications Instruction Set</A><BR>
   9 <B>prev:</B> <A HREF="s03_09.htm">3.9  Coprocessor Interface Instructions</A><BR>
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  11 <P>
  12 <HR>
  13 <P>
  14 <H1>3.10  Segment Register Instructions</H1>
  15 This category actually includes several distinct types of instructions.
  16 These various types are grouped together here because, if systems designers
  17 choose an unsegmented model of memory organization, none of these
  18 instructions is used by applications programmers. The instructions that deal
  19 with segment registers are:
  20 <OL>
  21 <LI> Segment-register transfer instructions.
  22 <UL>
  23 <LI><A HREF="MOV.htm">MOV</A> SegReg, ...
  24 <LI><A HREF="MOV.htm">MOV</A> ..., SegReg
  25 <LI><A HREF="PUSH.htm">PUSH</A> SegReg
  26 <LI><A HREF="POP.htm">POP</A> SegReg
  27 </UL>
  28
  29 <LI> Control transfers to another executable segment.
  30 <UL>
  31 <LI><A HREF="JMP.htm">JMP</A> far direct and indirect
  32 <LI><A HREF="CALL.htm">CALL</A> far
  33 <LI><A HREF="RET.htm">RET</A> far
  34 </UL>
  35
  36 <LI> Data pointer instructions.
  37 <UL>
  38 <LI><A HREF="LGS.htm">LDS</A>
  39 <LI><A HREF="LGS.htm">LES</A>
  40 <LI><A HREF="LGS.htm">LFS</A>
  41 <LI><A HREF="LGS.htm">LGS</A>
  42 <LI><A HREF="LGS.htm">LSS</A>
  43 </UL>
  44 </OL>
  45 Note that the following interrupt-related instructions are different; all
  46 are capable of transferring control to another segment, but the use of
  47 segmentation is not apparent to the applications programmer.
  48 <P>
  49 <UL>
  50 <LI><A HREF="INT.htm">INT n</A>
  51 <LI><A HREF="INT.htm">INTO</A>
  52 <LI><A HREF="BOUND.htm">BOUND</A>
  53 <LI><A HREF="IRET.htm">IRET</A>
  54 </UL>
  55
  56 <H2>3.10.1  Segment-Register Transfer Instructions</H2>
  57 The
  58 <A HREF="MOV.htm">MOV</A>,
  59 <A HREF="POP.htm">POP</A>, and
  60 <A HREF="PUSH.htm">PUSH</A> instructions also serve to load and store segment
  61 registers. These variants operate similarly to their general-register
  62 counterparts except that one operand can be a segment register.
  63 <A HREF="MOV.htm">MOV</A> cannot
  64 move segment register to a segment register. Neither
  65 <A HREF="POP.htm">POP</A> nor
  66 <A HREF="MOV.htm">MOV</A> can place a
  67 value in the code-segment register CS; only the far control-transfer
  68 instructions can change CS.
  69
  70 <H2>3.10.2  Far Control Transfer Instructions</H2>
  71 The far control-transfer instructions transfer control to a location in
  72 another segment by changing the content of the CS register.
  73 <P>
  74 Direct far <A HREF="JMP.htm">JMP</A>. Direct
  75 <A HREF="JMP.htm">JMP</A> instructions that specify a target location
  76 outside the current code segment contain a far pointer. This pointer
  77 consists of a selector for the new code segment and an offset within the new
  78 segment.
  79 <P>
  80 Indirect far <A HREF="JMP.htm">JMP</A>. Indirect
  81 <A HREF="JMP.htm">JMP</A> instructions that specify a target location
  82 outside the current code segment use a 48-bit variable to specify the far
  83 pointer.
  84 <P>
  85 Far <A HREF="CALL.htm">CALL</A>. An intersegment
  86 <A HREF="CALL.htm">CALL</A> places both the value of EIP and CS on the
  87 stack.
  88 <P>
  89 Far <A HREF="RET.htm">RET</A>. An intersegment
  90 <A HREF="RET.htm">RET</A> restores the values of both CS and EIP which
  91 were saved on the stack by the previous intersegment
  92 <A HREF="CALL.htm">CALL</A> instruction.
  93
  94 <H2>3.10.3  Data Pointer Instructions</H2>
  95 The data pointer instructions load a pointer (consisting of a segment
  96 selector and an offset) to a segment register and a general register.
  97 <P>
  98 <A HREF="LGS.htm">LDS</A> (Load Pointer Using DS)
  99 transfers a pointer variable from the source
 100 operand to DS and the destination register. The source operand must be a
 101 memory operand, and the destination operand must be a general register. DS
 102 receives the segment-selector of the pointer. The destination register
 103 receives the offset part of the pointer, which points to a specific location
 104 within the segment.
 105 Example:
 106 <PRE>
 107 <A HREF="LGS.htm">LDS</A> ESI, STRING_X
 108 </PRE>
 109 Loads DS with the selector identifying the segment pointed to by a
 110 STRING_X, and loads the offset of STRING_X into ESI.  Specifying ESI as the
 111 destination operand is a convenient way to prepare for a string operation on
 112 a source string that is not in the current data segment.
 113 <P>
 114 <A HREF="LGS.htm">LES</A> (Load Pointer Using ES)
 115 operates identically to <A HREF="LGS.htm">LDS</A> except that ES
 116 receives the segment selector rather than DS.
 117 Example:
 118 <PRE>
 119 <A HREF="LGS.htm">LES</A> EDI, DESTINATION_X
 120 </PRE>
 121 Loads ES with the selector identifying the segment pointed to by
 122 DESTINATION_X, and loads the offset of DESTINATION_X into EDI. This
 123 instruction provides a convenient way to select a destination for a string
 124 operation if the desired location is not in the current extra segment.
 125 <P>
 126 <A HREF="LGS.htm">LFS</A> (Load Pointer Using FS) operates identically to
 127 <A HREF="LGS.htm">LDS</A> except that FS
 128 receives the segment selector rather than DS.
 129 <P>
 130 <A HREF="LGS.htm">LGS</A> (Load Pointer Using GS) operates identically to
 131 <A HREF="LGS.htm">LDS</A> except that GS
 132 receives the segment selector rather than DS.
 133 <P>
 134 <A HREF="LGS.htm">LSS</A> (Load Pointer Using SS) operates identically to
 135 <A HREF="LGS.htm">LDS</A> except that SS
 136 receives the segment selector rather than DS.  This instruction is
 137 especially important, because it allows the two registers that identify the
 138 stack (SS:ESP) to be changed in one uninterruptible operation.  Unlike the
 139 other instructions which load SS, interrupts are not inhibited at the end
 140 of the
 141 <A HREF="LGS.htm">LSS</A> instruction.  The other instructions (e.g.,
 142 <A HREF="POP.htm">POP</A> SS) inhibit
 143 interrupts to permit the following instruction to load ESP, thereby forming
 144 an indivisible load of SS:ESP.  Since both SS and ESP can be loaded by
 145 <A HREF="LGS.htm">LSS</A>,
 146 there is no need to inhibit interrupts.
 147 <P>
 148 <HR>
 149 <P>
 150 <B>up:</B> <A HREF="c03.htm">
 151 Chapter 3 -- Applications Instruction Set</A><BR>
 152 <B>prev:</B> <A HREF="s03_09.htm">3.9  Coprocessor Interface Instructions</A><BR>
 153 <B>next:</B> <A HREF="s03_11.htm">3.11  Miscellaneous Instructions</A>
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