i386/i386.reference/s04_01.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 4.1</TITLE>
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   8 Chapter 4 -- Systems Architecture</A><BR>
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  11 <P>
  12 <HR>
  13 <P>
  14 <H1>4.1  Systems Registers</H1>
  15 The registers designed for use by systems programmers fall into these
  16 classes:
  17 <UL>
  18 <LI>EFLAGS
  19 <LI>Memory-Management Registers
  20 <LI>Control Registers
  21 <LI>Debug Registers
  22 <LI>Test Registers
  23 </UL>
  24 <H2>4.1.1  Systems Flags</H2>
  25 The systems flags of the EFLAGS register control I/O, maskable interrupts,
  26 debugging, task switching, and enabling of virtual 8086 execution in a
  27 protected, multitasking environment. These flags are highlighted in
  28 <A HREF="#fig4-1">Figure 4-1</A>
  29   .
  30 <DL>
  31 <DT>
  32 IF
  33 (Interrupt-Enable Flag, bit 9)
  34 <DD>
  35 Setting IF allows the CPU to recognize external (maskable) interrupt
  36 requests. Clearing IF disables these interrupts. IF has no effect on
  37 either exceptions or nonmaskable external interrupts . Refer to
  38 <A HREF="c09.htm">Chapter 9</A>
  39    for more details about interrupts .
  40 <DT>
  41 NT
  42 (Nested Task, bit 14)
  43 <DD>
  44 The processor uses the nested task flag to control chaining of
  45 interrupted and called tasks. NT influences the operation of the
  46 <A HREF="IRET.htm">IRET</A>
  47 instruction . Refer to
  48 <A HREF="c07.htm">Chapter 7</A> and
  49 <A HREF="c09.htm">Chapter 9</A>
  50 for more information on
  51 nested tasks.
  52 <DT>
  53 RF
  54 (Resume Flag, bit 16)
  55 <DD>
  56 The RF flag temporarily disables debug exceptions so that an instruction
  57 can be restarted after a debug exception without immediately causing
  58 another debug exception . Refer to
  59 <A HREF="c12.htm">Chapter 12</A>
  60    for details .
  61 <DT>
  62 TF
  63 (Trap Flag, bit 8)
  64 <DD>
  65 Setting TF puts the processor into single-step mode for debugging. In
  66 this mode, the CPU automatically generates an exception after each
  67 instruction, allowing a program to be inspected as it executes each
  68 instruction. Single-stepping is just one of several debugging features of
  69 the 80386 . Refer to
  70 <A HREF="c12.htm">Chapter 12</A>
  71    for additional information .
  72 <DT>
  73 VM
  74 (Virtual 8086 Mode, bit 17)
  75 <DD>
  76 When set, the VM flag indicates that the task is executing an 8086
  77 program . Refer to
  78 <A HREF="c14.htm">Chapter 14</A>
  79    for a detailed discussion of how the 80386
  80 executes 8086 tasks in a protected, multitasking environment.
  81 </DL>
  82
  83 <A NAME="fig4-1">
  84 <IMG align=center SRC="fig4-1.gif" border=0>
  85
  86 <H2>4.1.2  Memory-Management Registers</H2>
  87 Four registers of the 80386 locate the data structures that control
  88 segmented memory management:
  89 <DL>
  90 <DT>
  91 GDTR
  92 Global Descriptor Table Register
  93 <DT>
  94 LDTR
  95 Local Descriptor Table Register
  96 <DD>
  97 These registers point to the segment descriptor tables GDT and LDT.
  98 Refer to
  99 <A HREF="c05.htm">Chapter 5</A>
 100    for an explanation of addressing via descriptor
 101 tables.
 102 <DT>
 103 IDTR
 104 Interrupt Descriptor Table Register
 105 <DD>
 106 This register points to a table of entry points for interrupt handlers
 107 (the IDT ) . Refer to
 108 <A HREF="c09.htm">Chapter 9</A>
 109    for details of the interrupt mechanism .
 110 <DT>
 111 TR
 112 Task Register
 113 <DD>
 114 This register points to the information needed by the processor to define
 115 the current task . Refer to
 116 <A HREF="c07.htm">Chapter 7</A>
 117    for a description of the
 118 multitasking features of the 80386.
 119 </DL>
 120
 121 <H2>4.1.3  Control Registers</H2>
 122
 123 <A HREF="#fig4-2">Figure 4-2</A>
 124   shows the format of the 80386 control registers CR0, CR2, and
 125 CR3. These registers are accessible to systems programmers only via variants
 126 of the <A HREF="MOV.htm">MOV</A> instruction, which allow them to be loaded from or stored in
 127 general registers; for example:
 128 <PRE>
 129 MOV EAX, CR0
 130 MOV CR3, EBX
 131 </PRE>
 132 CR0 contains system control flags, which control or indicate conditions
 133 that apply to the system as a whole, not to an individual task.
 134 <DL>
 135 <DT>
 136 EM
 137 (Emulation, bit 2)
 138 <DD>
 139 EM indicates whether coprocessor functions are to be emulated. Refer to
 140
 141 <A HREF="c11.htm">Chapter 11</A>
 142    for details .
 143 <DT>
 144 ET
 145 (Extension Type, bit 4)
 146 <DD>
 147 ET indicates the type of coprocessor present in the system (80287 or
 148 80387 ) . Refer to
 149 <A HREF="c11.htm">Chapter 11</A> and
 150 <A HREF="c10.htm">Chapter 10</A> for details.
 151 <DT>
 152 MP
 153 (Math Present, bit 1)
 154 <DD>
 155 MP controls the function of the <A HREF="WAIT.htm">WAIT</A> instruction, which is used to
 156 coordinate a coprocessor . Refer to
 157 <A HREF="c11.htm">Chapter 11</A>
 158    for details .
 159 <DT>
 160 PE
 161 (Protection Enable, bit 0)
 162 <DD>
 163 Setting PE causes the processor to begin executing in protected mode.
 164 Resetting PE returns to real-address mode . Refer to
 165 <A HREF="c14.htm">Chapter 14</A>
 166    and
 167
 168 <A HREF="c10.htm">Chapter 10</A>
 169    for more information on changing processor modes .
 170 <DT>
 171 PG
 172 (Paging, bit 31)
 173 <DD>
 174 PG indicates whether the processor uses page tables to translate linear
 175 addresses into physical addresses . Refer to
 176 <A HREF="c05.htm">Chapter 5</A>
 177    for a description
 178 of page translation; refer to
 179 <A HREF="c10.htm">Chapter 10</A>
 180    for a discussion of how to set
 181 PG.
 182 <DT>
 183 TS
 184 (Task Switched, bit 3)
 185 <DD>
 186 The processor sets TS with every task switch and tests TS when
 187 interpreting coprocessor instructions . Refer to
 188 <A HREF="c11.htm">Chapter 11</A>
 189    for details .
 190 </DL>
 191 CR2 is used for handling page faults when PG is set. The processor stores
 192 in CR2 the linear address that triggers the fault . Refer to
 193 <A HREF="c09.htm">Chapter 9</A>
 194    for a
 195 description of page-fault handling.
 196 <P>
 197 CR3 is used when PG is set. CR3 enables the processor to locate the page
 198 table directory for the current task . Refer to
 199 <A HREF="c05.htm">Chapter 5</A>
 200    for a description
 201 of page tables and page translation.
 202 <P>
 203 <A NAME="fig4-2">
 204 <IMG align=center SRC="fig4-2.gif" border=0>
 205 <P>
 206 <H2>4.1.4  Debug Register</H2>
 207 The debug registers bring advanced debugging abilities to the 80386,
 208 including data breakpoints and the ability to set instruction breakpoints
 209 without modifying code segments . Refer to
 210 <A HREF="c12.htm">Chapter 12</A>
 211    for a complete
 212 description of formats and usage.
 213
 214 <H2>4.1.5  Test Registers</H2>
 215 The test registers are not a standard part of the 80386 architecture. They
 216 are provided solely to enable confidence testing of the translation
 217 lookaside buffer (TLB), the cache used for storing information from page
 218 tables .
 219 <A HREF="c12.htm">Chapter 12</A>
 220    explains how to use these registers .
 221 <P>
 222 <HR>
 223 <P>
 224 <B>up:</B> <A HREF="c04.htm">
 225 Chapter 4 -- Systems Architecture</A><BR>
 226 <B>prev:</B> <A HREF="c04.htm">Chapter 4 -- Systems Architecture</A><BR>
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