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15 The 80386 switches execution to another task in any of four cases:
16 <OL>
19 descriptor.
22 <LI> An interrupt or exception vectors to a task gate in the IDT.
23 <LI> The current task executes an
25 </OL>
29 interrupts, and exceptions are all ordinary mechanisms of
30 the 80386 that can be used in circumstances that do not require a task
31 switch. Either the type of descriptor referenced or the NT (nested task) bit
32 in the flag word distinguishes between the standard mechanism and the
33 variant that causes a task switch.
34 <P>
37 descriptor or to a task gate. The effect is the same in either case: the
38 80386 switches to the indicated task.
39 <P>
40 An exception or interrupt causes a task switch when it vectors to a task
41 gate in the IDT. If it vectors to an interrupt or trap gate in the IDT, a
42 task switch does not occur . Refer to
44 for more information on the
45 interrupt mechanism.
46 <P>
47 Whether invoked as a task or as a procedure of the interrupted task, an
48 interrupt handler always returns control to the interrupted procedure in the
49 interrupted task. If the NT flag is set, however, the handler is an
50 interrupt task, and the
52 <P>
53 A task switching operation involves these steps:
54 <OL>
55 <LI> Checking that the current task is allowed to switch to the designated
56 task. Data-access privilege rules apply in the case of
58 instructions. The DPL of the TSS descriptor or task gate must be
59 numerically greater (e.g., lower privilege level)
60 than or equal to the maximum of CPL and the RPL of the gate selector.
61 Exceptions, interrupts, and
63 regardless of the DPL of the target task gate or TSS descriptor.
64 <LI> Checking that the TSS descriptor of the new task is marked present
65 and has a valid limit. Any errors up to this point occur in the
66 context of the outgoing task. Errors are restartable and can be
67 handled in a way that is transparent to applications procedures.
68 <LI> Saving the state of the current task. The processor finds the base
69 address of the current TSS cached in the task register. It copies the
70 registers into the current TSS (EAX, ECX, EDX, EBX, ESP, EBP, ESI,
71 EDI, ES, CS, SS, DS, FS, GS, and the flag register). The EIP field of
72 the TSS points to the instruction after the one that caused the task
73 switch.
74 <LI> Loading the task register with the selector of the incoming task's
75 TSS descriptor, marking the incoming task's TSS descriptor as busy,
76 and setting the TS (task switched) bit of the MSW. The selector is
77 either the operand of a control transfer instruction or is taken from
78 a task gate.
79 <LI> Loading the incoming task's state from its TSS and resuming
80 execution. The registers loaded are the LDT register; the flag
81 register; the general registers EIP, EAX, ECX, EDX, EBX, ESP, EBP,
82 ESI, EDI; the segment registers ES, CS, SS, DS, FS, and GS; and PDBR.
83 Any errors detected in this step occur in the context of the incoming
84 task. To an exception handler, it appears that the first instruction
85 of the new task has not yet executed.
86 </OL>
87 Note that the state of the outgoing task is always saved when a task switch
88 occurs. If execution of that task is resumed, it starts after the
89 instruction that caused the task switch. The registers are restored to the
90 values they held when the task stopped executing.
91 <P>
92 Every task switch sets the TS (task switched) bit in the MSW (machine
93 status word). The TS flag is useful to systems software when a coprocessor
94 (such as a numerics coprocessor) is present. The TS bit signals that the
95 context of the coprocessor may not correspond to the current 80386 task.
98 discusses the TS bit and coprocessors in more detail .
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100 Exception handlers that field task-switch exceptions in the incoming task
102 taking any action that might load the selector that caused the exception.
103 Such an action will probably cause another exception, unless the exception
104 handler first examines the selector and fixes any potential problem.
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106 The privilege level at which execution resumes in the incoming task is
107 neither restricted nor affected by the privilege level at which the outgoing
108 task was executing. Because the tasks are isolated by their separate address
109 spaces and TSSs and because privilege rules can be used to prevent improper
110 access to a TSS, no privilege rules are needed to constrain the relation
111 between the CPLs of the tasks. The new task begins executing at the
112 privilege level indicated by the RPL of the CS selector value that is loaded
113 from the TSS.
114 <PRE>
117 NP = Segment-not-present exception
118 GP = General protection fault
119 TS = Invalid TSS
120 SF = Stack fault
122 Validity tests of a selector check that the selector is in the proper
123 table (e.g., the LDT selector refers to the GDT), lies within the bounds of
124 the table, and refers to the proper type of descriptor (e.g., the LDT
125 selector refers to an LDT descriptor).
127 Test Test Description Exception Error Code Selects
129 1 Incoming TSS descriptor is
130 present NP Incoming TSS
131 2 Incoming TSS descriptor is
132 marked not-busy GP Incoming TSS
133 marked not-busy
134 3 Limit of incoming TSS is
135 greater than or equal to 103 TS Incoming TSS
137 -- All register and selector values are loaded --
139 4 LDT selector of incoming
140 task is valid TS Incoming TSS
141 5 LDT of incoming task is
142 present TS Incoming TSS
143 6 CS selector is valid TS Code segment
144 7 Code segment is present NP Code segment
145 8 Code segment DPL matches
146 CS RPL TS Code segment
147 9 Stack segment is valid GP Stack segment
148 10 Stack segment is present SF Stack segment
149 11 Stack segment DPL = CPL SF Stack segment
150 12 Stack-selector RPL = CPL GP Stack segment
151 13 DS, ES, FS, GS selectors are
152 valid GP Segment
153 14 DS, ES, FS, GS segments
154 are readable GP Segment
155 15 DS, ES, FS, GS segments
156 are present NP Segment
157 16 DS, ES, FS, GS segment DPL
158 >= CPL (unless these are
159 conforming segments) GP Segment
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