* remove "\r" nonsense
[mascara-docs.git] / i386 / i386.reference / s10_01.htm
blob2978e021d29c03c571dc3ee55a2ad4e3491e69ec
1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
2 <HTML>
3 <HEAD>
4 <TITLE>80386 Programmer's Reference Manual -- Section 10.1</TITLE>
5 </HEAD>
6 <BODY>
7 <B>up:</B> <A HREF="c10.htm">
8 Chapter 10 -- Initialization</A><BR>
9 <B>prev:</B> <A HREF="c10.htm">Chapter 10 -- Initialization</A><BR>
10 <B>next:</B> <A HREF="s10_02.htm">10.2 Software Initialization for Real-Address Mode</A>
11 <P>
12 <HR>
13 <P>
14 <H1>10.1 Processor State After Reset</H1>
15 The contents of EAX depend upon the results of the power-up self test. The
16 self-test may be requested externally by assertion of BUSY# at the end of
17 RESET. The EAX register holds zero if the 80386 passed the test. A nonzero
18 value in EAX after self-test indicates that the particular 80386 unit is
19 faulty. If the self-test is not requested, the contents of EAX after RESET
20 is undefined.
21 <P>
22 DX holds a component identifier and revision number after RESET as
23 <A HREF="#fig10-1">Figure 10-1</A>
24 illustrates. DH contains 3, which indicates an 80386 component. DL
25 contains a unique identifier of the revision level.
26 <P>
27 Control register zero (CR0) contains the values shown in
28 <A HREF="#fig10-2">Figure 10-2</A>
29 . The
30 ET bit of CR0 is set if an 80387 is present in the configuration (according
31 to the state of the ERROR# pin after RESET). If ET is reset, the
32 configuration either contains an 80287 or does not contain a coprocessor. A
33 software test is required to distinguish between these latter two
34 possibilities.
35 <P>
36 The remaining registers and flags are set as follows:
37 <PRE>
38 EFLAGS =00000002H
39 IP =0000FFF0H
40 CS selector =000H
41 DS selector =0000H
42 ES selector =0000H
43 SS selector =0000H
44 FS selector =0000H
45 GS selector =0000H
46 IDTR:
47 base =0
48 limit =03FFH
49 </PRE>
50 All registers not mentioned above are undefined.
51 <P>
52 These settings imply that the processor begins in real-address mode with
53 interrupts disabled.
54 <P>
55 <A NAME="fig10-1">
56 <IMG align=center SRC="fig10-1.gif" border=0>
57 <HR>
58 <A NAME="fig10-2">
59 <IMG align=center SRC="fig10-2.gif" border=0>
60 <P>
61 <HR>
62 <P>
63 <B>up:</B> <A HREF="c10.htm">
64 Chapter 10 -- Initialization</A><BR>
65 <B>prev:</B> <A HREF="c10.htm">Chapter 10 -- Initialization</A><BR>
66 <B>next:</B> <A HREF="s10_02.htm">10.2 Software Initialization for Real-Address Mode</A>
67 </BODY>