i386/i386.reference/s14_07.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 14.7</TITLE>
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   7 <B>up:</B> <A HREF="c14.htm">
   8 Chapter 14 -- 80386 Real-Address Mode</A><BR>
   9 <B>prev:</B> <A HREF="s14_06.htm">14.6  Real-Address Mode Exceptions</A><BR>
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  11 <P>
  12 <HR>
  13 <P>
  14 <H1>14.7  Differences From 8086</H1>
  15 In general, the 80386 in real-address mode will correctly execute ROM-based
  16 software designed for the 8086, 8088, 80186, and 80188. Following is a list
  17 of the minor differences between 8086 execution on the 80386 and on an 8086.
  18 <OL>
  19 <LI> Instruction clock counts.
  20 <P>
  21 The 80386 takes fewer clocks for most instructions than the 8086/8088.
  22 The areas most likely to be affected are:
  23 <UL>
  24 <P>
  25 <LI> Delays required by I/O devices between I/O operations.
  26 <P>
  27 <LI> Assumed delays with 8086/8088 operating in parallel with an 8087.
  28 </UL>
  29 <P>
  30 <LI> Divide Exceptions Point to the
  31 <A HREF="DIV.htm">DIV</A> instruction.
  32 <P>
  33 Divide exceptions on the 80386 always leave the saved CS:IP value
  34 pointing to the instruction that failed. On the 8086/8088, the CS:IP
  35 value points to the next instruction.
  36
  37 <P>
  38 <LI> Undefined 8086/8088 opcodes.
  39 <P>
  40 Opcodes that were not defined for the 8086/8088 will cause exception
  41 6 or will execute one of the new instructions defined for the 80386.
  42
  43 <P>
  44 <LI> Value written by
  45 <A HREF="PUSH.htm">PUSH</A> SP.
  46 <P>
  47 The 80386 pushes a different value on the stack for
  48 <A HREF="PUSH.htm">PUSH</A> SP than the
  49 8086/8088. The 80386 pushes the value of SP before SP is incremented
  50 as part of the push operation; the 8086/8088 pushes the value of SP
  51 after it is incremented. If the value pushed is important, replace
  52 <A HREF="PUSH.htm">PUSH</A>
  53 SP instructions with the following three instructions:
  54 <PRE>
  55 PUSH  BP
  56 MOV   BP, SP
  57 XCHG  BP, [BP]
  58 </PRE>
  59 This code functions as the 8086/8088
  60 <A HREF="PUSH.htm">PUSH</A> SP instruction on the 80386.
  61
  62 <P>
  63 <LI> Shift or rotate by more than 31 bits.
  64 <P>
  65 The 80386 masks all shift and rotate counts to the low-order five
  66 bits. This MOD 32 operation limits the count to a maximum of 31 bits,
  67 thereby limiting the time that interrupt response is delayed while
  68 the instruction is executing.
  69
  70 <P>
  71 <LI> Redundant prefixes.
  72 <P>
  73 The 80386 sets a limit of 15 bytes on instruction length. The only
  74 way to violate this limit is by putting redundant prefixes before an
  75 instruction. Exception 13 occurs if the limit on instruction length
  76 is violated. The 8086/8088 has no instruction length limit.
  77
  78 <P>
  79 <LI> Operand crossing offset 0 or 65,535.
  80 <P>
  81 On the 8086, an attempt to access a memory operand that crosses
  82 offset 65,535 (e.g.,
  83 <A HREF="MOV.htm">MOV</A> a word to offset 65,535) or offset 0 (e.g.,
  84 <A HREF="PUSH.htm">PUSH</A>
  85 a word when SP = 1) causes the offset to wrap around modulo
  86 65,536. The 80386 raises an exception in these -- 13 if
  87 the segment is a data segment (i.e., if CS, DS, ES, FS, or GS is being
  88 used to address the segment), exception 12 if the segment is a stack
  89 segment (i.e., if SS is being used).
  90
  91 <P>
  92 <LI> Sequential execution across offset 65,535.
  93 <P>
  94 On the 8086, if sequential execution of instructions proceeds past
  95 offset 65,535, the processor fetches the next instruction byte from
  96 offset 0 of the same segment. On the 80386, the processor raises
  97 exception 13 in such a case.
  98
  99 <P>
 100 <LI> <A HREF="LOCK.htm">LOCK</A> is restricted to certain instructions.
 101 <P>
 102 The <A HREF="LOCK.htm">LOCK</A> prefix and its corresponding output signal should only be
 103 used to prevent other bus masters from interrupting a data movement
 104 operation. The 80386 always asserts the <A HREF="LOCK.htm">LOCK</A> signal during an XCHG
 105 instruction with memory (even if the
 106 <A HREF="LOCK.htm">LOCK</A> prefix is not used).
 107 <A HREF="LOCK.htm">LOCK</A>
 108 may only be used with the following 80386 instructions when they
 109 update memory:
 110 <A HREF="BTS.htm">BTS</A>,
 111 <A HREF="BTR.htm">BTR</A>,
 112 <A HREF="BTC.htm">BTC</A>,
 113 <A HREF="XCHG.htm">XCHG</A>,
 114 <A HREF="ADD.htm">ADD</A>,
 115 <A HREF="ADC.htm">ADC</A>,
 116 <A HREF="SUB.htm">SUB</A>,
 117 <A HREF="SBB.htm">SBB</A>,
 118 <A HREF="INC.htm">INC</A>,
 119 <A HREF="DEC.htm">DEC</A>,
 120 <A HREF="AND.htm">AND</A>,
 121 <A HREF="OR.htm">OR</A>,
 122 <A HREF="XOR.htm">XOR</A>,
 123 <A HREF="NOT.htm">NOT</A>, and
 124 <A HREF="NEG.htm">NEG</A>. An undefined-opcode exception
 125 (interrupt 6) results from using
 126 <A HREF="LOCK.htm">LOCK</A> before any other instruction.
 127
 128 <P>
 129 <LI> Single-stepping external interrupt handlers.
 130 <P>
 131 The priority of the 80386 single-step exception is different from that
 132 of the 8086/8088. The change prevents an external interrupt handler
 133 from being single-stepped if the interrupt occurs while a program is
 134 being single-stepped. The 80386 single-step exception has higher
 135 priority that any external interrupt. The 80386 will still single-step
 136 through an interrupt handler invoked by the
 137 <A HREF="INT.htm">INT</A> instructions or by an
 138 exception.
 139
 140 <P>
 141 <LI> <A HREF="IDIV.htm">IDIV</A> exceptions for quotients of 80H or 8000H.
 142 <P>
 143 The 80386 can generate the largest negative number as a quotient for
 144 the <A HREF="IDIV.htm">IDIV</A> instruction.
 145 The 8086/8088 causes exception zero instead.
 146
 147 <P>
 148 <LI> Flags in stack.
 149 <P>
 150 The setting of the flags stored by
 151 <A HREF="PUSHF.htm">PUSHF</A>, by interrupts, and by
 152 exceptions is different from that stored by the 8086 in bit positions
 153 12 through 15. On the 8086 these bits are stored as ones, but in
 154 80386 real-address mode bit 15 is always zero, and bits 14 through 12
 155 reflect the last value loaded into them.
 156
 157 <P>
 158 <LI> NMI interrupting NMI handlers.
 159 <P>
 160 After an NMI is recognized on the 80386, the NMI interrupt is masked
 161 until an <A HREF="IRET.htm">IRET</A> instruction is executed.
 162
 163 <P>
 164 <LI> Coprocessor errors vector to interrupt 16.
 165 <P>
 166 Any 80386 system with a coprocessor must use interrupt vector 16 for
 167 the coprocessor error exception. If an 8086/8088 system uses another
 168 vector for the 8087 interrupt, both vectors should point to the
 169 coprocessor-error exception handler.
 170
 171 <P>
 172 <LI> Numeric exception handlers should allow prefixes.
 173 <P>
 174 On the 80386, the value of CS:IP saved for coprocessor exceptions
 175 points at any prefixes before an ESC instruction. On 8086/8088
 176 systems, the saved CS:IP points to the ESC instruction.
 177
 178 <P>
 179 <LI> Coprocessor does not use interrupt controller.
 180 <P>
 181 The coprocessor error signal to the 80386 does not pass through an
 182 interrupt controller (an 8087
 183 <A HREF="INT.htm">INT</A> signal does). Some instructions in
 184 a coprocessor error handler may need to be deleted if they deal with
 185 the interrupt controller.
 186
 187 <P>
 188 <LI> Six new interrupt vectors.
 189 <P>
 190 The 80386 adds six exceptions that arise only if the 8086 program has
 191 a hidden bug. It is recommended that exception handlers be added that
 192 treat these exceptions as invalid operations. This additional
 193 software does not significantly affect the existing 8086 software
 194 because the interrupts do not normally occur. These interrupt
 195 identifiers should not already have been used by the 8086 software,
 196 because they are in the range reserved by Intel. Table 14-2 describes
 197 the new 80386 exceptions.
 198
 199 <P>
 200 <LI> One megabyte wraparound.
 201 <P>
 202 The 80386 does not wrap addresses at 1 megabyte in real-address mode.
 203 On members of the 8086 family, it possible to specify addresses
 204 greater than one megabyte.  For example, with a selector value 0FFFFH
 205 and an offset of 0FFFFH, the effective address would be 10FFEFH (1
 206 Mbyte + 65519).  The 8086, which can form adresses only up to 20 bits
 207 long, truncates the high-order bit, thereby "wrapping" this address
 208 to 0FFEFH.  However, the 80386, which can form addresses up to 32
 209 bits long does not truncate such an address.
 210 </OL>
 211 <PRE>
 212 Table 14-1. 80386 Real-Address Mode Exceptions
 213
 214 Description                      Interrupt  Function that Can                   Return Address
 215 Number     Generate the Exception              Points to Faulting
 216 Instruction
 217 Divide error                     0          DIV, IDIV                           YES
 218 Debug exceptions                 1          All
 219 Some debug exceptions point to the faulting instruction, others to the
 220 next instruction. The exception handler can determine which has occurred by
 221 examining DR6.
 222
 223 Breakpoint                       3          INT                                 NO
 224 Overflow                         4          INTO                                NO
 225 Bounds check                     5          BOUND                               YES
 226 Invalid opcode                   6          Any undefined opcode or LOCK        YES
 227 used with wrong instruction
 228 Coprocessor not available        7          ESC or WAIT                         YES
 229 Interrupt table limit too small  8          INT vector is not within IDTR       YES
 230 limit
 231 Reserved                         9-12
 232 Stack fault                      12         Memory operand crosses offset       YES
 233 0 or 0FFFFH
 234 Pseudo-protection exception      13         Memory operand crosses offset       YES
 235 0FFFFH or attempt to execute
 236 past offset 0FFFFH or
 237 instruction longer than 15
 238 bytes
 239 Reserved                         14,15
 240 Coprocessor error                16         ESC or WAIT                         YES
 241 Coprocessor errors are reported on the first ESC or WAIT instruction
 242 after the ESC instruction that caused the error.
 243
 244 Two-byte SW interrupt            0-255      INT n                               NO
 245 </PRE>
 246 <PRE>
 247 Table 14-2. New 80386 Exceptions
 248
 249 Interrupt   Function
 250 Identifier
 251
 252 5       A BOUND instruction was executed with a register value outside
 253 the limit values.
 254
 255 6       An undefined opcode was encountered or LOCK was used improperly
 256 before an instruction to which it does not apply.
 257
 258 7       The EM bit in the MSW is set when an ESC instruction was
 259 encountered. This exception also occurs on a WAIT instruction
 260 if TS is set.
 261
 262 8       An exception or interrupt has vectored to an interrupt table
 263 entry beyond the interrupt table limit in IDTR. This can occur
 264 only if the LIDT instruction has changed the limit from the
 265 default value of 3FFH, which is enough for all 256 interrupt
 266 IDs.
 267
 268 12       Operand crosses extremes of stack segment, e.g., MOV operation
 269 at offset 0FFFFH or push with SP=1 during PUSH, CALL, or INT.
 270
 271 13       Operand crosses extremes of a segment other than a stack
 272 segment; or sequential instruction execution attempts to
 273 proceed beyond offset 0FFFFH; or an instruction is longer than
 274 15 bytes (including prefixes).
 275 </PRE>
 276 <P>
 277 <HR>
 278 <P>
 279 <B>up:</B> <A HREF="c14.htm">
 280 Chapter 14 -- 80386 Real-Address Mode</A><BR>
 281 <B>prev:</B> <A HREF="s14_06.htm">14.6  Real-Address Mode Exceptions</A><BR>
 282 <B>next:</B> <A HREF="s14_08.htm">14.8  Differences From 80286 Real-Address Mode</A>
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