i386/i386.reference/s15_06.htm

   1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
   2 <HTML>
   3 <HEAD>
   4 <TITLE>80386 Programmer's Reference Manual -- Section 15.6</TITLE>
   5 </HEAD>
   6 <BODY>
   7 <B>up:</B> <A HREF="c15.htm">
   8 Chapter 15 -- Virtual 8086 Mode</A><BR>
   9 <B>prev:</B> <A HREF="s15_05.htm">15.5  Virtual I/O</A><BR>
  10 <B>next:</B> <A HREF="s15_07.htm">15.7  Differences From 80286 Real-Address Mode</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>15.6  Differences From 8086</H1>
  15 In general, V86 mode will correctly execute software designed for the 8086,
  16 8088, 80186, and 80188. Following is a list of the minor differences between
  17 8086 execution on the 80386 and on an 8086.
  18 <OL>
  19 <LI> Instruction clock counts.
  20 The 80386 takes fewer clocks for most instructions than the
  21 8086/8088. The areas most likely to be affected are:
  22 <UL>
  23
  24 <LI> Delays required by I/O devices between I/O operations.
  25
  26 <LI> Assumed delays with 8086/8088 operating in parallel with an 8087.
  27 </UL>
  28
  29 <LI> Divide exceptions point to the <A HREF="DIV.htm">DIV</A> instruction.
  30
  31 Divide exceptions on the 80386 always leave the saved CS:IP value
  32 pointing to the instruction that failed. On the 8086/8088, the CS:IP
  33 value points to the next instruction.
  34
  35
  36 <LI> Undefined 8086/8088 opcodes.
  37
  38 Opcodes that were not defined for the 8086/8088 will cause exception
  39 6 or will execute one of the new instructions defined for the 80386.
  40
  41
  42 <LI> Value written by <A HREF="PUSH.htm">PUSH</A> SP.
  43
  44 The 80386 pushes a different value on the stack for
  45 <A HREF="PUSH.htm">PUSH</A> SP than the
  46 8086/8088. The 80386 pushes the value of SP before SP is incremented
  47 as part of the push operation; the 8086/8088 pushes the value of SP
  48 after it is incremented. If the value pushed is important, replace
  49 <A HREF="PUSH.htm">PUSH</A> SP instructions with the following three instructions:
  50 <PRE>
  51 PUSH  BP
  52 MOV   BP, SP
  53 XCHG  BP, [BP]
  54 </PRE>
  55 This code functions as the 8086/8088
  56 <A HREF="PUSH.htm">PUSH</A> SP instruction on the 80386.
  57
  58
  59 <LI> Shift or rotate by more than 31 bits.
  60
  61 The 80386 masks all shift and rotate counts to the low-order five
  62 bits. This MOD 32 operation limits the count to a maximum of 31 bits,
  63 thereby limiting the time that interrupt response is delayed while
  64 the instruction is executing.
  65
  66
  67 <LI> Redundant prefixes.
  68
  69 The 80386 sets a limit of 15 bytes on instruction length. The only
  70 way to violate this limit is by putting redundant prefixes before an
  71 instruction. Exception 13 occurs if the limit on instruction length
  72 is violated. The 8086/8088 has no instruction length limit.
  73
  74
  75 <LI> Operand crossing offset 0 or 65,535.
  76
  77 On the 8086, an attempt to access a memory operand that crosses
  78 offset 65,535 (e.g.,
  79 <A HREF="MOV.htm">MOV</A> a word to offset 65,535) or offset 0 (e.g.,
  80 <A HREF="PUSH.htm">PUSH</A> a word when SP = 1)
  81 causes the offset to wrap around modulo
  82 65,536. The 80386 raises an exception in these -- 13 if
  83 the segment is a data segment (i.e., if CS, DS, ES, FS, or GS is
  84 being used to address the segment), exception 12 if the segment is a
  85 stack segment (i.e., if SS is being used).
  86
  87
  88 <LI> Sequential execution across offset 65,535.
  89
  90 On the 8086, if sequential execution of instructions proceeds past
  91 offset 65,535, the processor fetches the next instruction byte from
  92 offset 0 of the same segment. On the 80386, the processor raises
  93 exception 13 in such a case.
  94
  95
  96 <LI> <A HREF="LOCK.htm">LOCK</A> is restricted to certain instructions.
  97
  98 The <A HREF="LOCK.htm">LOCK</A>
  99 prefix and its corresponding output signal should only be
 100 used to prevent other bus masters from interrupting a data movement
 101 operation. The 80386 always asserts the
 102 <A HREF="LOCK.htm">LOCK</A> signal during an
 103 <A HREF="XCHG.htm">XCHG</A>
 104 instruction with memory (even if the
 105 <A HREF="LOCK.htm">LOCK</A> prefix is not used).
 106 <A HREF="LOCK.htm">LOCK</A>
 107 may only be used with the following 80386 instructions when they
 108 update memory:
 109 <A HREF="BTS.htm">BTS</A>,
 110 <A HREF="BTR.htm">BTR</A>,
 111 <A HREF="BTC.htm">BTC</A>,
 112 <A HREF="XCHG.htm">XCHG</A>,
 113 <A HREF="ADD.htm">ADD</A>,
 114 <A HREF="ADC.htm">ADC</A>,
 115 <A HREF="SUB.htm">SUB</A>,
 116 <A HREF="SBB.htm">SBB</A>,
 117 <A HREF="INC.htm">INC</A>,
 118 <A HREF="DEC.htm">DEC</A>,
 119 <A HREF="AND.htm">AND</A>,
 120 <A HREF="OR.htm">OR</A>,
 121 <A HREF="XOR.htm">XOR</A>,
 122 <A HREF="NOT.htm">NOT</A>, and
 123 <A HREF="NEG.htm">NEG</A>. An undefined-opcode exception (interrupt
 124 6) results from using
 125 <A HREF="LOCK.htm">LOCK</A> before any other instruction.
 126
 127
 128 <LI> Single-stepping external interrupt handlers.
 129
 130 The priority of the 80386 single-step exception is different from
 131 that of the 8086/8088. The change prevents an external interrupt
 132 handler from being single-stepped if the interrupt occurs while a
 133 program is being single-stepped. The 80386 single-step exception has
 134 higher priority that any external interrupt. The 80386 will still
 135 single-step through an interrupt handler invoked by the
 136 <A HREF="INT.htm">INT</A>
 137 instructions or by an exception.
 138
 139
 140 <LI> <A HREF="IDIV.htm">IDIV</A> exceptions for quotients of 80H or 8000H.
 141
 142 The 80386 can generate the largest negative number as a quotient for
 143 the
 144 <A HREF="IDIV.htm">IDIV</A> instruction.
 145 The 8086/8088 causes exception zero instead.
 146
 147
 148 <LI> Flags in stack.
 149
 150 The setting of the flags stored by
 151 <A HREF="PUSHF.htm">PUSHF</A>, by interrupts, and by
 152 exceptions is different from that stored by the 8086 in bit positions
 153 12 through 15. On the 8086 these bits are stored as ones, but in V86
 154 mode bit 15 is always zero, and bits 14 through 12 reflect the last
 155 value loaded into them.
 156
 157
 158 <LI> NMI interrupting NMI handlers.
 159
 160 After an NMI is recognized on the 80386, the NMI interrupt is masked
 161 until an <A HREF="IRET.htm">IRET</A> instruction is executed.
 162
 163
 164 <LI> Coprocessor errors vector to interrupt 16.
 165
 166 Any 80386 system with a coprocessor must use interrupt vector 16 for
 167 the coprocessor error exception. If an 8086/8088 system uses another
 168 vector for the 8087 interrupt, both vectors should point to the
 169 coprocessor-error exception handler.
 170
 171
 172 <LI> Numeric exception handlers should allow prefixes.
 173
 174 On the 80386, the value of CS:IP saved for coprocessor exceptions
 175 points at any prefixes before an ESC instruction. On 8086/8088
 176 systems, the saved CS:IP points to the ESC instruction itself.
 177
 178
 179 <LI> Coprocessor does not use interrupt controller.
 180
 181 The coprocessor error signal to the 80386 does not pass through an
 182 interrupt controller (an 8087
 183 <A HREF="INT.htm">INT</A> signal does). Some instructions in
 184 a coprocessor error handler may need to be deleted if they deal with
 185 the interrupt controller.
 186 </OL>
 187 <P>
 188 <HR>
 189 <P>
 190 <B>up:</B> <A HREF="c15.htm">
 191 Chapter 15 -- Virtual 8086 Mode</A><BR>
 192 <B>prev:</B> <A HREF="s15_05.htm">15.5  Virtual I/O</A><BR>
 193 <B>next:</B> <A HREF="s15_07.htm">15.7  Differences From 80286 Real-Address Mode</A>
 194 </BODY>