amd64/bareMetalOS-0.5.2/pure64.boot0/src/init_cpu.asm

   1 ; =============================================================================
   2 ; Pure64 -- a 64-bit OS loader written in Assembly for x86-64 systems
   3 ; Copyright (C) 2008-2011 Return Infinity -- see LICENSE.TXT
   4 ;
   5 ; INIT CPU
   6 ; =============================================================================
   7
   8
   9 init_cpu:
  10
  11 ; Check for Prefetcher and L2 Cache support
  12         mov r15b, 1                     ; Set MSR support to 1
  13         xor eax, eax
  14         mov al, 1                       ; Access CPUID leaf 1
  15         cpuid
  16         shr rax, 8                      ; Family now in AL (lowest 4 bits)
  17         and al, 0x0F                    ; Clear the high 4 bits
  18         cmp al, 0x0F
  19         jne init_cpu_msrok              ; If Family is not 0xF then jump
  20         mov r15b, 0                     ; If it is 0xF (Older P4/Xeon) then set MSR support to 0
  21 init_cpu_msrok:
  22
  23 ; Disable Cache
  24         mov rax, cr0
  25         btr rax, 29                     ; Clear No Write Thru (Bit 29)
  26         bts rax, 30                     ; Set Cache Disable (Bit 30)
  27         mov cr0, rax
  28
  29 ; Flush Cache
  30         wbinvd
  31
  32 ; Diable Paging Global Extensions
  33         mov rax, cr4
  34         btr rax, 7                      ; Clear Paging Global Extensions (Bit 7)
  35         mov cr4, rax
  36         mov rax, cr3
  37         mov cr3, rax
  38
  39 ; Skip next portion if MSR support doesn't exist
  40 ;       cmp r15b, 0
  41 ;       je init_cpu_skip1
  42
  43 ; Disable Prefetchers (Not supported on P4 or Atom)
  44 ;       mov ecx, 0x000001A0
  45 ;       rdmsr
  46 ;       or eax, 0x00080200              ; Set Hardware Prefetcher Disable (Bit 9) and Adjacent Cache Line Prefetch Disable (Bit 19)
  47 ;       or edx, 0x000000A0              ; Set DCU Prefetcher Disable (Bit 37) and IP Prefetcher Disable (Bit 39)
  48 ;       wrmsr
  49
  50 ; Disable L2 Cache (Not supported on P4 or Atom)
  51 ;       mov ecx, 0x0000011E             ; Control register 3: used to configure the L2 Cache
  52 ;       rdmsr
  53 ;       btr eax, 8                      ; Clear L2 Enabled (Bit 8)
  54 ;       wrmsr
  55
  56 ;init_cpu_skip1:
  57
  58 ; Disable MTRRs and Configure default memory type to UC
  59         mov ecx, 0x000002FF
  60         rdmsr
  61         and eax, 0xFFFFF300             ; Clear MTRR Enable (Bit 11), Fixed Range MTRR Enable (Bit 10), and Default Memory Type (Bits 7:0) to UC (0x00)
  62         wrmsr
  63
  64 ; Setup variable-size address ranges
  65 ; Cache 0-64 MiB as type 6 (WB) cache
  66 ; See example in Intel Volume 3A. Example Base and Mask Calculations
  67 ;       mov ecx, 0x00000200             ; MTRR_Phys_Base_MSR(0)
  68 ;       mov edx, 0x00000000             ; Base is EDX:EAX, 0x0000000000000006
  69 ;       mov eax, 0x00000006             ; Type 6 (write-back cache)
  70 ;       wrmsr
  71 ;       mov ecx, 0x00000201             ; MTRR_Phys_Mask_MSR(0)
  72 ;;      mov edx, 0x00000000             ; Mask is EDX:EAX, 0x0000000001000800 (Because bochs sucks)
  73 ;;      mov eax, 0x01000800             ; Bit 11 set for Valid
  74 ;       mov edx, 0x0000000F             ; Mask is EDX:EAX, 0x0000000F80000800 (2 GiB)
  75 ;       mov eax, 0x80000800             ; Bit 11 set for Valid
  76 ;       wrmsr
  77
  78 ; MTRR notes:
  79 ; Base 0x0000000000000000 = 0 MiB
  80 ; Base 0x0000000080000000 = 2048 MiB, 2048 is 0x800
  81 ; Base 0x0000000100000000 = 4096 MiB, 4096 is 0x1000
  82 ; Mask 0x0000000F80000000 = 2048 MiB, 0xFFFFFFFFF - F80000000 = 7FFFFFFF = 2147483647 (~2 GiB)
  83 ; Mask 0x0000000FC0000000 = 1024 MiB, 0xFFFFFFFFF - FC0000000 = 3FFFFFFF = 1073741823 (~1 GiB)
  84 ; Mask 0x0000000FFC000000 = 64 MiB,   0xFFFFFFFFF - FFC000000 =  3FFFFFF =   67108863 (~64 MiB)
  85
  86 ; Enable MTRRs
  87         mov ecx, 0x000002FF
  88         rdmsr
  89         bts eax, 11                     ; Set MTRR Enable (Bit 11), Only enables Variable Range MTRR's
  90         wrmsr
  91
  92 ; Flush Cache
  93         wbinvd
  94
  95 ; Skip next portion if MSR support doesn't exist
  96 ;       cmp r15b, 0
  97 ;       je init_cpu_skip2
  98
  99 ; Enable L2 Cache (Not supported on P4 or Atom)
 100 ;       mov ecx, 0x0000011E             ; Control register 3: used to configure the L2 Cache
 101 ;       rdmsr
 102 ;       bts eax, 8                      ; Set L2 Enabled (Bit 8)
 103 ;       wrmsr
 104
 105 ; Enable Prefetchers (Not supported on P4 or Atom)
 106 ;       mov ecx, 0x000001A0
 107 ;       rdmsr
 108 ;       and eax, 0xFFF7FDFF             ; Clear Hardware Prefetcher Disable (Bit 9) and Adjacent Cache Line Prefetch Disable (Bit 19)
 109 ;       and edx, 0xFFFFFFAF             ; Clear DCU Prefetcher Disable (Bit 37) and IP Prefetcher Disable (Bit 39)
 110 ;       wrmsr
 111
 112 ;init_cpu_skip2:
 113
 114 ; Enable Cache
 115         mov rax, cr0
 116         btr rax, 29                     ; Clear No Write Thru (Bit 29)
 117         btr rax, 30                     ; Clear CD (Bit 30)
 118         mov cr0, rax
 119
 120 ; Enable Paging Global Extensions
 121         mov rax, cr4
 122         bts rax, 7                      ; Set Paging Global Extensions (Bit 7)
 123         mov cr4, rax
 124
 125 ; Enable Floating Point
 126         mov rax, cr0
 127         bts rax, 1                      ; Set Monitor co-processor (Bit 1)
 128         btr rax, 2                      ; Clear Emulation (Bit 2)
 129         mov cr0, rax
 130
 131 ; Enable SSE
 132         mov rax, cr4
 133         bts rax, 9                      ; Set Operating System Support for FXSAVE and FXSTOR instructions (Bit 9)
 134         bts rax, 10                     ; Set Operating System Support for Unmasked SIMD Floating-Point Exceptions (Bit 10)
 135         mov cr4, rax
 136
 137 ; Enable Math Co-processor
 138         finit
 139
 140 ret
 141
 142
 143 ; =============================================================================
 144 ; EOF