i386/linux/linux-2.3.21/arch/sparc64/kernel/pci_impl.h

   1 /* $Id: pci_impl.h,v 1.3 1999/09/10 10:40:44 davem Exp $
   2  * pci_impl.h: Helper definitions for PCI controller support.
   3  *
   4  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
   5  */
   6
   7 #ifndef PCI_IMPL_H
   8 #define PCI_IMPL_H
   9
  10 #include <linux/types.h>
  11 #include <linux/spinlock.h>
  12 #include <asm/io.h>
  13
  14 extern spinlock_t pci_controller_lock;
  15 extern struct pci_controller_info *pci_controller_root;
  16
  17 extern struct pci_pbm_info *pci_bus2pbm[256];
  18 extern unsigned char pci_highest_busnum;
  19 extern int pci_num_controllers;
  20
  21 /* PCI bus scanning and fixup support. */
  22 extern void pci_fill_in_pbm_cookies(struct pci_bus *pbus,
  23                                     struct pci_pbm_info *pbm,
  24                                     int prom_node);
  25 extern void pci_record_assignments(struct pci_pbm_info *pbm,
  26                                    struct pci_bus *pbus);
  27 extern void pci_assign_unassigned(struct pci_pbm_info *pbm,
  28                                   struct pci_bus *pbus);
  29 extern void pci_fixup_irq(struct pci_pbm_info *pbm,
  30                           struct pci_bus *pbus);
  31
  32 /* Error reporting support. */
  33 extern void pci_scan_for_target_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
  34 extern void pci_scan_for_master_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
  35 extern void pci_scan_for_parity_error(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
  36
  37 /* IOMMU/DVMA initialization. */
  38 #define PCI_DVMA_HASH_NONE      ~0UL
  39 static __inline__ void set_dvma_hash(unsigned long dvma_offset,
  40                                      unsigned long paddr,
  41                                      unsigned long daddr)
  42 {
  43         unsigned long dvma_addr = dvma_offset + daddr;
  44         unsigned long vaddr = (unsigned long)__va(paddr);
  45
  46         pci_dvma_v2p_hash[pci_dvma_ahashfn(paddr)] = dvma_addr - vaddr;
  47         pci_dvma_p2v_hash[pci_dvma_ahashfn(dvma_addr)] = vaddr - dvma_addr;
  48 }
  49
  50 /* Configuration space access. */
  51 extern spinlock_t pci_poke_lock;
  52 extern volatile int pci_poke_in_progress;
  53 extern volatile int pci_poke_faulted;
  54
  55 static __inline__ void pci_config_read8(u8 *addr, u8 *ret)
  56 {
  57         unsigned long flags;
  58         u8 byte;
  59
  60         spin_lock_irqsave(&pci_poke_lock, flags);
  61         pci_poke_in_progress = 1;
  62         pci_poke_faulted = 0;
  63         __asm__ __volatile__("membar #Sync\n\t"
  64                              "lduba [%1] %2, %0\n\t"
  65                              "membar #Sync"
  66                              : "=r" (byte)
  67                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  68                              : "memory");
  69         pci_poke_in_progress = 0;
  70         if (!pci_poke_faulted)
  71                 *ret = byte;
  72         spin_unlock_irqrestore(&pci_poke_lock, flags);
  73 }
  74
  75 static __inline__ void pci_config_read16(u16 *addr, u16 *ret)
  76 {
  77         unsigned long flags;
  78         u16 word;
  79
  80         spin_lock_irqsave(&pci_poke_lock, flags);
  81         pci_poke_in_progress = 1;
  82         pci_poke_faulted = 0;
  83         __asm__ __volatile__("membar #Sync\n\t"
  84                              "lduha [%1] %2, %0\n\t"
  85                              "membar #Sync"
  86                              : "=r" (word)
  87                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  88                              : "memory");
  89         pci_poke_in_progress = 0;
  90         if (!pci_poke_faulted)
  91                 *ret = word;
  92         spin_unlock_irqrestore(&pci_poke_lock, flags);
  93 }
  94
  95 static __inline__ void pci_config_read32(u32 *addr, u32 *ret)
  96 {
  97         unsigned long flags;
  98         u32 dword;
  99
 100         spin_lock_irqsave(&pci_poke_lock, flags);
 101         pci_poke_in_progress = 1;
 102         pci_poke_faulted = 0;
 103         __asm__ __volatile__("membar #Sync\n\t"
 104                              "lduwa [%1] %2, %0\n\t"
 105                              "membar #Sync"
 106                              : "=r" (dword)
 107                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 108                              : "memory");
 109         pci_poke_in_progress = 0;
 110         if (!pci_poke_faulted)
 111                 *ret = dword;
 112         spin_unlock_irqrestore(&pci_poke_lock, flags);
 113 }
 114
 115 static __inline__ void pci_config_write8(u8 *addr, u8 val)
 116 {
 117         unsigned long flags;
 118
 119         spin_lock_irqsave(&pci_poke_lock, flags);
 120         pci_poke_in_progress = 1;
 121         pci_poke_faulted = 0;
 122         __asm__ __volatile__("membar #Sync\n\t"
 123                              "stba %0, [%1] %2\n\t"
 124                              "membar #Sync"
 125                              : /* no outputs */
 126                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 127                              : "memory");
 128         pci_poke_in_progress = 0;
 129         spin_unlock_irqrestore(&pci_poke_lock, flags);
 130 }
 131
 132 static __inline__ void pci_config_write16(u16 *addr, u16 val)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&pci_poke_lock, flags);
 137         pci_poke_in_progress = 1;
 138         pci_poke_faulted = 0;
 139         __asm__ __volatile__("membar #Sync\n\t"
 140                              "stha %0, [%1] %2\n\t"
 141                              "membar #Sync"
 142                              : /* no outputs */
 143                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 144                              : "memory");
 145         pci_poke_in_progress = 0;
 146         spin_unlock_irqrestore(&pci_poke_lock, flags);
 147 }
 148
 149 static __inline__ void pci_config_write32(u32 *addr, u32 val)
 150 {
 151         unsigned long flags;
 152
 153         spin_lock_irqsave(&pci_poke_lock, flags);
 154         pci_poke_in_progress = 1;
 155         pci_poke_faulted = 0;
 156         __asm__ __volatile__("membar #Sync\n\t"
 157                              "stwa %0, [%1] %2\n\t"
 158                              "membar #Sync"
 159                              : /* no outputs */
 160                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 161                              : "memory");
 162         pci_poke_in_progress = 0;
 163         spin_unlock_irqrestore(&pci_poke_lock, flags);
 164 }
 165
 166 #endif /* !(PCI_IMPL_H) */