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* add p cc
[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / isdn / avmb1 / b1lli.c
blob4d9fd647cdb601e08fecd8de6bf514c947f2c68b
1 /*
2 * $Id: b1lli.c,v 1.10 1999/04/15 19:49:31 calle Exp $
3 *
4 * ISDN lowlevel-module for AVM B1-card.
5 *
6 * (c) Copyright 1997 by Carsten Paeth (calle@calle.in-berlin.de)
7 *
8 * $Log: b1lli.c,v $
9 * Revision 1.10 1999/04/15 19:49:31 calle
10 * fix fuer die B1-PCI. Jetzt geht z.B. auch IRQ 17 ...
11 *
12 * Revision 1.9 1999/01/05 18:33:23 he
13 * merged remaining 2.2pre{1,2} changes (jiffies and Config)
14 *
15 * Revision 1.8 1998/10/25 14:39:00 fritz
16 * Backported from MIPS (Cobalt).
17 *
18 * Revision 1.7 1998/03/29 16:06:00 calle
19 * changes from 2.0 tree merged.
20 *
21 * Revision 1.1.2.10 1998/03/20 20:34:41 calle
22 * port valid check now only for T1, because of the PCI and PCMCIA cards.
23 *
24 * Revision 1.1.2.9 1998/03/20 14:38:20 calle
25 * capidrv: prepared state machines for suspend/resume/hold
26 * capidrv: fix bug in state machine if B1/T1 is out of nccis
27 * b1capi: changed some errno returns.
28 * b1capi: detect if you try to add same T1 to different io address.
29 * b1capi: change number of nccis depending on number of channels.
30 * b1lli: cosmetics
31 *
32 * Revision 1.1.2.8 1998/03/18 17:43:29 calle
33 * T1 with fastlink, bugfix for multicontroller support in capidrv.c
34 *
35 * Revision 1.1.2.7 1998/03/04 17:33:50 calle
36 * Changes for T1.
37 *
38 * Revision 1.1.2.6 1998/02/27 15:40:44 calle
39 * T1 running with slow link. bugfix in capi_release.
40 *
41 * Revision 1.1.2.5 1998/02/13 16:28:28 calle
42 * first step for T1
43 *
44 * Revision 1.6 1998/02/13 07:09:11 calle
45 * change for 2.1.86 (removing FREE_READ/FREE_WRITE from [dev]_kfree_skb()
46 *
47 * Revision 1.5 1998/01/31 11:14:41 calle
48 * merged changes to 2.0 tree, prepare 2.1.82 to work.
49 *
50 * Revision 1.4 1997/12/10 20:00:48 calle
51 * get changes from 2.0 version
52 *
53 * Revision 1.1.2.2 1997/11/26 10:46:55 calle
54 * prepared for M1 (Mobile) and T1 (PMX) cards.
55 * prepared to set configuration after load to support other D-channel
56 * protocols, point-to-point and leased lines.
57 *
58 * Revision 1.3 1997/10/01 09:21:13 fritz
59 * Removed old compatibility stuff for 2.0.X kernels.
60 * From now on, this code is for 2.1.X ONLY!
61 * Old stuff is still in the separate branch.
62 *
63 * Revision 1.2 1997/07/13 12:22:42 calle
64 * bug fix for more than one controller in connect_req.
65 * debugoutput now with contrnr.
66 *
67 *
68 * Revision 1.1 1997/03/04 21:50:28 calle
69 * Frirst version in isdn4linux
70 *
71 * Revision 2.2 1997/02/12 09:31:39 calle
72 * new version
73 *
74 * Revision 1.1 1997/01/31 10:32:20 calle
75 * Initial revision
76 *
77 *
78 */
79 /* #define FASTLINK_DEBUG */
80
81 #include <linux/kernel.h>
82 #include <linux/skbuff.h>
83 #include <linux/delay.h>
84 #include <linux/mm.h>
85 #include <asm/segment.h>
86 #include <asm/io.h>
87 #include <linux/capi.h>
88 #include <linux/b1lli.h>
89
90 #include "compat.h"
91 #include "capicmd.h"
92 #include "capiutil.h"
93
94 extern int showcapimsgs;
95
96 /*
97 * LLI Messages to the ISDN-ControllerISDN Controller
98 */
99
100 #define SEND_POLL 0x72 /*
101 * after load <- RECEIVE_POLL
102 */
103 #define SEND_INIT 0x11 /*
104 * first message <- RECEIVE_INIT
105 * int32 NumApplications int32
106 * NumNCCIs int32 BoardNumber
107 */
108 #define SEND_REGISTER 0x12 /*
109 * register an application int32
110 * ApplIDId int32 NumMessages
111 * int32 NumB3Connections int32
112 * NumB3Blocks int32 B3Size
113 *
114 * AnzB3Connection != 0 &&
115 * AnzB3Blocks >= 1 && B3Size >= 1
116 */
117 #define SEND_RELEASE 0x14 /*
118 * deregister an application int32
119 * ApplID
120 */
121 #define SEND_MESSAGE 0x15 /*
122 * send capi-message int32 length
123 * capi-data ...
124 */
125 #define SEND_DATA_B3_REQ 0x13 /*
126 * send capi-data-message int32
127 * MsgLength capi-data ... int32
128 * B3Length data ....
129 */
130
131 #define SEND_CONFIG 0x21 /*
132 */
133
134 #define SEND_POLLACK 0x73 /* T1 Watchdog */
135
136 /*
137 * LLI Messages from the ISDN-ControllerISDN Controller
138 */
139
140 #define RECEIVE_POLL 0x32 /*
141 * <- after SEND_POLL
142 */
143 #define RECEIVE_INIT 0x27 /*
144 * <- after SEND_INIT int32 length
145 * byte total length b1struct board
146 * driver revision b1struct card
147 * type b1struct reserved b1struct
148 * serial number b1struct driver
149 * capability b1struct d-channel
150 * protocol b1struct CAPI-2.0
151 * profile b1struct capi version
152 */
153 #define RECEIVE_MESSAGE 0x21 /*
154 * <- after SEND_MESSAGE int32
155 * AppllID int32 Length capi-data
156 * ....
157 */
158 #define RECEIVE_DATA_B3_IND 0x22 /*
159 * received data int32 AppllID
160 * int32 Length capi-data ...
161 * int32 B3Length data ...
162 */
163 #define RECEIVE_START 0x23 /*
164 * Handshake
165 */
166 #define RECEIVE_STOP 0x24 /*
167 * Handshake
168 */
169 #define RECEIVE_NEW_NCCI 0x25 /*
170 * int32 AppllID int32 NCCI int32
171 * WindowSize
172 */
173 #define RECEIVE_FREE_NCCI 0x26 /*
174 * int32 AppllID int32 NCCI
175 */
176 #define RECEIVE_RELEASE 0x26 /*
177 * int32 AppllID int32 0xffffffff
178 */
179 #define RECEIVE_TASK_READY 0x31 /*
180 * int32 tasknr
181 * int32 Length Taskname ...
182 */
183
184 #define WRITE_REGISTER 0x00
185 #define READ_REGISTER 0x01
186
187 /*
188 * port offsets
189 */
190
191 #define B1_READ 0x00
192 #define B1_WRITE 0x01
193 #define B1_INSTAT 0x02
194 #define B1_OUTSTAT 0x03
195 #define B1_RESET 0x10
196 #define B1_ANALYSE 0x04
197
198 /* Hema card T1 */
199
200 #define T1_FASTLINK 0x00
201 #define T1_SLOWLINK 0x08
202
203 #define T1_READ B1_READ
204 #define T1_WRITE B1_WRITE
205 #define T1_INSTAT B1_INSTAT
206 #define T1_OUTSTAT B1_OUTSTAT
207 #define T1_IRQENABLE 0x05
208 #define T1_FIFOSTAT 0x06
209 #define T1_RESETLINK 0x10
210 #define T1_ANALYSE 0x11
211 #define T1_IRQMASTER 0x12
212 #define T1_IDENT 0x17
213 #define T1_RESETBOARD 0x1f
214
215 #define T1F_IREADY 0x01
216 #define T1F_IHALF 0x02
217 #define T1F_IFULL 0x04
218 #define T1F_IEMPTY 0x08
219 #define T1F_IFLAGS 0xF0
220
221 #define T1F_OREADY 0x10
222 #define T1F_OHALF 0x20
223 #define T1F_OEMPTY 0x40
224 #define T1F_OFULL 0x80
225 #define T1F_OFLAGS 0xF0
226
227 /* there are HEMA cards with 1k and 4k FIFO out */
228 #define FIFO_OUTBSIZE 256
229 #define FIFO_INPBSIZE 512
230
231 #define HEMA_VERSION_ID 0
232 #define HEMA_PAL_ID 0
233
234 #define B1_STAT0(cardtype) ((cardtype) == AVM_CARDTYPE_M1 ? 0x81200000l : 0x80A00000l)
235 #define B1_STAT1(cardtype) (0x80E00000l)
236
237
238 static inline unsigned char b1outp(unsigned int base,
239 unsigned short offset,
240 unsigned char value)
241 {
242 outb(value, base + offset);
243 return inb(base + B1_ANALYSE);
244 }
245
246 static inline void t1outp(unsigned int base,
247 unsigned short offset,
248 unsigned char value)
249 {
250 outb(value, base + offset);
251 }
252
253 static inline unsigned char t1inp(unsigned int base,
254 unsigned short offset)
255 {
256 return inb(base + offset);
257 }
258
259 static inline int B1_isfastlink(unsigned int base)
260 {
261 return (inb(base + T1_IDENT) & ~0x82) == 1;
262 }
263 static inline unsigned char B1_fifostatus(unsigned int base)
264 {
265 return inb(base + T1_FIFOSTAT);
266 }
267
268 static inline int B1_rx_full(unsigned int base)
269 {
270 return inb(base + B1_INSTAT) & 0x1;
271 }
272
273 static inline unsigned char B1_get_byte(unsigned int base)
274 {
275 unsigned long i = jiffies + 1 * HZ; /* maximum wait time 1 sec */
276 while (!B1_rx_full(base) && time_before(jiffies, i));
277 if (B1_rx_full(base))
278 return inb(base + B1_READ);
279 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base);
280 return 0;
281 }
282
283 static inline unsigned int B1_get_word(unsigned int base)
284 {
285 unsigned int val = 0;
286 val |= B1_get_byte(base);
287 val |= (B1_get_byte(base) << 8);
288 val |= (B1_get_byte(base) << 16);
289 val |= (B1_get_byte(base) << 24);
290 return val;
291 }
292
293 static inline int B1_tx_empty(unsigned int base)
294 {
295 return inb(base + B1_OUTSTAT) & 0x1;
296 }
297
298 static inline void B1_put_byte(unsigned int base, unsigned char val)
299 {
300 while (!B1_tx_empty(base));
301 b1outp(base, B1_WRITE, val);
302 }
303
304 static inline void B1_put_word(unsigned int base, unsigned int val)
305 {
306 B1_put_byte(base, val & 0xff);
307 B1_put_byte(base, (val >> 8) & 0xff);
308 B1_put_byte(base, (val >> 16) & 0xff);
309 B1_put_byte(base, (val >> 24) & 0xff);
310 }
311
312 static inline unsigned int B1_get_slice(unsigned int base,
313 unsigned char *dp)
314 {
315 unsigned int len, i;
316 #ifdef FASTLINK_DEBUG
317 unsigned wcnt = 0, bcnt = 0;
318 #endif
319
320 len = i = B1_get_word(base);
321 if (B1_isfastlink(base)) {
322 int status;
323 while (i > 0) {
324 status = B1_fifostatus(base) & (T1F_IREADY|T1F_IHALF);
325 if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
326
327 switch (status) {
328 case T1F_IREADY|T1F_IHALF|T1F_IFULL:
329 insb(base+B1_READ, dp, FIFO_INPBSIZE);
330 dp += FIFO_INPBSIZE;
331 i -= FIFO_INPBSIZE;
332 #ifdef FASTLINK_DEBUG
333 wcnt += FIFO_INPBSIZE;
334 #endif
335 break;
336 case T1F_IREADY|T1F_IHALF:
337 insb(base+B1_READ,dp, i);
338 #ifdef FASTLINK_DEBUG
339 wcnt += i;
340 #endif
341 dp += i;
342 i = 0;
343 if (i == 0)
344 break;
345 /* fall through */
346 default:
347 *dp++ = B1_get_byte(base);
348 i--;
349 #ifdef FASTLINK_DEBUG
350 bcnt++;
351 #endif
352 break;
353 }
354 }
355 #ifdef FASTLINK_DEBUG
356 if (wcnt)
357 printk(KERN_DEBUG "b1lli(0x%x): get_slice l=%d w=%d b=%d\n",
358 base, len, wcnt, bcnt);
359 #endif
360 } else {
361 while (i-- > 0)
362 *dp++ = B1_get_byte(base);
363 }
364 return len;
365 }
366
367 static inline void B1_put_slice(unsigned int base,
368 unsigned char *dp, unsigned int len)
369 {
370 unsigned i = len;
371 B1_put_word(base, i);
372 if (B1_isfastlink(base)) {
373 int status;
374 while (i > 0) {
375 status = B1_fifostatus(base) & (T1F_OREADY|T1F_OHALF);
376 if (i >= FIFO_OUTBSIZE) status |= T1F_OEMPTY;
377 switch (status) {
378 case T1F_OREADY|T1F_OHALF|T1F_OEMPTY:
379 outsb(base+B1_WRITE, dp, FIFO_OUTBSIZE);
380 dp += FIFO_OUTBSIZE;
381 i -= FIFO_OUTBSIZE;
382 break;
383 case T1F_OREADY|T1F_OHALF:
384 outsb(base+B1_WRITE, dp, i);
385 dp += i;
386 i = 0;
387 break;
388 default:
389 B1_put_byte(base, *dp++);
390 i--;
391 break;
392 }
393 }
394 } else {
395 while (i-- > 0)
396 B1_put_byte(base, *dp++);
397 }
398 }
399
400 static void b1_wr_reg(unsigned int base,
401 unsigned int reg,
402 unsigned int value)
403 {
404 B1_put_byte(base, WRITE_REGISTER);
405 B1_put_word(base, reg);
406 B1_put_word(base, value);
407 }
408
409 static inline unsigned int b1_rd_reg(unsigned int base,
410 unsigned int reg)
411 {
412 B1_put_byte(base, READ_REGISTER);
413 B1_put_word(base, reg);
414 return B1_get_word(base);
415
416 }
417
418 static inline void b1_set_test_bit(unsigned int base,
419 int cardtype,
420 int onoff)
421 {
422 b1_wr_reg(base, B1_STAT0(cardtype), onoff ? 0x21 : 0x20);
423 }
424
425 static inline int b1_get_test_bit(unsigned int base,
426 int cardtype)
427 {
428 return (b1_rd_reg(base, B1_STAT0(cardtype)) & 0x01) != 0;
429 }
430
431 static int irq_table[16] =
432 {0,
433 0,
434 0,
435 192, /* irq 3 */
436 32, /* irq 4 */
437 160, /* irq 5 */
438 96, /* irq 6 */
439 224, /* irq 7 */
440 0,
441 64, /* irq 9 */
442 80, /* irq 10 */
443 208, /* irq 11 */
444 48, /* irq 12 */
445 0,
446 0,
447 112, /* irq 15 */
448 };
449
450 static int hema_irq_table[16] =
451 {0,
452 0,
453 0,
454 0x80, /* irq 3 */
455 0,
456 0x90, /* irq 5 */
457 0,
458 0xA0, /* irq 7 */
459 0,
460 0xB0, /* irq 9 */
461 0xC0, /* irq 10 */
462 0xD0, /* irq 11 */
463 0xE0, /* irq 12 */
464 0,
465 0,
466 0xF0, /* irq 15 */
467 };
468
469
470 int B1_valid_irq(unsigned irq, int cardtype)
471 {
472 switch (cardtype) {
473 default:
474 case AVM_CARDTYPE_M1:
475 case AVM_CARDTYPE_M2:
476 case AVM_CARDTYPE_B1:
477 return irq_table[irq & 0xf] != 0;
478 case AVM_CARDTYPE_T1:
479 return hema_irq_table[irq & 0xf] != 0;
480 case AVM_CARDTYPE_B1PCI:
481 return 1;
482 }
483 }
484
485 int B1_valid_port(unsigned port, int cardtype)
486 {
487 switch (cardtype) {
488 default:
489 case AVM_CARDTYPE_M1:
490 case AVM_CARDTYPE_M2:
491 case AVM_CARDTYPE_B1:
492 #if 0 /* problem with PCMCIA and PCI cards */
493 switch (port) {
494 case 0x150:
495 case 0x250:
496 case 0x300:
497 case 0x340:
498 return 1;
499 }
500 return 0;
501 #else
502 return 1;
503 #endif
504 case AVM_CARDTYPE_B1PCI:
505 return 1;
506 case AVM_CARDTYPE_T1:
507 return ((port & 0x7) == 0) && ((port & 0x30) != 0x30);
508 }
509 }
510
511 void B1_setinterrupt(unsigned int base,
512 unsigned irq, int cardtype)
513 {
514 switch (cardtype) {
515 case AVM_CARDTYPE_T1:
516 t1outp(base, B1_INSTAT, 0x00);
517 t1outp(base, B1_INSTAT, 0x02);
518 t1outp(base, T1_IRQMASTER, 0x08);
519 break;
520 default:
521 case AVM_CARDTYPE_M1:
522 case AVM_CARDTYPE_M2:
523 case AVM_CARDTYPE_B1:
524 b1outp(base, B1_INSTAT, 0x00);
525 b1outp(base, B1_RESET, irq_table[irq]);
526 b1outp(base, B1_INSTAT, 0x02);
527 break;
528 case AVM_CARDTYPE_B1PCI:
529 b1outp(base, B1_INSTAT, 0x00);
530 b1outp(base, B1_RESET, 0xf0);
531 b1outp(base, B1_INSTAT, 0x02);
532 break;
533 }
534 }
535
536 unsigned char B1_disable_irq(unsigned int base)
537 {
538 return b1outp(base, B1_INSTAT, 0x00);
539 }
540
541 void T1_disable_irq(unsigned int base)
542 {
543 t1outp(base, T1_IRQMASTER, 0x00);
544 }
545
546 void B1_reset(unsigned int base)
547 {
548 b1outp(base, B1_RESET, 0);
549 udelay(55 * 2 * 1000); /* 2 TIC's */
550
551 b1outp(base, B1_RESET, 1);
552 udelay(55 * 2 * 1000); /* 2 TIC's */
553
554 b1outp(base, B1_RESET, 0);
555 udelay(55 * 2 * 1000); /* 2 TIC's */
556 }
557
558 void T1_reset(unsigned int base)
559 {
560 /* reset T1 Controller */
561 B1_reset(base);
562 /* disable irq on HEMA */
563 t1outp(base, B1_INSTAT, 0x00);
564 t1outp(base, B1_OUTSTAT, 0x00);
565 t1outp(base, T1_IRQMASTER, 0x00);
566 /* reset HEMA board configuration */
567 t1outp(base, T1_RESETBOARD, 0xf);
568 }
569
570 int B1_detect(unsigned int base, int cardtype)
571 {
572 int onoff, i;
573
574 if (cardtype == AVM_CARDTYPE_T1)
575 return 0;
576
577 /*
578 * Statusregister 0000 00xx
579 */
580 if ((inb(base + B1_INSTAT) & 0xfc)
581 || (inb(base + B1_OUTSTAT) & 0xfc))
582 return 1;
583 /*
584 * Statusregister 0000 001x
585 */
586 b1outp(base, B1_INSTAT, 0x2); /* enable irq */
587 /* b1outp(base, B1_OUTSTAT, 0x2); */
588 if ((inb(base + B1_INSTAT) & 0xfe) != 0x2
589 /* || (inb(base + B1_OUTSTAT) & 0xfe) != 0x2 */)
590 return 2;
591 /*
592 * Statusregister 0000 000x
593 */
594 b1outp(base, B1_INSTAT, 0x0); /* disable irq */
595 b1outp(base, B1_OUTSTAT, 0x0);
596 if ((inb(base + B1_INSTAT) & 0xfe)
597 || (inb(base + B1_OUTSTAT) & 0xfe))
598 return 3;
599
600 for (onoff = !0, i= 0; i < 10 ; i++) {
601 b1_set_test_bit(base, cardtype, onoff);
602 if (b1_get_test_bit(base, cardtype) != onoff)
603 return 4;
604 onoff = !onoff;
605 }
606
607 if (cardtype == AVM_CARDTYPE_M1)
608 return 0;
609
610 if ((b1_rd_reg(base, B1_STAT1(cardtype)) & 0x0f) != 0x01)
611 return 5;
612
613 return 0;
614 }
615
616 int T1_detectandinit(unsigned int base, unsigned irq, int cardnr)
617 {
618 unsigned char cregs[8];
619 unsigned char reverse_cardnr;
620 unsigned long flags;
621 unsigned char dummy;
622 int i;
623
624 reverse_cardnr = ((cardnr & 0x01) << 3) | ((cardnr & 0x02) << 1)
625 | ((cardnr & 0x04) >> 1) | ((cardnr & 0x08) >> 3);
626 cregs[0] = (HEMA_VERSION_ID << 4) | (reverse_cardnr & 0xf);
627 cregs[1] = 0x00; /* fast & slow link connected to CON1 */
628 cregs[2] = 0x05; /* fast link 20MBit, slow link 20 MBit */
629 cregs[3] = 0;
630 cregs[4] = 0x11; /* zero wait state */
631 cregs[5] = hema_irq_table[irq & 0xf];
632 cregs[6] = 0;
633 cregs[7] = 0;
634
635 save_flags(flags);
636 cli();
637 /* board reset */
638 t1outp(base, T1_RESETBOARD, 0xf);
639 udelay(100 * 1000);
640 dummy = t1inp(base, T1_FASTLINK+T1_OUTSTAT); /* first read */
641
642 /* write config */
643 dummy = (base >> 4) & 0xff;
644 for (i=1;i<=0xf;i++) t1outp(base, i, dummy);
645 t1outp(base, HEMA_PAL_ID & 0xf, dummy);
646 t1outp(base, HEMA_PAL_ID >> 4, cregs[0]);
647 for(i=1;i<7;i++) t1outp(base, 0, cregs[i]);
648 t1outp(base, ((base >> 4)) & 0x3, cregs[7]);
649 restore_flags(flags);
650
651 udelay(100 * 1000);
652 t1outp(base, T1_FASTLINK+T1_RESETLINK, 0);
653 t1outp(base, T1_SLOWLINK+T1_RESETLINK, 0);
654 udelay(10 * 1000);
655 t1outp(base, T1_FASTLINK+T1_RESETLINK, 1);
656 t1outp(base, T1_SLOWLINK+T1_RESETLINK, 1);
657 udelay(100 * 1000);
658 t1outp(base, T1_FASTLINK+T1_RESETLINK, 0);
659 t1outp(base, T1_SLOWLINK+T1_RESETLINK, 0);
660 udelay(10 * 1000);
661 t1outp(base, T1_FASTLINK+T1_ANALYSE, 0);
662 udelay(5 * 1000);
663 t1outp(base, T1_SLOWLINK+T1_ANALYSE, 0);
664
665 if (t1inp(base, T1_FASTLINK+T1_OUTSTAT) != 0x1) /* tx empty */
666 return 1;
667 if (t1inp(base, T1_FASTLINK+T1_INSTAT) != 0x0) /* rx empty */
668 return 2;
669 if (t1inp(base, T1_FASTLINK+T1_IRQENABLE) != 0x0)
670 return 3;
671 if ((t1inp(base, T1_FASTLINK+T1_FIFOSTAT) & 0xf0) != 0x70)
672 return 4;
673 if ((t1inp(base, T1_FASTLINK+T1_IRQMASTER) & 0x0e) != 0)
674 return 5;
675 if ((t1inp(base, T1_FASTLINK+T1_IDENT) & 0x7d) != 1)
676 return 6;
677 if (t1inp(base, T1_SLOWLINK+T1_OUTSTAT) != 0x1) /* tx empty */
678 return 7;
679 if ((t1inp(base, T1_SLOWLINK+T1_IRQMASTER) & 0x0e) != 0)
680 return 8;
681 if ((t1inp(base, T1_SLOWLINK+T1_IDENT) & 0x7d) != 0)
682 return 9;
683 return 0;
684 }
685
686 extern int loaddebug;
687
688 int B1_load_t4file(unsigned int base, avmb1_t4file * t4file)
689 {
690 /*
691 * Data is in user space !!!
692 */
693 unsigned char buf[256];
694 unsigned char *dp;
695 int i, left, retval;
696
697
698 dp = t4file->data;
699 left = t4file->len;
700 while (left > sizeof(buf)) {
701 retval = copy_from_user(buf, dp, sizeof(buf));
702 if (retval)
703 return -EFAULT;
704 if (loaddebug)
705 printk(KERN_DEBUG "b1capi: loading: %d bytes ..", sizeof(buf));
706 for (i = 0; i < sizeof(buf); i++)
707 B1_put_byte(base, buf[i]);
708 if (loaddebug)
709 printk("ok\n");
710 left -= sizeof(buf);
711 dp += sizeof(buf);
712 }
713 if (left) {
714 retval = copy_from_user(buf, dp, left);
715 if (retval)
716 return -EFAULT;
717 if (loaddebug)
718 printk(KERN_DEBUG "b1capi: loading: %d bytes ..", left);
719 for (i = 0; i < left; i++)
720 B1_put_byte(base, buf[i]);
721 if (loaddebug)
722 printk("ok\n");
723 }
724 return 0;
725 }
726
727 int B1_load_config(unsigned int base, avmb1_t4file * config)
728 {
729 /*
730 * Data is in user space !!!
731 */
732 unsigned char buf[256];
733 unsigned char *dp;
734 int i, j, left, retval;
735
736
737 dp = config->data;
738 left = config->len;
739 if (left) {
740 B1_put_byte(base, SEND_CONFIG);
741 B1_put_word(base, 1);
742 B1_put_byte(base, SEND_CONFIG);
743 B1_put_word(base, left);
744 }
745 while (left > sizeof(buf)) {
746 retval = copy_from_user(buf, dp, sizeof(buf));
747 if (retval)
748 return -EFAULT;
749 if (loaddebug)
750 printk(KERN_DEBUG "b1capi: conf load: %d bytes ..", sizeof(buf));
751 for (i = 0; i < sizeof(buf); ) {
752 B1_put_byte(base, SEND_CONFIG);
753 for (j=0; j < 4; j++) {
754 B1_put_byte(base, buf[i++]);
755 }
756 }
757 if (loaddebug)
758 printk("ok\n");
759 left -= sizeof(buf);
760 dp += sizeof(buf);
761 }
762 if (left) {
763 retval = copy_from_user(buf, dp, left);
764 if (retval)
765 return -EFAULT;
766 if (loaddebug)
767 printk(KERN_DEBUG "b1capi: conf load: %d bytes ..", left);
768 for (i = 0; i < left; ) {
769 B1_put_byte(base, SEND_CONFIG);
770 for (j=0; j < 4; j++) {
771 if (i < left)
772 B1_put_byte(base, buf[i++]);
773 else
774 B1_put_byte(base, 0);
775 }
776 }
777 if (loaddebug)
778 printk("ok\n");
779 }
780 return 0;
781 }
782
783 int B1_loaded(unsigned int base)
784 {
785 int i;
786 unsigned char ans;
787
788 if (loaddebug)
789 printk(KERN_DEBUG "b1capi: loaded: wait 1 ..\n");
790 for (i = jiffies + 10 * HZ; time_before(jiffies, i);) {
791 if (B1_tx_empty(base))
792 break;
793 }
794 if (!B1_tx_empty(base)) {
795 printk(KERN_ERR "b1lli(0x%x): B1_loaded: timeout tx\n", base);
796 return 0;
797 }
798 B1_put_byte(base, SEND_POLL);
799 printk(KERN_DEBUG "b1capi: loaded: wait 2 ..\n");
800 for (i = jiffies + 10 * HZ; time_before(jiffies, i);) {
801 if (B1_rx_full(base)) {
802 if ((ans = B1_get_byte(base)) == RECEIVE_POLL) {
803 if (loaddebug)
804 printk(KERN_DEBUG "b1capi: loaded: ok\n");
805 return 1;
806 }
807 printk(KERN_ERR "b1lli(0x%x): B1_loaded: got 0x%x ???\n",
808 base, ans);
809 return 0;
810 }
811 }
812 printk(KERN_ERR "b1lli(0x%x): B1_loaded: timeout rx\n", base);
813 return 0;
814 }
815
816 /*
817 * -------------------------------------------------------------------
818 */
819 static inline void parse_version(avmb1_card * card)
820 {
821 int i, j;
822 for (j = 0; j < AVM_MAXVERSION; j++)
823 card->version[j] = "\0\0" + 1;
824 for (i = 0, j = 0;
825 j < AVM_MAXVERSION && i < card->versionlen;
826 j++, i += card->versionbuf[i] + 1)
827 card->version[j] = &card->versionbuf[i + 1];
828 }
829 /*
830 * -------------------------------------------------------------------
831 */
832
833 void B1_send_init(unsigned int port,
834 unsigned int napps, unsigned int nncci, unsigned int cardnr)
835 {
836 unsigned long flags;
837
838 save_flags(flags);
839 cli();
840 B1_put_byte(port, SEND_INIT);
841 B1_put_word(port, napps);
842 B1_put_word(port, nncci);
843 B1_put_word(port, cardnr);
844 restore_flags(flags);
845 }
846
847 void B1_send_register(unsigned int port,
848 __u16 appid, __u32 nmsg,
849 __u32 nb3conn, __u32 nb3blocks, __u32 b3bsize)
850 {
851 unsigned long flags;
852
853 save_flags(flags);
854 cli();
855 B1_put_byte(port, SEND_REGISTER);
856 B1_put_word(port, appid);
857 B1_put_word(port, nmsg);
858 B1_put_word(port, nb3conn);
859 B1_put_word(port, nb3blocks);
860 B1_put_word(port, b3bsize);
861 restore_flags(flags);
862 }
863
864 void B1_send_release(unsigned int port,
865 __u16 appid)
866 {
867 unsigned long flags;
868
869 save_flags(flags);
870 cli();
871 B1_put_byte(port, SEND_RELEASE);
872 B1_put_word(port, appid);
873 restore_flags(flags);
874 }
875
876 void B1_send_message(unsigned int port, struct sk_buff *skb)
877 {
878 unsigned long flags;
879 __u16 len = CAPIMSG_LEN(skb->data);
880 __u8 cmd = CAPIMSG_COMMAND(skb->data);
881 __u8 subcmd = CAPIMSG_SUBCOMMAND(skb->data);
882 __u32 contr = CAPIMSG_CONTROL(skb->data);
883
884 if (CAPICMD(cmd, subcmd) == CAPI_DATA_B3_REQ) {
885 __u16 dlen = CAPIMSG_DATALEN(skb->data);
886
887 if (showcapimsgs > 2) {
888 if (showcapimsgs & 1) {
889 printk(KERN_DEBUG "b1lli: Put [0x%lx] id#%d %s len=%u\n",
890 (unsigned long) contr,
891 CAPIMSG_APPID(skb->data),
892 capi_cmd2str(cmd, subcmd), len);
893 } else {
894 printk(KERN_DEBUG "b1lli: Put [0x%lx] %s\n",
895 (unsigned long) contr,
896 capi_message2str(skb->data));
897 }
898
899 }
900 save_flags(flags);
901 cli();
902 B1_put_byte(port, SEND_DATA_B3_REQ);
903 B1_put_slice(port, skb->data, len);
904 B1_put_slice(port, skb->data + len, dlen);
905 restore_flags(flags);
906 } else {
907 if (showcapimsgs) {
908
909 if (showcapimsgs & 1) {
910 printk(KERN_DEBUG "b1lli: Put [0x%lx] id#%d %s len=%u\n",
911 (unsigned long) contr,
912 CAPIMSG_APPID(skb->data),
913 capi_cmd2str(cmd, subcmd), len);
914 } else {
915 printk(KERN_DEBUG "b1lli: Put [0x%lx] %s\n", (unsigned long)contr, capi_message2str(skb->data));
916 }
917 }
918 save_flags(flags);
919 cli();
920 B1_put_byte(port, SEND_MESSAGE);
921 B1_put_slice(port, skb->data, len);
922 restore_flags(flags);
923 }
924 dev_kfree_skb(skb);
925 }
926
927 /*
928 * -------------------------------------------------------------------
929 */
930
931 void B1_handle_interrupt(avmb1_card * card)
932 {
933 unsigned char b1cmd;
934 struct sk_buff *skb;
935
936 unsigned ApplId;
937 unsigned MsgLen;
938 unsigned DataB3Len;
939 unsigned NCCI;
940 unsigned WindowSize;
941
942 t1retry:
943 if (!B1_rx_full(card->port))
944 return;
945
946 b1cmd = B1_get_byte(card->port);
947
948 switch (b1cmd) {
949
950 case RECEIVE_DATA_B3_IND:
951
952 ApplId = (unsigned) B1_get_word(card->port);
953 MsgLen = B1_get_slice(card->port, card->msgbuf);
954 DataB3Len = B1_get_slice(card->port, card->databuf);
955
956 if (showcapimsgs > 2) {
957 __u8 cmd = CAPIMSG_COMMAND(card->msgbuf);
958 __u8 subcmd = CAPIMSG_SUBCOMMAND(card->msgbuf);
959 __u32 contr = CAPIMSG_CONTROL(card->msgbuf);
960 CAPIMSG_SETDATA(card->msgbuf, card->databuf);
961 if (showcapimsgs & 1) {
962 printk(KERN_DEBUG "b1lli: Got [0x%lx] id#%d %s len=%u/%u\n",
963 (unsigned long) contr,
964 CAPIMSG_APPID(card->msgbuf),
965 capi_cmd2str(cmd, subcmd),
966 MsgLen, DataB3Len);
967 } else {
968 printk(KERN_DEBUG "b1lli: Got [0x%lx] %s\n", (unsigned long)contr, capi_message2str(card->msgbuf));
969 }
970 }
971 if (!(skb = dev_alloc_skb(DataB3Len + MsgLen))) {
972 printk(KERN_ERR "b1lli: incoming packet dropped\n");
973 } else {
974 memcpy(skb_put(skb, MsgLen), card->msgbuf, MsgLen);
975 memcpy(skb_put(skb, DataB3Len), card->databuf, DataB3Len);
976 CAPIMSG_SETDATA(skb->data, skb->data + MsgLen);
977 avmb1_handle_capimsg(card, ApplId, skb);
978 }
979 break;
980
981 case RECEIVE_MESSAGE:
982
983 ApplId = (unsigned) B1_get_word(card->port);
984 MsgLen = B1_get_slice(card->port, card->msgbuf);
985 if (showcapimsgs) {
986 __u8 cmd = CAPIMSG_COMMAND(card->msgbuf);
987 __u8 subcmd = CAPIMSG_SUBCOMMAND(card->msgbuf);
988 __u32 contr = CAPIMSG_CONTROL(card->msgbuf);
989 if (showcapimsgs & 1) {
990 printk(KERN_DEBUG "b1lli: Got [0x%lx] id#%d %s len=%u\n",
991 (unsigned long) contr,
992 CAPIMSG_APPID(card->msgbuf),
993 capi_cmd2str(cmd, subcmd),
994 MsgLen);
995 } else {
996 printk(KERN_DEBUG "b1lli: Got [0x%lx] %s\n",
997 (unsigned long) contr,
998 capi_message2str(card->msgbuf));
999 }
1000
1001 }
1002 if (!(skb = dev_alloc_skb(MsgLen))) {
1003 printk(KERN_ERR "b1lli: incoming packet dropped\n");
1004 } else {
1005 memcpy(skb_put(skb, MsgLen), card->msgbuf, MsgLen);
1006 avmb1_handle_capimsg(card, ApplId, skb);
1007 }
1008 break;
1009
1010 case RECEIVE_NEW_NCCI:
1011
1012 ApplId = B1_get_word(card->port);
1013 NCCI = B1_get_word(card->port);
1014 WindowSize = B1_get_word(card->port);
1015
1016 if (showcapimsgs)
1017 printk(KERN_DEBUG "b1lli(0x%x): NEW_NCCI app %u ncci 0x%x\n", card->port, ApplId, NCCI);
1018
1019 avmb1_handle_new_ncci(card, ApplId, NCCI, WindowSize);
1020
1021 break;
1022
1023 case RECEIVE_FREE_NCCI:
1024
1025 ApplId = B1_get_word(card->port);
1026 NCCI = B1_get_word(card->port);
1027
1028 if (showcapimsgs)
1029 printk(KERN_DEBUG "b1lli(0x%x): FREE_NCCI app %u ncci 0x%x\n", card->port, ApplId, NCCI);
1030
1031 avmb1_handle_free_ncci(card, ApplId, NCCI);
1032 break;
1033
1034 case RECEIVE_START:
1035 if (card->cardtype == AVM_CARDTYPE_T1) {
1036 B1_put_byte(card->port, SEND_POLLACK);
1037 /* printk(KERN_DEBUG "b1lli: T1 watchdog\n"); */
1038 }
1039 if (card->blocked)
1040 printk(KERN_DEBUG "b1lli(0x%x): RESTART\n", card->port);
1041 card->blocked = 0;
1042 break;
1043
1044 case RECEIVE_STOP:
1045 printk(KERN_DEBUG "b1lli(0x%x): STOP\n", card->port);
1046 card->blocked = 1;
1047 break;
1048
1049 case RECEIVE_INIT:
1050
1051 card->versionlen = B1_get_slice(card->port, card->versionbuf);
1052 card->cardstate = CARD_ACTIVE;
1053 parse_version(card);
1054 printk(KERN_INFO "b1lli(0x%x): %s-card (%s) now active\n",
1055 card->port,
1056 card->version[VER_CARDTYPE],
1057 card->version[VER_DRIVER]);
1058 avmb1_card_ready(card);
1059 break;
1060 case RECEIVE_TASK_READY:
1061 ApplId = (unsigned) B1_get_word(card->port);
1062 MsgLen = B1_get_slice(card->port, card->msgbuf);
1063 card->msgbuf[MsgLen] = 0;
1064 printk(KERN_INFO "b1lli(0x%x): Task %d \"%s\" ready.\n",
1065 card->port, ApplId, card->msgbuf);
1066 break;
1067 default:
1068 printk(KERN_ERR "b1lli(0x%x): B1_handle_interrupt: 0x%x ???\n",
1069 card->port, b1cmd);
1070 break;
1071 }
1072 if (card->cardtype == AVM_CARDTYPE_T1)
1073 goto t1retry;
1074 }