i386/linux/linux-2.3.21/drivers/net/a2065.h

   1 /*
   2  * Amiga Linux/68k A2065 Ethernet Driver
   3  *
   4  * (C) Copyright 1995 by Geert Uytterhoeven <geert@linux-m68k.org>
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * This program is based on
   9  *
  10  *      ariadne.?:      Amiga Linux/68k Ariadne Ethernet Driver
  11  *                      (C) Copyright 1995 by Geert Uytterhoeven,
  12  *                      Peter De Schrijver
  13  *
  14  *      lance.c:        An AMD LANCE ethernet driver for linux.
  15  *                      Written 1993-94 by Donald Becker.
  16  *
  17  *      Am79C960:       PCnet(tm)-ISA Single-Chip Ethernet Controller
  18  *                      Advanced Micro Devices
  19  *                      Publication #16907, Rev. B, Amendment/0, May 1994
  20  *
  21  * ---------------------------------------------------------------------------
  22  *
  23  * This file is subject to the terms and conditions of the GNU General Public
  24  * License.  See the file COPYING in the main directory of the Linux
  25  * distribution for more details.
  26  *
  27  * ---------------------------------------------------------------------------
  28  *
  29  * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
  30  *
  31  *      - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
  32  *        both 10BASE-2 (thin coax) and AUI (DB-15) connectors
  33  */
  34
  35
  36 /*
  37  *              Am7990 Local Area Network Controller for Ethernet (LANCE)
  38  */
  39
  40 struct lance_regs {
  41         unsigned short rdp;             /* Register Data Port */
  42         unsigned short rap;             /* Register Address Port */
  43 };
  44
  45
  46 #define CRC_POLYNOMIAL_BE 0x04c11db7UL  /* Ethernet CRC, big endian */
  47 #define CRC_POLYNOMIAL_LE 0xedb88320UL  /* Ethernet CRC, little endian */
  48
  49 /*
  50  *              Am7990 Control and Status Registers
  51  */
  52
  53 #define LE_CSR0         0x0000          /* LANCE Controller Status */
  54 #define LE_CSR1         0x0001          /* IADR[15:0] */
  55 #define LE_CSR2         0x0002          /* IADR[23:16] */
  56 #define LE_CSR3         0x0003          /* Misc */
  57
  58
  59 /*
  60  *              Bit definitions for CSR0 (LANCE Controller Status)
  61  */
  62
  63 #define LE_C0_ERR       0x8000          /* Error */
  64 #define LE_C0_BABL      0x4000          /* Babble: Transmitted too many bits */
  65 #define LE_C0_CERR      0x2000          /* No Heartbeat (10BASE-T) */
  66 #define LE_C0_MISS      0x1000          /* Missed Frame */
  67 #define LE_C0_MERR      0x0800          /* Memory Error */
  68 #define LE_C0_RINT      0x0400          /* Receive Interrupt */
  69 #define LE_C0_TINT      0x0200          /* Transmit Interrupt */
  70 #define LE_C0_IDON      0x0100          /* Initialization Done */
  71 #define LE_C0_INTR      0x0080          /* Interrupt Flag */
  72 #define LE_C0_INEA      0x0040          /* Interrupt Enable */
  73 #define LE_C0_RXON      0x0020          /* Receive On */
  74 #define LE_C0_TXON      0x0010          /* Transmit On */
  75 #define LE_C0_TDMD      0x0008          /* Transmit Demand */
  76 #define LE_C0_STOP      0x0004          /* Stop */
  77 #define LE_C0_STRT      0x0002          /* Start */
  78 #define LE_C0_INIT      0x0001          /* Initialize */
  79
  80
  81 /*
  82  *              Bit definitions for CSR3
  83  */
  84
  85 #define LE_C3_BSWP      0x0004          /* Byte Swap
  86                                            (on for big endian byte order) */
  87 #define LE_C3_ACON      0x0002          /* ALE Control
  88                                            (on for active low ALE) */
  89 #define LE_C3_BCON      0x0001          /* Byte Control */
  90
  91
  92 /*
  93  *              Mode Flags
  94  */
  95
  96 #define LE_MO_PROM      0x8000          /* Promiscuous Mode */
  97 #define LE_MO_INTL      0x0040          /* Internal Loopback */
  98 #define LE_MO_DRTY      0x0020          /* Disable Retry */
  99 #define LE_MO_FCOLL     0x0010          /* Force Collision */
 100 #define LE_MO_DXMTFCS   0x0008          /* Disable Transmit CRC */
 101 #define LE_MO_LOOP      0x0004          /* Loopback Enable */
 102 #define LE_MO_DTX       0x0002          /* Disable Transmitter */
 103 #define LE_MO_DRX       0x0001          /* Disable Receiver */
 104
 105
 106 struct lance_rx_desc {
 107         unsigned short rmd0;        /* low address of packet */
 108         unsigned char  rmd1_bits;   /* descriptor bits */
 109         unsigned char  rmd1_hadr;   /* high address of packet */
 110         short    length;            /* This length is 2s complement (negative)!
 111                                      * Buffer length
 112                                      */
 113         unsigned short mblength;    /* Aactual number of bytes received */
 114 };
 115
 116 struct lance_tx_desc {
 117         unsigned short tmd0;        /* low address of packet */
 118         unsigned char  tmd1_bits;   /* descriptor bits */
 119         unsigned char  tmd1_hadr;   /* high address of packet */
 120         short    length;            /* Length is 2s complement (negative)! */
 121         unsigned short misc;
 122 };
 123
 124
 125 /*
 126  *              Receive Flags
 127  */
 128
 129 #define LE_R1_OWN       0x80            /* LANCE owns the descriptor */
 130 #define LE_R1_ERR       0x40            /* Error */
 131 #define LE_R1_FRA       0x20            /* Framing Error */
 132 #define LE_R1_OFL       0x10            /* Overflow Error */
 133 #define LE_R1_CRC       0x08            /* CRC Error */
 134 #define LE_R1_BUF       0x04            /* Buffer Error */
 135 #define LE_R1_SOP       0x02            /* Start of Packet */
 136 #define LE_R1_EOP       0x01            /* End of Packet */
 137 #define LE_R1_POK       0x03            /* Packet is complete: SOP + EOP */
 138
 139
 140 /*
 141  *              Transmit Flags
 142  */
 143
 144 #define LE_T1_OWN       0x80            /* LANCE owns the descriptor */
 145 #define LE_T1_ERR       0x40            /* Error */
 146 #define LE_T1_RES       0x20            /* Reserved,
 147                                            LANCE writes this with a zero */
 148 #define LE_T1_EMORE     0x10            /* More than one retry needed */
 149 #define LE_T1_EONE      0x08            /* One retry needed */
 150 #define LE_T1_EDEF      0x04            /* Deferred */
 151 #define LE_T1_SOP       0x02            /* Start of Packet */
 152 #define LE_T1_EOP       0x01            /* End of Packet */
 153 #define LE_T1_POK       0x03            /* Packet is complete: SOP + EOP */
 154
 155
 156 /*
 157  *              Error Flags
 158  */
 159
 160 #define LE_T3_BUF       0x8000          /* Buffer Error */
 161 #define LE_T3_UFL       0x4000          /* Underflow Error */
 162 #define LE_T3_LCOL      0x1000          /* Late Collision */
 163 #define LE_T3_CLOS      0x0800          /* Loss of Carrier */
 164 #define LE_T3_RTY       0x0400          /* Retry Error */
 165 #define LE_T3_TDR       0x03ff          /* Time Domain Reflectometry */
 166
 167
 168 /*
 169  *              A2065 Expansion Board Structure
 170  */
 171
 172 struct A2065Board {
 173         u_char Pad1[0x4000];
 174         volatile struct lance_regs Lance;
 175         u_char Pad2[0x3ffc];
 176         volatile u_char RAM[0x8000];
 177 };