i386/linux/linux-2.3.21/drivers/net/atp.h

   1 #include <linux/if_ether.h>
   2 #include <linux/types.h>
   3 #include <asm/io.h>
   4
   5 struct net_local
   6 {
   7 #ifdef __KERNEL__
   8         struct net_device_stats stats;
   9 #endif
  10         ushort saved_tx_size;
  11         unsigned char
  12         re_tx,                  /* Number of packet retransmissions. */
  13         tx_unit_busy,
  14         addr_mode,              /* Current Rx filter e.g. promiscuous, etc. */
  15         pac_cnt_in_tx_buf;
  16 };
  17
  18 struct rx_header {
  19         ushort pad;                     /* The first read is always corrupted. */
  20         ushort rx_count;
  21         ushort rx_status;               /* Unknown bit assignments :-<.  */
  22         ushort cur_addr;                /* Apparently the current buffer address(?) */
  23 };
  24
  25 #define PAR_DATA        0
  26 #define PAR_STATUS      1
  27 #define PAR_CONTROL 2
  28
  29 #define Ctrl_LNibRead   0x08    /* LP_PSELECP */
  30 #define Ctrl_HNibRead   0
  31 #define Ctrl_LNibWrite  0x08    /* LP_PSELECP */
  32 #define Ctrl_HNibWrite  0
  33 #define Ctrl_SelData    0x04    /* LP_PINITP */
  34 #define Ctrl_IRQEN      0x10    /* LP_PINTEN */
  35
  36 #define EOW     0xE0
  37 #define EOC     0xE0
  38 #define WrAddr  0x40    /* Set address of EPLC read, write register. */
  39 #define RdAddr  0xC0
  40 #define HNib    0x10
  41
  42 enum page0_regs
  43 {
  44         /* The first six registers hold the ethernet physical station address. */
  45         PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
  46         TxCNT0 = 6, TxCNT1 = 7,         /* The transmit byte count. */
  47         TxSTAT = 8, RxSTAT = 9,         /* Tx and Rx status. */
  48         ISR = 10, IMR = 11,             /* Interrupt status and mask. */
  49         CMR1 = 12,                      /* Command register 1. */
  50         CMR2 = 13,                      /* Command register 2. */
  51         MAR = 14,                       /* Memory address register. */
  52         CMR2_h = 0x1d,
  53 };
  54
  55 enum eepage_regs
  56 { PROM_CMD = 6, PROM_DATA = 7 };        /* Note that PROM_CMD is in the "high" bits. */
  57
  58
  59 #define ISR_TxOK        0x01
  60 #define ISR_RxOK        0x04
  61 #define ISR_TxErr       0x02
  62 #define ISRh_RxErr      0x11    /* ISR, high nibble */
  63
  64 #define CMR1h_RESET     0x04    /* Reset. */
  65 #define CMR1h_RxENABLE  0x02    /* Rx unit enable.  */
  66 #define CMR1h_TxENABLE  0x01    /* Tx unit enable.  */
  67 #define CMR1h_TxRxOFF   0x00
  68 #define CMR1_ReXmit     0x08    /* Trigger a retransmit. */
  69 #define CMR1_Xmit       0x04    /* Trigger a transmit. */
  70 #define CMR1_IRQ        0x02    /* Interrupt active. */
  71 #define CMR1_BufEnb     0x01    /* Enable the buffer(?). */
  72 #define CMR1_NextPkt    0x01    /* Enable the buffer(?). */
  73
  74 #define CMR2_NULL       8
  75 #define CMR2_IRQOUT     9
  76 #define CMR2_RAMTEST    10
  77 #define CMR2_EEPROM     12      /* Set to page 1, for reading the EEPROM. */
  78
  79 #define CMR2h_OFF       0       /* No accept mode. */
  80 #define CMR2h_Physical  1       /* Accept a physical address match only. */
  81 #define CMR2h_Normal    2       /* Accept physical and broadcast address. */
  82 #define CMR2h_PROMISC   3       /* Promiscuous mode. */
  83
  84 /* An inline function used below: it differs from inb() by explicitly return an unsigned
  85    char, saving a truncation. */
  86
  87 extern inline unsigned char inbyte(unsigned short port)
  88 {
  89         unsigned char _v;
  90         __asm__ __volatile__ ("inb %w1,%b0" :"=a" (_v):"d" (port));
  91         return _v;
  92 }
  93
  94 /* Read register OFFSET.
  95    This command should always be terminated with read_end(). */
  96
  97 extern inline unsigned char read_nibble(short port, unsigned char offset)
  98 {
  99         unsigned char retval;
 100         outb(EOC+offset, port + PAR_DATA);
 101         outb(RdAddr+offset, port + PAR_DATA);
 102         inbyte(port + PAR_STATUS);              /* Settling time delay */
 103         retval = inbyte(port + PAR_STATUS);
 104         outb(EOC+offset, port + PAR_DATA);
 105
 106         return retval;
 107 }
 108
 109 /* Functions for bulk data read.  The interrupt line is always disabled. */
 110 /* Get a byte using read mode 0, reading data from the control lines. */
 111
 112 extern inline unsigned char read_byte_mode0(short ioaddr)
 113 {
 114         unsigned char low_nib;
 115
 116         outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
 117         inbyte(ioaddr + PAR_STATUS);
 118         low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
 119         outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
 120         inbyte(ioaddr + PAR_STATUS);    /* Settling time delay -- needed!  */
 121         inbyte(ioaddr + PAR_STATUS);    /* Settling time delay -- needed!  */
 122         return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
 123 }
 124
 125 /* The same as read_byte_mode0(), but does multiple inb()s for stability. */
 126
 127 extern inline unsigned char read_byte_mode2(short ioaddr)
 128 {
 129         unsigned char low_nib;
 130
 131         outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
 132         inbyte(ioaddr + PAR_STATUS);
 133         low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
 134         outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
 135         inbyte(ioaddr + PAR_STATUS);    /* Settling time delay -- needed!  */
 136         return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
 137 }
 138
 139 /* Read a byte through the data register. */
 140
 141 extern inline unsigned char read_byte_mode4(short ioaddr)
 142 {
 143         unsigned char low_nib;
 144
 145         outb(RdAddr | MAR, ioaddr + PAR_DATA);
 146         low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
 147         outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
 148         return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
 149 }
 150
 151 /* Read a byte through the data register, double reading to allow settling. */
 152
 153 extern inline unsigned char read_byte_mode6(short ioaddr)
 154 {
 155         unsigned char low_nib;
 156
 157         outb(RdAddr | MAR, ioaddr + PAR_DATA);
 158         inbyte(ioaddr + PAR_STATUS);
 159         low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
 160         outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
 161         inbyte(ioaddr + PAR_STATUS);
 162         return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
 163 }
 164
 165 extern inline void write_reg(short port, unsigned char reg, unsigned char value)
 166 {
 167         unsigned char outval;
 168         outb(EOC | reg, port + PAR_DATA);
 169         outval = WrAddr | reg;
 170         outb(outval, port + PAR_DATA);
 171         outb(outval, port + PAR_DATA);  /* Double write for PS/2. */
 172
 173         outval &= 0xf0;
 174         outval |= value;
 175         outb(outval, port + PAR_DATA);
 176         outval &= 0x1f;
 177         outb(outval, port + PAR_DATA);
 178         outb(outval, port + PAR_DATA);
 179
 180         outb(EOC | outval, port + PAR_DATA);
 181 }
 182
 183 extern inline void write_reg_high(short port, unsigned char reg, unsigned char value)
 184 {
 185         unsigned char outval = EOC | HNib | reg;
 186
 187         outb(outval, port + PAR_DATA);
 188         outval &= WrAddr | HNib | 0x0f;
 189         outb(outval, port + PAR_DATA);
 190         outb(outval, port + PAR_DATA);  /* Double write for PS/2. */
 191
 192         outval = WrAddr | HNib | value;
 193         outb(outval, port + PAR_DATA);
 194         outval &= HNib | 0x0f;          /* HNib | value */
 195         outb(outval, port + PAR_DATA);
 196         outb(outval, port + PAR_DATA);
 197
 198         outb(EOC | HNib | outval, port + PAR_DATA);
 199 }
 200
 201 /* Write a byte out using nibble mode.  The low nibble is written first. */
 202
 203 extern inline void write_reg_byte(short port, unsigned char reg, unsigned char value)
 204 {
 205         unsigned char outval;
 206         outb(EOC | reg, port + PAR_DATA);       /* Reset the address register. */
 207         outval = WrAddr | reg;
 208         outb(outval, port + PAR_DATA);
 209         outb(outval, port + PAR_DATA);          /* Double write for PS/2. */
 210
 211         outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
 212         outb(value & 0x0f, port + PAR_DATA);
 213         value >>= 4;
 214         outb(value, port + PAR_DATA);
 215         outb(0x10 | value, port + PAR_DATA);
 216         outb(0x10 | value, port + PAR_DATA);
 217
 218         outb(EOC  | value, port + PAR_DATA);    /* Reset the address register. */
 219 }
 220
 221 /*
 222  * Bulk data writes to the packet buffer.  The interrupt line remains enabled.
 223  * The first, faster method uses only the dataport (data modes 0, 2 & 4).
 224  * The second (backup) method uses data and control regs (modes 1, 3 & 5).
 225  * It should only be needed when there is skew between the individual data
 226  * lines.
 227  */
 228
 229 extern inline void write_byte_mode0(short ioaddr, unsigned char value)
 230 {
 231         outb(value & 0x0f, ioaddr + PAR_DATA);
 232         outb((value>>4) | 0x10, ioaddr + PAR_DATA);
 233 }
 234
 235 extern inline void write_byte_mode1(short ioaddr, unsigned char value)
 236 {
 237         outb(value & 0x0f, ioaddr + PAR_DATA);
 238         outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
 239         outb((value>>4) | 0x10, ioaddr + PAR_DATA);
 240         outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
 241 }
 242
 243 /* Write 16bit VALUE to the packet buffer: the same as above just doubled. */
 244
 245 extern inline void write_word_mode0(short ioaddr, unsigned short value)
 246 {
 247         outb(value & 0x0f, ioaddr + PAR_DATA);
 248         value >>= 4;
 249         outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
 250         value >>= 4;
 251         outb(value & 0x0f, ioaddr + PAR_DATA);
 252         value >>= 4;
 253         outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
 254 }
 255
 256 /*  EEPROM_Ctrl bits. */
 257 #define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
 258 #define EE_CS           0x02    /* EEPROM chip select. */
 259 #define EE_CLK_HIGH     0x12
 260 #define EE_CLK_LOW      0x16
 261 #define EE_DATA_WRITE   0x01    /* EEPROM chip data in. */
 262 #define EE_DATA_READ    0x08    /* EEPROM chip data out. */
 263
 264 /* The EEPROM commands include the alway-set leading bit. */
 265 #define EE_WRITE_CMD(offset)    (((5 << 6) + (offset)) << 17)
 266 #define EE_READ(offset)         (((6 << 6) + (offset)) << 17)
 267 #define EE_ERASE(offset)        (((7 << 6) + (offset)) << 17)
 268 #define EE_CMD_SIZE     27      /* The command+address+data size. */