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* add p cc
[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / net / dmfe.c
blob81cb3edb22bc38bea92a17e22eebc6d57d526671
1 /*
2 dmfe.c: Version 1.26
3
4 A Davicom DM9102 fast ethernet driver for Linux.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, version 1.
9
10 Compiler command:
11 "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net/inet -Wall
12 -Wstrict-prototypes -O6 -c dmfe.c"
13
14 The following steps teach you how to active DM9102 board:
15 1. Used the upper compiler command to compile dmfe.c
16 2. insert dmfe module into kernel
17 "insmod dmfe" ;;Auto Detection Mode
18 "insmod dmfe mode=0" ;;Force 10M Half Duplex
19 "insmod dmfe mode=1" ;;Force 100M Half Duplex
20 "insmod dmfe mode=4" ;;Force 10M Full Duplex
21 "insmod dmfe mode=5" ;;Force 100M Full Duplex
22 3. config a dm9102 network interface
23 "ifconfig eth0 172.22.3.18"
24 4. active the IP routing table
25 "route add -net 172.22.3.0 eth0"
26 5. Well done. Your DM9102 adapter actived now.
27
28 Author: Sten Wang, E-mail: sten_wang@davicom.com.tw
29
30 Date: 10/28,1998
31
32 (C)Copyright 1997-1998 DAVICOM Semiconductor, Inc. All Rights Reserved.
33
34 Marcelo Tosatti <marcelo@conectiva.com.br> :
35 Made it compile in 2.3 (device to net_device)
36
37 Alan Cox <alan@redhat.com> :
38 Removed the back compatibility support
39 Reformatted, fixing spelling etc as I went
40 Removed IRQ 0-15 assumption
41
42 TODO
43
44 Check and fix on 64bit and big endian boxes.
45 Sort out the PCI latency.
46
47 */
48
49 #include <linux/config.h>
50 #include <linux/module.h>
51
52 #include <linux/kernel.h>
53 #include <linux/sched.h>
54 #include <linux/string.h>
55 #include <linux/timer.h>
56 #include <linux/ptrace.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/malloc.h>
60 #include <linux/interrupt.h>
61 #include <linux/pci.h>
62 #include <linux/version.h>
63
64 #include <linux/delay.h>
65 #include <asm/processor.h>
66 #include <asm/bitops.h>
67 #include <asm/io.h>
68 #include <asm/dma.h>
69
70 #include <linux/netdevice.h>
71 #include <linux/etherdevice.h>
72 #include <linux/skbuff.h>
73
74
75 /* Board/System/Debug information/definition ---------------- */
76 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
77 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
78
79 #define DMFE_SUCC 0
80 #define DM9102_IO_SIZE 0x80
81 #define TX_FREE_DESC_CNT 0x1 /* Tx packet count */
82 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
83 #define RX_DESC_CNT 0x10 /* Allocated Rx descriptors */
84 #define DESC_ALL_CNT TX_DESC_CNT+RX_DESC_CNT
85 #define TX_BUF_ALLOC 0x600
86 #define RX_ALLOC_SIZE 0x620
87 #define DM910X_RESET 1
88 #define CR6_DEFAULT 0x002c0000 /* SF, MII, HD */
89 #define CR7_DEFAULT 0x1a2cd
90 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
91 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
92 #define MAX_PACKET_SIZE 1514
93 #define DMFE_MAX_MULTICAST 14
94 #define RX_MAX_TRAFFIC 0x5000
95 #define MAX_CHECK_PACKET 0x8000
96
97 #define DMFE_10MHF 0
98 #define DMFE_100MHF 1
99 #define DMFE_10MFD 4
100 #define DMFE_100MFD 5
101 #define DMFE_AUTO 8
102
103 #define DMFE_TIMER_WUT jiffies+HZ*1 /* timer wakeup time : 1 second */
104 #define DMFE_TX_TIMEOUT HZ*2 /* tx packet time-out time */
105
106 #define DMFE_DBUG(dbug_now, msg, vaule) if (dmfe_debug || dbug_now) printk("DBUG: %s %x\n", msg, vaule)
107
108 #define DELAY_5US udelay(5) /* udelay scale 1 usec */
109
110 #define DELAY_1US udelay(1) /* udelay scale 1 usec */
111
112 #define SHOW_MEDIA_TYPE(mode) printk("\n<WARN> Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
113
114
115 /* CR9 definition: SROM/MII */
116 #define CR9_SROM_READ 0x4800
117 #define CR9_SRCS 0x1
118 #define CR9_SRCLK 0x2
119 #define CR9_CRDOUT 0x8
120 #define SROM_DATA_0 0x0
121 #define SROM_DATA_1 0x4
122 #define PHY_DATA_1 0x20000
123 #define PHY_DATA_0 0x00000
124 #define MDCLKH 0x10000
125
126 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;
127
128 /* Structure/enum declaration ------------------------------- */
129 struct tx_desc {
130 u32 tdes0, tdes1, tdes2, tdes3;
131 u32 tx_skb_ptr;
132 u32 tx_buf_ptr;
133 u32 next_tx_desc;
134 u32 reserved;
135 };
136
137 struct rx_desc {
138 u32 rdes0, rdes1, rdes2, rdes3;
139 u32 rx_skb_ptr;
140 u32 rx_buf_ptr;
141 u32 next_rx_desc;
142 u32 reserved;
143 };
144
145 struct dmfe_board_info {
146 u32 chip_id; /* Chip vendor/Device ID */
147 u32 chip_revesion; /* Chip revesion */
148 struct net_device *next_dev; /* next device */
149
150 struct pci_dev *net_dev; /* PCI device */
151
152 u32 ioaddr; /* I/O base address */
153 u32 cr5_data;
154 u32 cr6_data;
155 u32 cr7_data;
156 u32 cr15_data;
157
158 /* descriptor pointer */
159 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
160 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
161 unsigned char *desc_pool_ptr; /* descriptor pool memory */
162 struct tx_desc *first_tx_desc;
163 struct tx_desc *tx_insert_ptr;
164 struct tx_desc *tx_remove_ptr;
165 struct rx_desc *first_rx_desc;
166 struct rx_desc *rx_insert_ptr;
167 struct rx_desc *rx_ready_ptr; /* packet come pointer */
168 u32 tx_packet_cnt; /* transmitted packet count */
169 u32 rx_avail_cnt; /* available rx descriptor count */
170 u32 interval_rx_cnt; /* rx packet count a callback time */
171
172 u8 media_mode; /* user specify media mode */
173 u8 op_mode; /* real work media mode */
174 u8 phy_addr;
175 u8 link_failed; /* Ever link failed */
176 u8 wait_reset; /* Hardware failed, need to reset */
177 u8 in_reset_state; /* Now driver in reset routine */
178 u8 rx_error_cnt; /* recievd abnormal case count */
179 u8 dm910x_chk_mode; /* Operating mode check */
180 struct timer_list timer;
181 struct enet_statistics stats; /* statistic counter */
182 unsigned char srom[128];
183 };
184
185 enum dmfe_offsets {
186 DCR0 = 0, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, DCR5 = 0x28,
187 DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58,
188 DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, DCR15 = 0x78
189 };
190
191 enum dmfe_CR6_bits {
192 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, CR6_FDM = 0x200,
193 CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000, CR6_RXA = 0x40000000
194 };
195
196 /* Global variable declaration ----------------------------- */
197
198 static int dmfe_debug = 0;
199 static unsigned char dmfe_media_mode = 8;
200 static struct net_device *dmfe_root_dev = NULL; /* First device */
201 static u32 dmfe_cr6_user_set = 0;
202
203 /* For module input parameter */
204 static int debug = 0;
205 static u32 cr6set = 0;
206 static unsigned char mode = 8;
207 static u8 chkmode = 1;
208
209 unsigned long CrcTable[256] =
210 {
211 0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL,
212 0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L,
213 0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L,
214 0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L,
215 0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL,
216 0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L,
217 0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL,
218 0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L,
219 0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L,
220 0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL,
221 0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L,
222 0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L,
223 0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L,
224 0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL,
225 0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L,
226 0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL,
227 0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL,
228 0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L,
229 0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L,
230 0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L,
231 0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL,
232 0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L,
233 0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL,
234 0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L,
235 0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L,
236 0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL,
237 0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L,
238 0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L,
239 0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L,
240 0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL,
241 0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L,
242 0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL,
243 0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL,
244 0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L,
245 0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L,
246 0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L,
247 0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL,
248 0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L,
249 0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL,
250 0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L,
251 0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L,
252 0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL,
253 0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L,
254 0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L,
255 0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L,
256 0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL,
257 0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L,
258 0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL,
259 0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL,
260 0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L,
261 0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L,
262 0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L,
263 0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL,
264 0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L,
265 0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL,
266 0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L,
267 0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L,
268 0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL,
269 0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L,
270 0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L,
271 0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L,
272 0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL,
273 0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L,
274 0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL
275 };
276
277 /* function declaration ------------------------------------- */
278 int dmfe_reg_board(struct net_device *);
279 static int dmfe_open(struct net_device *);
280 static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
281 static int dmfe_stop(struct net_device *);
282 static struct enet_statistics *dmfe_get_stats(struct net_device *);
283 static void dmfe_set_filter_mode(struct net_device *);
284 static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
285 static u16 read_srom_word(long, int);
286 static void dmfe_interrupt(int, void *, struct pt_regs *);
287 static void dmfe_descriptor_init(struct dmfe_board_info *, u32);
288 static void allocated_rx_buffer(struct dmfe_board_info *);
289 static void update_cr6(u32, u32);
290 static void send_filter_frame(struct net_device *, int);
291 static u16 phy_read(u32, u8, u8);
292 static void phy_write(u32, u8, u8, u16);
293 static void phy_write_1bit(u32, u32);
294 static u16 phy_read_1bit(u32);
295 static void parser_ctrl_info(struct dmfe_board_info *);
296 static void dmfe_sense_speed(struct dmfe_board_info *);
297 static void dmfe_process_mode(struct dmfe_board_info *);
298 static void dmfe_timer(unsigned long);
299 static void dmfe_rx_packet(struct net_device *, struct dmfe_board_info *);
300 static void dmfe_reused_skb(struct dmfe_board_info *, struct sk_buff *);
301 static void dmfe_dynamic_reset(struct net_device *);
302 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
303 static void dmfe_init_dm910x(struct net_device *);
304 static unsigned long cal_CRC(unsigned char *, unsigned int);
305
306 /* DM910X network board routine ---------------------------- */
307
308 /*
309 * Search DM910X board, allocate space and register it
310 */
311
312 int dmfe_reg_board(struct net_device *dev)
313 {
314 u32 pci_iobase;
315 u16 dm9102_count = 0;
316 u8 pci_irqline;
317 static int index = 0; /* For multiple call */
318 struct dmfe_board_info *db; /* Point a board information structure */
319 int i;
320 struct pci_dev *net_dev = NULL;
321
322 DMFE_DBUG(0, "dmfe_reg_board()", 0);
323
324 if (!pci_present())
325 return -ENODEV;
326
327 index = 0;
328 while ((net_dev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, net_dev)))
329 {
330 u32 pci_id;
331 u8 pci_cmd;
332
333 index++;
334 if (pci_read_config_dword(net_dev, PCI_VENDOR_ID, &pci_id) != DMFE_SUCC)
335 continue;
336
337 if (pci_id != PCI_DM9102_ID)
338 continue;
339
340 pci_iobase = net_dev->resource[0].start;
341 pci_irqline = net_dev->irq;
342
343 /* Enable Master/IO access, Disable memory access */
344
345 pci_set_master(net_dev);
346
347 pci_read_config_byte(net_dev, PCI_COMMAND, &pci_cmd);
348 pci_cmd |= PCI_COMMAND_IO;
349 pci_cmd &= ~PCI_COMMAND_MEMORY;
350 pci_write_config_byte(net_dev, PCI_COMMAND, pci_cmd);
351
352 /* Set Latency Timer 80h */
353
354 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
355 Need a PCI quirk.. */
356
357 pci_write_config_byte(net_dev, PCI_LATENCY_TIMER, 0x80);
358
359 /* IO range and interrupt check */
360
361 if (check_region(pci_iobase, DM9102_IO_SIZE)) /* IO range check */
362 continue;
363
364 /* Found DM9102 card and PCI resource allocated OK */
365 dm9102_count++; /* Found a DM9102 card */
366
367 /* Init network device */
368 dev = init_etherdev(dev, 0);
369
370 /* Allocated board information structure */
371 db = (void *) (kmalloc(sizeof(*db), GFP_KERNEL | GFP_DMA));
372 if(db==NULL)
373 continue; /* Out of memory */
374
375 memset(db, 0, sizeof(*db));
376 dev->priv = db; /* link device and board info */
377 db->next_dev = dmfe_root_dev;
378 dmfe_root_dev = dev;
379
380 db->chip_id = pci_id; /* keep Chip vandor/Device ID */
381 db->ioaddr = pci_iobase;
382 pci_read_config_dword(net_dev, 8, &db->chip_revesion);
383
384 db->net_dev = net_dev;
385
386 dev->base_addr = pci_iobase;
387 dev->irq = pci_irqline;
388 dev->open = &dmfe_open;
389 dev->hard_start_xmit = &dmfe_start_xmit;
390 dev->stop = &dmfe_stop;
391 dev->get_stats = &dmfe_get_stats;
392 dev->set_multicast_list = &dmfe_set_filter_mode;
393 dev->do_ioctl = &dmfe_do_ioctl;
394
395 request_region(pci_iobase, DM9102_IO_SIZE, dev->name);
396
397 /* read 64 word srom data */
398 for (i = 0; i < 64; i++)
399 ((u16 *) db->srom)[i] = read_srom_word(pci_iobase, i);
400
401 /* Set Node address */
402 for (i = 0; i < 6; i++)
403 dev->dev_addr[i] = db->srom[20 + i];
404
405 dev = 0; /* NULL device */
406 }
407
408 #ifdef MODULE
409 if (!dm9102_count)
410 printk(KERN_WARNING "dmfe: Can't find DM910X board\n");
411 #endif
412 return dm9102_count ? 0 : -ENODEV;
413 }
414
415 /*
416 * Open the interface.
417 * The interface is opened whenever "ifconfig" actives it.
418 */
419
420 static int dmfe_open(struct net_device *dev)
421 {
422 struct dmfe_board_info *db = dev->priv;
423
424 DMFE_DBUG(0, "dmfe_open", 0);
425
426 if (request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev))
427 return -EAGAIN;
428
429 /* Allocated Tx/Rx descriptor memory */
430 db->desc_pool_ptr = kmalloc(sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, GFP_KERNEL | GFP_DMA);
431 if (db->desc_pool_ptr == NULL)
432 return -ENOMEM;
433
434 if ((u32) db->desc_pool_ptr & 0x1f)
435 db->first_tx_desc = (struct tx_desc *) (((u32) db->desc_pool_ptr & ~0x1f) + 0x20);
436 else
437 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
438
439 /* Allocated Tx buffer memory */
440
441 db->buf_pool_ptr = kmalloc(TX_BUF_ALLOC * TX_DESC_CNT + 4, GFP_KERNEL | GFP_DMA);
442 if (db->buf_pool_ptr == NULL) {
443 kfree(db->desc_pool_ptr);
444 return -ENOMEM;
445 }
446
447 if ((u32) db->buf_pool_ptr & 0x3)
448 db->buf_pool_start = (char *) (((u32) db->buf_pool_ptr & ~0x3) + 0x4);
449 else
450 db->buf_pool_start = db->buf_pool_ptr;
451
452 /* system variable init */
453 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
454 db->tx_packet_cnt = 0;
455 db->rx_avail_cnt = 0;
456 db->link_failed = 0;
457 db->wait_reset = 0;
458 db->in_reset_state = 0;
459 db->rx_error_cnt = 0;
460
461 if (chkmode && (db->chip_revesion < 0x02000030)) {
462 db->dm910x_chk_mode = 1; /* Enter the check mode */
463 } else {
464 db->dm910x_chk_mode = 4; /* Enter the normal mode */
465 }
466
467 /* Initilize DM910X board */
468 dmfe_init_dm910x(dev);
469
470 /* Active System Interface */
471 dev->tbusy = 0; /* Can transmit packet */
472 dev->start = 1; /* interface ready */
473 MOD_INC_USE_COUNT;
474
475 /* set and active a timer process */
476 init_timer(&db->timer);
477 db->timer.expires = DMFE_TIMER_WUT;
478 db->timer.data = (unsigned long) dev;
479 db->timer.function = &dmfe_timer;
480 add_timer(&db->timer);
481
482 return 0;
483 }
484
485 /*
486 * Initialize DM910X board
487 * Reset DM910X board
488 * Initialize TX/Rx descriptor chain structure
489 * Send the set-up frame
490 * Enable Tx/Rx machine
491 */
492
493 static void dmfe_init_dm910x(struct net_device *dev)
494 {
495 struct dmfe_board_info *db = dev->priv;
496 u32 ioaddr = db->ioaddr;
497
498 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
499
500 /* Reset DM910x board : need 32 PCI clock to complete */
501 outl(DM910X_RESET, ioaddr + DCR0);
502 DELAY_5US;
503 outl(0, ioaddr + DCR0);
504
505 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
506 outl(0x80, ioaddr + DCR12); /* Reset DM9102 phyxcer */
507 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
508
509 /* Parser control information: Phy addr */
510 parser_ctrl_info(db);
511 db->media_mode = dmfe_media_mode;
512 if (db->media_mode & DMFE_AUTO)
513 dmfe_sense_speed(db);
514 else
515 db->op_mode = db->media_mode;
516 dmfe_process_mode(db);
517
518 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
519 dmfe_descriptor_init(db, ioaddr);
520
521 /* Init CR6 to program DM910x operation */
522 update_cr6(db->cr6_data, ioaddr);
523
524 /* Send setup frame */
525 send_filter_frame(dev, 0);
526
527 /* Init CR5/CR7, interrupt active bit */
528 outl(0xffffffff, ioaddr + DCR5); /* clear all CR5 status */
529 db->cr7_data = CR7_DEFAULT;
530 outl(db->cr7_data, ioaddr + DCR7);
531
532 /* Init CR15, Tx jabber and Rx watchdog timer */
533 db->cr15_data = CR15_DEFAULT;
534 outl(db->cr15_data, ioaddr + DCR15);
535
536 /* Enable DM910X Tx/Rx function */
537 db->cr6_data |= CR6_RXSC | CR6_TXSC;
538 update_cr6(db->cr6_data, ioaddr);
539
540 }
541
542
543 /*
544 * Hardware start transmission.
545 * Send a packet to media from the upper layer.
546 */
547
548 static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
549 {
550 struct dmfe_board_info *db = dev->priv;
551 struct tx_desc *txptr;
552
553 DMFE_DBUG(0, "dmfe_start_xmit", 0);
554
555 if ((dev->tbusy == 1) && (db->tx_packet_cnt != 0))
556 return 1;
557 else
558 dev->tbusy = 0;
559
560 /* Too large packet check */
561 if (skb->len > MAX_PACKET_SIZE) {
562 printk(KERN_ERR "%s: oversized frame (%d bytes) received.\n", dev->name, (u16) skb->len);
563 dev_kfree_skb(skb);
564 return 0;
565 }
566 /* No Tx resource check, it never happen nromally */
567 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
568 printk(KERN_WARNING "%s: No Tx resource, enter xmit() again \n", dev->name);
569 dev_kfree_skb(skb);
570 dev->tbusy = 1;
571 return -EBUSY;
572 }
573
574 /* transmit this packet */
575 txptr = db->tx_insert_ptr;
576 memcpy((char *) txptr->tx_buf_ptr, (char *) skb->data, skb->len);
577 txptr->tdes1 = 0xe1000000 | skb->len;
578 txptr->tdes0 = 0x80000000; /* set owner bit to DM910X */
579
580 /* Point to next transmit free descriptor */
581 db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
582
583 /* transmit counter increase 1 */
584 db->tx_packet_cnt++;
585 db->stats.tx_packets++;
586
587 /* issue Tx polling command */
588 outl(0x1, dev->base_addr + DCR1);
589
590 /* Tx resource check */
591 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT)
592 dev->tbusy = 1;
593
594 /* Set transmit time stamp */
595 dev->trans_start = jiffies; /* saved the time stamp */
596
597 /* free this SKB */
598 dev_kfree_skb(skb);
599 return 0;
600 }
601
602 /*
603 * Stop the interface.
604 * The interface is stopped when it is brought.
605 */
606
607 static int dmfe_stop(struct net_device *dev)
608 {
609 struct dmfe_board_info *db = dev->priv;
610 u32 ioaddr = dev->base_addr;
611
612 DMFE_DBUG(0, "dmfe_stop", 0);
613
614 /* disable system */
615 dev->start = 0; /* interface disable */
616 dev->tbusy = 1; /* can't transmit */
617
618 /* Reset & stop DM910X board */
619 outl(DM910X_RESET, ioaddr + DCR0);
620 DELAY_5US;
621
622 /* deleted timer */
623 del_timer(&db->timer);
624
625 /* free interrupt */
626 free_irq(dev->irq, dev);
627
628 /* free allocated rx buffer */
629 dmfe_free_rxbuffer(db);
630
631 /* free all descriptor memory and buffer memory */
632 kfree(db->desc_pool_ptr);
633 kfree(db->buf_pool_ptr);
634
635 MOD_DEC_USE_COUNT;
636
637 return 0;
638 }
639
640 /*
641 * DM9102 insterrupt handler
642 * receive the packet to upper layer, free the transmitted packet
643 */
644
645 static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
646 {
647 struct net_device *dev = dev_id;
648 struct tx_desc *txptr;
649 struct dmfe_board_info *db;
650 u32 ioaddr;
651
652 if (!dev) {
653 DMFE_DBUG(1, "dmfe_interrupt() without device arg", 0);
654 return;
655 }
656 if (dev->interrupt) {
657 DMFE_DBUG(1, "dmfe_interrupt() re-entry ", 0);
658 return;
659 }
660
661 /* A real interrupt coming */
662 dev->interrupt = 1; /* Lock interrupt */
663 db = (struct dmfe_board_info *) dev->priv;
664 ioaddr = dev->base_addr;
665
666 DMFE_DBUG(0, "dmfe_interrupt()", 0);
667
668 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
669 outl(0, ioaddr + DCR7);
670
671 /* Got DM910X status */
672 db->cr5_data = inl(ioaddr + DCR5);
673 outl(db->cr5_data, ioaddr + DCR5);
674 /* printk("CR5=%x\n", db->cr5_data); */
675
676 /* Check system status */
677 if (db->cr5_data & 0x2000) {
678 /* A system bus error occurred */
679 DMFE_DBUG(1, "A system bus error occurred. CR5=", db->cr5_data);
680 dev->tbusy = 1;
681 db->wait_reset = 1; /* Need to RESET */
682 outl(0, ioaddr + DCR7); /* disable all interrupt */
683 dev->interrupt = 0; /* unlock interrupt */
684 return;
685 }
686 /* Free the transmitted descriptor */
687 txptr = db->tx_remove_ptr;
688 while (db->tx_packet_cnt) {
689 /* printk("tdes0=%x\n", txptr->tdes0); */
690 if (txptr->tdes0 & 0x80000000)
691 break;
692 if ((txptr->tdes0 & TDES0_ERR_MASK) && (txptr->tdes0 != 0x7fffffff)) {
693 /* printk("tdes0=%x\n", txptr->tdes0); */
694 db->stats.tx_errors++;
695 }
696 txptr = (struct tx_desc *) txptr->next_tx_desc;
697 db->tx_packet_cnt--;
698 }
699 db->tx_remove_ptr = (struct tx_desc *) txptr;
700
701 if (dev->tbusy && (db->tx_packet_cnt < TX_FREE_DESC_CNT)) {
702 dev->tbusy = 0; /* free a resource */
703 mark_bh(NET_BH); /* active bottom half */
704 }
705 /* Received the coming packet */
706 if (db->rx_avail_cnt)
707 dmfe_rx_packet(dev, db);
708
709 /* reallocated rx descriptor buffer */
710 if (db->rx_avail_cnt < RX_DESC_CNT)
711 allocated_rx_buffer(db);
712
713 /* Mode Check */
714 if (db->dm910x_chk_mode & 0x2) {
715 db->dm910x_chk_mode = 0x4;
716 db->cr6_data |= 0x100;
717 update_cr6(db->cr6_data, db->ioaddr);
718 }
719 dev->interrupt = 0; /* release interrupt lock */
720
721 /* Restore CR7 to enable interrupt mask */
722
723 if (db->interval_rx_cnt > RX_MAX_TRAFFIC)
724 db->cr7_data = 0x1a28d;
725 else
726 db->cr7_data = 0x1a2cd;
727 outl(db->cr7_data, ioaddr + DCR7);
728 }
729
730 /*
731 * Receive the come packet and pass to upper layer
732 */
733
734 static void dmfe_rx_packet(struct net_device *dev, struct dmfe_board_info *db)
735 {
736 struct rx_desc *rxptr;
737 struct sk_buff *skb;
738 int rxlen;
739
740 rxptr = db->rx_ready_ptr;
741
742 while (db->rx_avail_cnt) {
743 if (rxptr->rdes0 & 0x80000000) /* packet owner check */
744 break;
745
746 db->rx_avail_cnt--;
747 db->interval_rx_cnt++;
748
749 if ((rxptr->rdes0 & 0x300) != 0x300) {
750 /* A packet without First/Last flag */
751 /* reused this SKB */
752 DMFE_DBUG(0, "Reused SK buffer, rdes0", rxptr->rdes0);
753 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
754 db->rx_error_cnt++;
755 } else {
756 rxlen = ((rxptr->rdes0 >> 16) & 0x3fff) - 4; /* skip CRC */
757
758 /* A packet with First/Last flag */
759 if (rxptr->rdes0 & 0x8000) { /* error summary bit check */
760 /* This is a error packet */
761 /* printk("rdes0 error : %x \n", rxptr->rdes0); */
762 db->stats.rx_errors++;
763 if (rxptr->rdes0 & 1)
764 db->stats.rx_fifo_errors++;
765 if (rxptr->rdes0 & 2)
766 db->stats.rx_crc_errors++;
767 if (rxptr->rdes0 & 0x80)
768 db->stats.rx_length_errors++;
769 }
770 if (!(rxptr->rdes0 & 0x8000) ||
771 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
772 skb = (struct sk_buff *) rxptr->rx_skb_ptr;
773
774 /* Received Packet CRC check need or not */
775 if ((db->dm910x_chk_mode & 1) && (cal_CRC(skb->tail, rxlen) != (*(unsigned long *) (skb->tail + rxlen)))) {
776 /* Found a error received packet */
777 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
778 db->dm910x_chk_mode = 3;
779 } else {
780 /* A good packet coming, send to upper layer */
781 skb->dev = dev;
782 skb_put(skb, rxlen);
783 skb->protocol = eth_type_trans(skb, dev);
784 netif_rx(skb); /* Send to upper layer */
785 /* skb->ip_summed = CHECKSUM_UNNECESSARY; */
786 dev->last_rx = jiffies;
787 db->stats.rx_packets++;
788 }
789 } else {
790 DMFE_DBUG(0, "Reused SK buffer, rdes0", rxptr->rdes0);
791 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
792 }
793 }
794
795 rxptr = (struct rx_desc *) rxptr->next_rx_desc;
796 }
797
798 db->rx_ready_ptr = rxptr;
799 }
800
801 /*
802 * Get statistics from driver.
803 */
804
805 static struct enet_statistics *dmfe_get_stats(struct net_device *dev)
806 {
807 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
808
809 DMFE_DBUG(0, "dmfe_get_stats", 0);
810 return &db->stats;
811 }
812
813 /*
814 * Set DM910X multicast address
815 */
816
817 static void dmfe_set_filter_mode(struct net_device *dev)
818 {
819 struct dmfe_board_info *db = dev->priv;
820
821 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
822
823 if (dev->flags & IFF_PROMISC) {
824 DMFE_DBUG(0, "Enable PROM Mode", 0);
825 db->cr6_data |= CR6_PM | CR6_PBF;
826 update_cr6(db->cr6_data, db->ioaddr);
827 return;
828 }
829 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
830 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
831 db->cr6_data &= ~(CR6_PM | CR6_PBF);
832 db->cr6_data |= CR6_PAM;
833 return;
834 }
835 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
836 send_filter_frame(dev, dev->mc_count);
837 }
838
839 /*
840 * Process the upper socket ioctl command
841 */
842
843 static int dmfe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
844 {
845 DMFE_DBUG(0, "dmfe_do_ioctl()", 0);
846 return 0;
847 }
848
849 /*
850 * A periodic timer routine
851 * Dynamic media sense, allocated Rx buffer...
852 */
853
854 static void dmfe_timer(unsigned long data)
855 {
856 u32 tmp_cr8;
857 unsigned char tmp_cr12;
858 struct net_device *dev = (struct net_device *) data;
859 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
860
861 DMFE_DBUG(0, "dmfe_timer()", 0);
862
863 /* Do reset now */
864 if (db->in_reset_state)
865 return;
866
867 /* Operating Mode Check */
868 if ((db->dm910x_chk_mode & 0x1) && (db->stats.rx_packets > MAX_CHECK_PACKET)) {
869 db->dm910x_chk_mode = 0x4;
870 }
871 /* Dynamic reset DM910X : system error or transmit time-out */
872 tmp_cr8 = inl(db->ioaddr + DCR8);
873 if ((db->interval_rx_cnt == 0) && (tmp_cr8)) {
874 db->wait_reset = 1;
875 /* printk("CR8 %x, Interval Rx %x\n", tmp_cr8, db->interval_rx_cnt); */
876 }
877 /* Receiving Traffic check */
878 if (db->interval_rx_cnt > RX_MAX_TRAFFIC)
879 db->cr7_data = 0x1a28d;
880 else
881 db->cr7_data = 0x1a2cd;
882 outl(db->cr7_data, db->ioaddr + DCR7);
883
884 db->interval_rx_cnt = 0;
885
886 if (db->wait_reset | (db->tx_packet_cnt &&
887 ((jiffies - dev->trans_start) > DMFE_TX_TIMEOUT)) | (db->rx_error_cnt > 3)) {
888 /* printk("wait_reset %x, tx cnt %x, rx err %x, time %x\n", db->wait_reset, db->tx_packet_cnt, db->rx_error_cnt, jiffies-dev->trans_start); */
889 DMFE_DBUG(0, "Warn!! Warn!! Tx/Rx moniotr step1", db->tx_packet_cnt);
890 dmfe_dynamic_reset(dev);
891 db->timer.expires = DMFE_TIMER_WUT;
892 add_timer(&db->timer);
893 return;
894 }
895 db->rx_error_cnt = 0; /* Clear previous counter */
896
897 /* Link status check, Dynamic media type change */
898 tmp_cr12 = inb(db->ioaddr + DCR12);
899 if (db->chip_revesion == 0x02000030) {
900 if (tmp_cr12 & 2)
901 tmp_cr12 = 0x0; /* Link failed */
902 else
903 tmp_cr12 = 0x3; /* Link OK */
904 }
905 if (!(tmp_cr12 & 0x3) && !db->link_failed) {
906 /* Link Failed */
907 DMFE_DBUG(0, "Link Failed", tmp_cr12);
908 db->link_failed = 1;
909 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000); /* reset Phy controller */
910 } else if ((tmp_cr12 & 0x3) && db->link_failed) {
911 DMFE_DBUG(0, "Link link OK", tmp_cr12);
912 db->link_failed = 0;
913 if (db->media_mode & DMFE_AUTO)
914 dmfe_sense_speed(db);
915 dmfe_process_mode(db);
916 update_cr6(db->cr6_data, db->ioaddr);
917 /* SHOW_MEDIA_TYPE(db->op_mode); */
918 }
919 /* reallocated rx descriptor buffer */
920 if (db->rx_avail_cnt < RX_DESC_CNT)
921 allocated_rx_buffer(db);
922
923 /* Timer active again */
924 db->timer.expires = DMFE_TIMER_WUT;
925 add_timer(&db->timer);
926 }
927
928 /*
929 * Dynamic reset the DM910X board
930 * Stop DM910X board
931 * Free Tx/Rx allocated memory
932 * Reset DM910X board
933 * Re-initilize DM910X board
934 */
935
936 static void dmfe_dynamic_reset(struct net_device *dev)
937 {
938 struct dmfe_board_info *db = dev->priv;
939
940 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
941
942 /* Enter dynamic reset route */
943 db->in_reset_state = 1;
944
945 /* Disable upper layer interface */
946 dev->tbusy = 1; /* transmit packet disable */
947 dev->start = 0; /* interface not ready */
948
949 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
950 update_cr6(db->cr6_data, dev->base_addr);
951
952 /* Free Rx Allocate buffer */
953 dmfe_free_rxbuffer(db);
954
955 /* system variable init */
956 db->tx_packet_cnt = 0;
957 db->rx_avail_cnt = 0;
958 db->link_failed = 0;
959 db->wait_reset = 0;
960 db->rx_error_cnt = 0;
961
962 /* Re-initilize DM910X board */
963 dmfe_init_dm910x(dev);
964
965 /* Restart upper layer interface */
966 dev->tbusy = 0; /* Can transmit packet */
967 dev->start = 1; /* interface ready */
968
969 /* Leave dynamic reser route */
970 db->in_reset_state = 0;
971 }
972
973 /*
974 * Free all allocated rx buffer
975 */
976
977 static void dmfe_free_rxbuffer(struct dmfe_board_info *db)
978 {
979 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
980
981 /* free allocated rx buffer */
982 while (db->rx_avail_cnt) {
983 dev_kfree_skb((void *) (db->rx_ready_ptr->rx_skb_ptr));
984 db->rx_ready_ptr = (struct rx_desc *) db->rx_ready_ptr->next_rx_desc;
985 db->rx_avail_cnt--;
986 }
987 }
988
989 /*
990 * Reused the SK buffer
991 */
992
993 static void dmfe_reused_skb(struct dmfe_board_info *db, struct sk_buff *skb)
994 {
995 struct rx_desc *rxptr = db->rx_insert_ptr;
996
997 if (!(rxptr->rdes0 & 0x80000000)) {
998 rxptr->rx_skb_ptr = (u32) skb;
999 rxptr->rdes2 = virt_to_bus(skb->tail);
1000 rxptr->rdes0 = 0x80000000;
1001 db->rx_avail_cnt++;
1002 db->rx_insert_ptr = (struct rx_desc *) rxptr->next_rx_desc;
1003 } else
1004 DMFE_DBUG(0, "SK Buffer reused method error", db->rx_avail_cnt);
1005 }
1006
1007 /*
1008 * Initialize transmit/Receive descriptor
1009 * Using Chain structure, and allocated Tx/Rx buffer
1010 */
1011
1012 static void dmfe_descriptor_init(struct dmfe_board_info *db, u32 ioaddr)
1013 {
1014 struct tx_desc *tmp_tx;
1015 struct rx_desc *tmp_rx;
1016 unsigned char *tmp_buf;
1017 int i;
1018
1019 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1020
1021 /* tx descriptor start pointer */
1022 db->tx_insert_ptr = db->first_tx_desc;
1023 db->tx_remove_ptr = db->first_tx_desc;
1024 outl(virt_to_bus(db->first_tx_desc), ioaddr + DCR4); /* Init CR4 */
1025
1026 /* rx descriptor start pointer */
1027 db->first_rx_desc = (struct rx_desc *)
1028 ((u32) db->first_tx_desc + sizeof(struct rx_desc) * TX_DESC_CNT);
1029 db->rx_insert_ptr = db->first_rx_desc;
1030 db->rx_ready_ptr = db->first_rx_desc;
1031 outl(virt_to_bus(db->first_rx_desc), ioaddr + DCR3); /* Init CR3 */
1032
1033 /* Init Transmit chain */
1034 tmp_buf = db->buf_pool_start;
1035 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1036 tmp_tx->tx_buf_ptr = (u32) tmp_buf;
1037 tmp_tx->tdes0 = 0;
1038 tmp_tx->tdes1 = 0x81000000; /* IC, chain */
1039 tmp_tx->tdes2 = (u32) virt_to_bus(tmp_buf);
1040 tmp_tx->tdes3 = (u32) virt_to_bus(tmp_tx) + sizeof(struct tx_desc);
1041 tmp_tx->next_tx_desc = (u32) ((u32) tmp_tx + sizeof(struct tx_desc));
1042 tmp_buf = (unsigned char *) ((u32) tmp_buf + TX_BUF_ALLOC);
1043 }
1044 (--tmp_tx)->tdes3 = (u32) virt_to_bus(db->first_tx_desc);
1045 tmp_tx->next_tx_desc = (u32) db->first_tx_desc;
1046
1047 /* Init Receive descriptor chain */
1048 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1049 tmp_rx->rdes0 = 0;
1050 tmp_rx->rdes1 = 0x01000600;
1051 tmp_rx->rdes3 = (u32) virt_to_bus(tmp_rx) + sizeof(struct rx_desc);
1052 tmp_rx->next_rx_desc = (u32) ((u32) tmp_rx + sizeof(struct rx_desc));
1053 }
1054 (--tmp_rx)->rdes3 = (u32) virt_to_bus(db->first_rx_desc);
1055 tmp_rx->next_rx_desc = (u32) db->first_rx_desc;
1056
1057 /* pre-allocated Rx buffer */
1058 allocated_rx_buffer(db);
1059 }
1060
1061 /*
1062 * Update CR6 vaule
1063 * Firstly stop DM910X , then written value and start
1064 */
1065
1066 static void update_cr6(u32 cr6_data, u32 ioaddr)
1067 {
1068 u32 cr6_tmp;
1069
1070 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1071 outl(cr6_tmp, ioaddr + DCR6);
1072 DELAY_5US;
1073 outl(cr6_data, ioaddr + DCR6);
1074 cr6_tmp = inl(ioaddr + DCR6);
1075 /* printk("CR6 update %x ", cr6_tmp); */
1076 }
1077
1078 /*
1079 * Send a setup frame
1080 * This setup frame initilize DM910X addres filter mode
1081 */
1082
1083 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1084 {
1085 struct dmfe_board_info *db = dev->priv;
1086 struct dev_mc_list *mcptr;
1087 struct tx_desc *txptr;
1088 u16 *addrptr;
1089 u32 *suptr;
1090 int i;
1091
1092 DMFE_DBUG(0, "send_filetr_frame()", 0);
1093
1094 txptr = db->tx_insert_ptr;
1095 suptr = (u32 *) txptr->tx_buf_ptr;
1096
1097 /* broadcast address */
1098 *suptr++ = 0xffff;
1099 *suptr++ = 0xffff;
1100 *suptr++ = 0xffff;
1101
1102 /* Node address */
1103 addrptr = (u16 *) dev->dev_addr;
1104 *suptr++ = addrptr[0];
1105 *suptr++ = addrptr[1];
1106 *suptr++ = addrptr[2];
1107
1108 /* fit the multicast address */
1109 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1110 addrptr = (u16 *) mcptr->dmi_addr;
1111 *suptr++ = addrptr[0];
1112 *suptr++ = addrptr[1];
1113 *suptr++ = addrptr[2];
1114 }
1115
1116 for (; i < 14; i++) {
1117 *suptr++ = 0xffff;
1118 *suptr++ = 0xffff;
1119 *suptr++ = 0xffff;
1120 }
1121
1122 /* prepare the setup frame */
1123 db->tx_packet_cnt++;
1124 dev->tbusy = 1;
1125 txptr->tdes1 = 0x890000c0;
1126 txptr->tdes0 = 0x80000000;
1127 db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
1128
1129 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1130 outl(0x1, dev->base_addr + DCR1);
1131 update_cr6(db->cr6_data, dev->base_addr);
1132 dev->trans_start = jiffies;
1133
1134 }
1135
1136 /*
1137 * Allocate rx buffer,
1138 * Allocate as many Rx buffers as possible.
1139 */
1140 static void allocated_rx_buffer(struct dmfe_board_info *db)
1141 {
1142 struct rx_desc *rxptr;
1143 struct sk_buff *skb;
1144
1145 rxptr = db->rx_insert_ptr;
1146
1147 while (db->rx_avail_cnt < RX_DESC_CNT) {
1148 if ((skb = alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC)) == NULL)
1149 break;
1150 rxptr->rx_skb_ptr = (u32) skb;
1151 rxptr->rdes2 = virt_to_bus(skb->tail);
1152 rxptr->rdes0 = 0x80000000;
1153 rxptr = (struct rx_desc *) rxptr->next_rx_desc;
1154 db->rx_avail_cnt++;
1155 }
1156
1157 db->rx_insert_ptr = rxptr;
1158 }
1159
1160 /*
1161 * Read one word data from the serial ROM
1162 */
1163
1164 static u16 read_srom_word(long ioaddr, int offset)
1165 {
1166 int i;
1167 u16 srom_data = 0;
1168 long cr9_ioaddr = ioaddr + DCR9;
1169
1170 outl(CR9_SROM_READ, cr9_ioaddr);
1171 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1172
1173 /* Send the Read Command 110b */
1174 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1175 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1176 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1177
1178 /* Send the offset */
1179 for (i = 5; i >= 0; i--) {
1180 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1181 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1182 }
1183
1184 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1185
1186 for (i = 16; i > 0; i--) {
1187 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1188 DELAY_5US;
1189 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1190 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1191 DELAY_5US;
1192 }
1193
1194 outl(CR9_SROM_READ, cr9_ioaddr);
1195 return srom_data;
1196 }
1197
1198 /*
1199 * Parser Control media block to get Phy address
1200 */
1201
1202 static void parser_ctrl_info(struct dmfe_board_info *db)
1203 {
1204 int i;
1205 char *sdata = db->srom;
1206 unsigned char count;
1207
1208 /* point to info leaf0 */
1209 count = *(sdata + 33);
1210
1211 /* Point to First media block */
1212 sdata += 34;
1213 for (i = 0; i < count; i++) {
1214 if (*(sdata + 1) == 1) {
1215 db->phy_addr = *(sdata + 2);
1216 break;
1217 }
1218 sdata += ((unsigned char) *(sdata) & 0x7f) + 1;
1219 }
1220
1221 if (i >= count) {
1222 printk("Can't found Control Block\n");
1223 db->phy_addr = 1;
1224 }
1225 }
1226
1227 /*
1228 * Auto sense the media mode
1229 */
1230
1231 static void dmfe_sense_speed(struct dmfe_board_info *db)
1232 {
1233 int i;
1234 u16 phy_mode;
1235
1236 for (i = 1000; i; i--) {
1237 DELAY_5US;
1238 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1);
1239 if ((phy_mode & 0x24) == 0x24)
1240 break;
1241 }
1242
1243 if (i) {
1244 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17) & 0xf000;
1245 /* printk("Phy_mode %x ",phy_mode); */
1246 switch (phy_mode) {
1247 case 0x1000:
1248 db->op_mode = DMFE_10MHF;
1249 break;
1250 case 0x2000:
1251 db->op_mode = DMFE_10MFD;
1252 break;
1253 case 0x4000:
1254 db->op_mode = DMFE_100MHF;
1255 break;
1256 case 0x8000:
1257 db->op_mode = DMFE_100MFD;
1258 break;
1259 default:
1260 db->op_mode = DMFE_100MHF;
1261 DMFE_DBUG(1, "Media Type error, phy reg17", phy_mode);
1262 break;
1263 }
1264 } else {
1265 db->op_mode = DMFE_100MHF;
1266 DMFE_DBUG(0, "Link Failed :", phy_mode);
1267 }
1268 }
1269
1270 /*
1271 * Process op-mode
1272 * AUTO mode : PHY controller in Auto-negotiation Mode
1273 * Force mode: PHY controller in force mode with HUB
1274 * N-way force capability with SWITCH
1275 */
1276
1277 static void dmfe_process_mode(struct dmfe_board_info *db)
1278 {
1279 u16 phy_reg;
1280
1281 /* Full Duplex Mode Check */
1282 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1283 if (db->op_mode & 0x4)
1284 db->cr6_data |= CR6_FDM;
1285
1286 if (!(db->media_mode & DMFE_AUTO)) { /* Force Mode Check */
1287 /* User force the media type */
1288 phy_reg = phy_read(db->ioaddr, db->phy_addr, 5);
1289 /* printk("Nway phy_reg5 %x ",phy_reg); */
1290 if (phy_reg & 0x1) {
1291 /* parter own the N-Way capability */
1292 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4) & ~0x1e0;
1293 switch (db->op_mode) {
1294 case DMFE_10MHF:
1295 phy_reg |= 0x20;
1296 break;
1297 case DMFE_10MFD:
1298 phy_reg |= 0x40;
1299 break;
1300 case DMFE_100MHF:
1301 phy_reg |= 0x80;
1302 break;
1303 case DMFE_100MFD:
1304 phy_reg |= 0x100;
1305 break;
1306 }
1307 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg);
1308 } else {
1309 /* parter without the N-Way capability */
1310 switch (db->op_mode) {
1311 case DMFE_10MHF:
1312 phy_reg = 0x0;
1313 break;
1314 case DMFE_10MFD:
1315 phy_reg = 0x100;
1316 break;
1317 case DMFE_100MHF:
1318 phy_reg = 0x2000;
1319 break;
1320 case DMFE_100MFD:
1321 phy_reg = 0x2100;
1322 break;
1323 }
1324 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg);
1325 }
1326 }
1327 }
1328
1329 /*
1330 * Write a word to Phy register
1331 */
1332
1333 static void phy_write(u32 iobase, u8 phy_addr, u8 offset, u16 phy_data)
1334 {
1335 u16 i;
1336 u32 ioaddr = iobase + DCR9;
1337
1338 /* Send 33 synchronization clock to Phy controller */
1339 for (i = 0; i < 35; i++)
1340 phy_write_1bit(ioaddr, PHY_DATA_1);
1341
1342 /* Send start command(01) to Phy */
1343 phy_write_1bit(ioaddr, PHY_DATA_0);
1344 phy_write_1bit(ioaddr, PHY_DATA_1);
1345
1346 /* Send write command(01) to Phy */
1347 phy_write_1bit(ioaddr, PHY_DATA_0);
1348 phy_write_1bit(ioaddr, PHY_DATA_1);
1349
1350 /* Send Phy addres */
1351 for (i = 0x10; i > 0; i = i >> 1)
1352 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1353
1354 /* Send register addres */
1355 for (i = 0x10; i > 0; i = i >> 1)
1356 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1357
1358 /* written trasnition */
1359 phy_write_1bit(ioaddr, PHY_DATA_1);
1360 phy_write_1bit(ioaddr, PHY_DATA_0);
1361
1362 /* Write a word data to PHY controller */
1363 for (i = 0x8000; i > 0; i >>= 1)
1364 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1365 }
1366
1367 /*
1368 * Read a word data from phy register
1369 */
1370
1371 static u16 phy_read(u32 iobase, u8 phy_addr, u8 offset)
1372 {
1373 int i;
1374 u16 phy_data;
1375 u32 ioaddr = iobase + DCR9;
1376
1377 /* Send 33 synchronization clock to Phy controller */
1378 for (i = 0; i < 35; i++)
1379 phy_write_1bit(ioaddr, PHY_DATA_1);
1380
1381 /* Send start command(01) to Phy */
1382 phy_write_1bit(ioaddr, PHY_DATA_0);
1383 phy_write_1bit(ioaddr, PHY_DATA_1);
1384
1385 /* Send read command(10) to Phy */
1386 phy_write_1bit(ioaddr, PHY_DATA_1);
1387 phy_write_1bit(ioaddr, PHY_DATA_0);
1388
1389 /* Send Phy addres */
1390 for (i = 0x10; i > 0; i = i >> 1)
1391 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1392
1393 /* Send register addres */
1394 for (i = 0x10; i > 0; i = i >> 1)
1395 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1396
1397 /* Skip transition state */
1398 phy_read_1bit(ioaddr);
1399
1400 /* read 16bit data */
1401 for (phy_data = 0, i = 0; i < 16; i++) {
1402 phy_data <<= 1;
1403 phy_data |= phy_read_1bit(ioaddr);
1404 }
1405
1406 return phy_data;
1407 }
1408
1409 /*
1410 * Write one bit data to Phy Controller
1411 */
1412
1413 static void phy_write_1bit(u32 ioaddr, u32 phy_data)
1414 {
1415 outl(phy_data, ioaddr); /* MII Clock Low */
1416 DELAY_1US;
1417 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1418 DELAY_1US;
1419 outl(phy_data, ioaddr); /* MII Clock Low */
1420 DELAY_1US;
1421 }
1422
1423 /*
1424 * Read one bit phy data from PHY controller
1425 */
1426
1427 static u16 phy_read_1bit(u32 ioaddr)
1428 {
1429 u16 phy_data;
1430
1431 outl(0x50000, ioaddr);
1432 DELAY_1US;
1433 phy_data = (inl(ioaddr) >> 19) & 0x1;
1434 outl(0x40000, ioaddr);
1435 DELAY_1US;
1436
1437 return phy_data;
1438 }
1439
1440 /*
1441 * Calculate the CRC valude of the Rx packet
1442 */
1443
1444 static unsigned long cal_CRC(unsigned char *Data, unsigned int Len)
1445 {
1446 unsigned long Crc = 0xffffffff;
1447
1448 while (Len--) {
1449 Crc = CrcTable[(Crc ^ *Data++) & 0xFF] ^ (Crc >> 8);
1450 }
1451
1452 return ~Crc;
1453
1454 }
1455
1456 #ifdef MODULE
1457
1458 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1459 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1460 MODULE_PARM(debug, "i");
1461 MODULE_PARM(mode, "i");
1462 MODULE_PARM(cr6set, "i");
1463 MODULE_PARM(chkmode, "i");
1464
1465 /* Description:
1466 * when user used insmod to add module, system invoked init_module()
1467 * to initilize and register.
1468 */
1469
1470 int init_module(void)
1471 {
1472 DMFE_DBUG(0, "init_module() ", debug);
1473
1474 if (debug)
1475 dmfe_debug = debug; /* set debug flag */
1476 if (cr6set)
1477 dmfe_cr6_user_set = cr6set;
1478
1479 switch (mode) {
1480 case 0:
1481 case 1:
1482 case 4:
1483 case 5:
1484 dmfe_media_mode = mode;
1485 break;
1486 default:
1487 dmfe_media_mode = 8;
1488 break;
1489 }
1490
1491 return dmfe_reg_board(0); /* search board and register */
1492 }
1493
1494 /*
1495 * Description:
1496 * when user used rmmod to delete module, system invoked clean_module()
1497 * to un-register device.
1498 */
1499
1500 void cleanup_module(void)
1501 {
1502 struct net_device *next_dev;
1503
1504 DMFE_DBUG(0, "clean_module()", 0);
1505
1506 while (dmfe_root_dev) {
1507 next_dev = ((struct dmfe_board_info *) dmfe_root_dev->priv)->next_dev;
1508 unregister_netdev(dmfe_root_dev);
1509 release_region(dmfe_root_dev->base_addr, DM9102_IO_SIZE);
1510 kfree(dmfe_root_dev->priv); /* free board information */
1511 kfree(dmfe_root_dev); /* free device structure */
1512 dmfe_root_dev = next_dev;
1513 }
1514 DMFE_DBUG(0, "clean_module() exit", 0);
1515 }
1516
1517 #endif /* MODULE */