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[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / net / epic100.c
blob2ff81fba10077fdc8794a2c8c6464e58d086784b
1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-1998 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU Public License, incorporated herein by reference.
7 All other rights reserved.
8
9 This driver is for the SMC83c170/175 "EPIC" series, as used on the
10 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
11
12 The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O
13 USRA Center of Excellence in Space Data and Information Sciences
14 Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771
15
16 Information and updates available at
17 http://cesdis.gsfc.nasa.gov/linux/drivers/epic100.html
18 */
19
20 static const char *version =
21 "epic100.c:v1.04 8/23/98 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/epic100.html\n";
22
23 /* A few user-configurable values. */
24
25 /* Keep the ring sizes a power of two for efficiency.
26 Making the Tx ring too large decreases the effectiveness of channel
27 bonding and packet priority.
28 There are no ill effects from too-large receive rings. */
29 #define TX_RING_SIZE 16
30 #define RX_RING_SIZE 32
31
32 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
33 Setting to > 1518 effectively disables this feature. */
34 static int rx_copybreak = 200;
35
36 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37 static int max_interrupt_work = 10;
38
39 /* Operational parameters that usually are not changed. */
40 /* Time in jiffies before concluding the transmitter is hung. */
41 #define TX_TIMEOUT ((2000*HZ)/1000)
42
43 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
44
45 /* Bytes transferred to chip before transmission starts. */
46 #define TX_FIFO_THRESH 256 /* Rounded down to 4 byte units. */
47 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
48
49 #include <linux/version.h> /* Evil, but neccessary */
50 #ifdef MODULE
51 #ifdef MODVERSIONS
52 #include <linux/modversions.h>
53 #endif
54 #include <linux/module.h>
55 #else
56 #define MOD_INC_USE_COUNT
57 #define MOD_DEC_USE_COUNT
58 #endif
59
60 #include <linux/kernel.h>
61 #include <linux/string.h>
62 #include <linux/timer.h>
63 #include <linux/errno.h>
64 #include <linux/ioport.h>
65 #include <linux/malloc.h>
66 #include <linux/interrupt.h>
67 #include <linux/pci.h>
68 #if LINUX_VERSION_CODE >= 0x20155
69 #define PCI_SUPPORT_VER2
70 #else
71 #include <linux/bios32.h>
72 #endif
73 #include <linux/delay.h>
74
75 #include <asm/processor.h> /* Processor type for cache alignment. */
76 #include <asm/bitops.h>
77 #include <asm/io.h>
78
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82
83 /* Kernel compatibility defines, common to David Hind's PCMCIA package.
84 This is only in the support-all-kernels source code. */
85
86 #if ! defined (LINUX_VERSION_CODE) || LINUX_VERSION_CODE < 0x20000
87 #warning This driver version is only for kernel versions 2.0.0 and later.
88 #endif
89
90 #define RUN_AT(x) (jiffies + (x))
91
92 #if defined(MODULE) && (LINUX_VERSION_CODE >= 0x20115)
93 MODULE_AUTHOR("Donald Becker <becker@cesdis.gsfc.nasa.gov>");
94 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
95 MODULE_PARM(debug, "i");
96 MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
97 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
98 MODULE_PARM(rx_copybreak, "i");
99 MODULE_PARM(max_interrupt_work, "i");
100 #endif
101 #if LINUX_VERSION_CODE < 0x20123
102 #define test_and_set_bit(val, addr) set_bit(val, addr)
103 #endif
104 #if LINUX_VERSION_CODE <= 0x20139
105 #define net_device_stats enet_statistics
106 #define NETSTATS_VER2
107 #endif
108 #if LINUX_VERSION_CODE < 0x20159
109 #define DEV_FREE_SKB(skb) dev_kfree_skb(skb, FREE_WRITE);
110 #else /* Grrr, unneeded incompatible change. */
111 #define DEV_FREE_SKB(skb) dev_kfree_skb(skb);
112 #endif
113
114 /* The I/O extent. */
115 #define EPIC_TOTAL_SIZE 0x100
116
117 #define epic_debug debug
118 static int epic_debug = 1;
119
120 /*
121 Theory of Operation
122
123 I. Board Compatibility
124
125 This device driver is designed for the SMC "EPIC/100", the SMC
126 single-chip Ethernet controllers for PCI. This chip is used on
127 the SMC EtherPower II boards.
128
129 II. Board-specific settings
130
131 PCI bus devices are configured by the system at boot time, so no jumpers
132 need to be set on the board. The system BIOS will assign the
133 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
134 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
135 interrupt lines.
136
137 III. Driver operation
138
139 IIIa. Ring buffers
140
141 IVb. References
142
143 http://www.smsc.com/main/datasheets/83c171.pdf
144 http://www.smsc.com/main/datasheets/83c175.pdf
145 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
146 http://www.national.com/pf/DP/DP83840A.html
147
148 IVc. Errata
149
150 */
151
152 /* The rest of these values should never change. */
153
154 static struct net_device *epic_probe1(int pci_bus, int pci_devfn,
155 struct net_device *dev, long ioaddr, int irq,
156 int chip_id, int card_idx);
157
158 enum pci_flags_bit {
159 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
160 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
161 };
162
163 struct chip_info {
164 const char *name;
165 u16 vendor_id, device_id, device_id_mask, pci_flags;
166 int io_size, min_latency;
167 struct net_device *(*probe1)(int pci_bus, int pci_devfn, struct net_device *dev,
168 long ioaddr, int irq, int chip_idx, int fnd_cnt);
169 } chip_tbl[] = {
170 {"SMSC EPIC/100 83c170", 0x10B8, 0x0005, 0x7fff,
171 PCI_USES_IO|PCI_USES_MASTER|PCI_ADDR0, EPIC_TOTAL_SIZE, 32, epic_probe1},
172 {"SMSC EPIC/C 83c175", 0x10B8, 0x0006, 0x7fff,
173 PCI_USES_IO|PCI_USES_MASTER|PCI_ADDR0, EPIC_TOTAL_SIZE, 32, epic_probe1},
174 {0,},
175 };
176
177 /* Offsets to registers, using the (ugh) SMC names. */
178 enum epic_registers {
179 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
180 PCIBurstCnt=0x18,
181 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
182 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
183 LAN0=64, /* MAC address. */
184 MC0=80, /* Multicast filter table. */
185 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
186 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
187 };
188
189 /* Interrupt register bits, using my own meaningful names. */
190 enum IntrStatus {
191 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
192 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
193 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
194 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
195 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
196 };
197
198 /* The EPIC100 Rx and Tx buffer descriptors. */
199
200 struct epic_tx_desc {
201 s16 status;
202 u16 txlength;
203 u32 bufaddr;
204 u16 buflength;
205 u16 control;
206 u32 next;
207 };
208
209 struct epic_rx_desc {
210 s16 status;
211 u16 rxlength;
212 u32 bufaddr;
213 u32 buflength;
214 u32 next;
215 };
216
217 struct epic_private {
218 char devname[8]; /* Used only for kernel debugging. */
219 const char *product_name;
220 struct net_device *next_module;
221
222 /* Tx and Rx rings here so that they remain paragraph aligned. */
223 struct epic_rx_desc rx_ring[RX_RING_SIZE];
224 struct epic_tx_desc tx_ring[TX_RING_SIZE];
225 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
226 struct sk_buff* tx_skbuff[TX_RING_SIZE];
227 /* The addresses of receive-in-place skbuffs. */
228 struct sk_buff* rx_skbuff[RX_RING_SIZE];
229
230 /* Ring pointers. */
231 unsigned int cur_rx, cur_tx; /* The next free ring entry */
232 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
233
234 u8 pci_bus, pci_dev_fn; /* PCI bus location. */
235 u16 chip_id;
236
237 struct net_device_stats stats;
238 struct timer_list timer; /* Media selection timer. */
239 unsigned char mc_filter[8];
240 signed char phys[4]; /* MII device addresses. */
241 unsigned int tx_full:1; /* The Tx queue is full. */
242 unsigned int full_duplex:1; /* Current duplex setting. */
243 unsigned int force_fd:1; /* Full-duplex operation requested. */
244 unsigned int default_port:4; /* Last dev->if_port value. */
245 unsigned int media2:4; /* Secondary monitored media port. */
246 unsigned int medialock:1; /* Don't sense media type. */
247 unsigned int mediasense:1; /* Media sensing in progress. */
248 int pad0, pad1; /* Used for 8-byte alignment */
249 };
250
251 /* Used to pass the full-duplex flag, etc. */
252 #define MAX_UNITS 8
253 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
254 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
255
256 static int epic_open(struct net_device *dev);
257 static int read_eeprom(long ioaddr, int location);
258 static int mdio_read(long ioaddr, int phy_id, int location);
259 static void mdio_write(long ioaddr, int phy_id, int location, int value);
260 static void epic_restart(struct net_device *dev);
261 static void epic_timer(unsigned long data);
262 static void epic_tx_timeout(struct net_device *dev);
263 static void epic_init_ring(struct net_device *dev);
264 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
265 static int epic_rx(struct net_device *dev);
266 static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
267 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
268 static int epic_close(struct net_device *dev);
269 static struct net_device_stats *epic_get_stats(struct net_device *dev);
270 static void set_rx_mode(struct net_device *dev);
271
272 \f
273 /* A list of all installed EPIC devices, for removing the driver module. */
274 static struct net_device *root_epic_dev = NULL;
275
276 #ifndef CARDBUS
277 int epic100_probe(struct net_device *dev)
278 {
279 int cards_found = 0;
280 int chip_idx, irq;
281 u16 pci_command, new_command;
282 unsigned char pci_bus, pci_device_fn;
283
284 #ifdef PCI_SUPPORT_VER2
285 struct pci_dev *pcidev = NULL;
286 while ((pcidev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pcidev))
287 != NULL) {
288 long pci_ioaddr = pcidev->resource[0].start;
289 int vendor = pcidev->vendor;
290 int device = pcidev->device;
291
292 for (chip_idx = 0; chip_tbl[chip_idx].vendor_id; chip_idx++)
293 if (vendor == chip_tbl[chip_idx].vendor_id
294 && (device & chip_tbl[chip_idx].device_id_mask) ==
295 chip_tbl[chip_idx].device_id)
296 break;
297 if (chip_tbl[chip_idx].vendor_id == 0 /* Compiled out! */
298 || check_region(pci_ioaddr, chip_tbl[chip_idx].io_size))
299 continue;
300 pci_bus = pcidev->bus->number;
301 pci_device_fn = pcidev->devfn;
302 irq = pcidev->irq;
303 #else
304 int pci_index;
305
306 if ( ! pcibios_present())
307 return -ENODEV;
308
309 for (pci_index = 0; pci_index < 0xff; pci_index++) {
310 u8 pci_irq_line;
311 u16 vendor, device;
312 u32 pci_ioaddr;
313
314 if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8,
315 pci_index, &pci_bus, &pci_device_fn)
316 != PCIBIOS_SUCCESSFUL)
317 break;
318 pcibios_read_config_word(pci_bus, pci_device_fn,
319 PCI_VENDOR_ID, &vendor);
320 pcibios_read_config_word(pci_bus, pci_device_fn,
321 PCI_DEVICE_ID, &device);
322
323 for (chip_idx = 0; chip_tbl[chip_idx].vendor_id; chip_idx++)
324 if (vendor == chip_tbl[chip_idx].vendor_id
325 && (device & chip_tbl[chip_idx].device_id_mask) ==
326 chip_tbl[chip_idx].device_id)
327 break;
328 if (chip_tbl[chip_idx].vendor_id == 0) /* Compiled out! */
329 continue;
330
331 pcibios_read_config_dword(pci_bus, pci_device_fn,
332 PCI_BASE_ADDRESS_0, &pci_ioaddr);
333 pcibios_read_config_byte(pci_bus, pci_device_fn,
334 PCI_INTERRUPT_LINE, &pci_irq_line);
335 /* Remove I/O space marker in bit 0. */
336 pci_ioaddr &= ~3;
337 irq = pci_irq_line;
338
339 if (check_region(pci_ioaddr, chip_tbl[chip_idx].io_size))
340 continue;
341 #endif
342
343 /* EPIC-specific code: Soft-reset the chip ere setting as master. */
344 outl(0x0001, pci_ioaddr + GENCTL);
345
346 /* Activate the card: fix for brain-damaged Win98 BIOSes. */
347 pcibios_read_config_word(pci_bus, pci_device_fn,
348 PCI_COMMAND, &pci_command);
349 new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
350 if (pci_command != new_command) {
351 printk(KERN_INFO " The PCI BIOS has not enabled Ethernet"
352 " device %4.4x-%4.4x."
353 " Updating PCI command %4.4x->%4.4x.\n",
354 vendor, device, pci_command, new_command);
355 pcibios_write_config_word(pci_bus, pci_device_fn,
356 PCI_COMMAND, new_command);
357 }
358
359 dev = chip_tbl[chip_idx].probe1(pci_bus, pci_device_fn, dev, pci_ioaddr,
360 irq, chip_idx, cards_found);
361
362 /* Check the latency timer. */
363 if (dev) {
364 u8 pci_latency;
365 pcibios_read_config_byte(pci_bus, pci_device_fn,
366 PCI_LATENCY_TIMER, &pci_latency);
367 if (pci_latency < chip_tbl[chip_idx].min_latency) {
368 printk(KERN_INFO " PCI latency timer (CFLT) value of %d is "
369 "unreasonably low, setting to %d.\n", pci_latency,
370 chip_tbl[chip_idx].min_latency);
371 pcibios_write_config_byte(pci_bus, pci_device_fn,
372 PCI_LATENCY_TIMER,
373 chip_tbl[chip_idx].min_latency);
374 }
375 dev = 0;
376 cards_found++;
377 }
378 }
379
380 return cards_found ? 0 : -ENODEV;
381 }
382 #endif /* not CARDBUS */
383
384 static struct net_device *epic_probe1(int pci_bus, int pci_devfn,
385 struct net_device *dev, long ioaddr, int irq,
386 int chip_idx, int card_idx)
387 {
388 struct epic_private *ep;
389 int i, option = 0, duplex = 0;
390
391 if (dev && dev->mem_start) {
392 option = dev->mem_start;
393 duplex = (dev->mem_start & 16) ? 1 : 0;
394 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
395 if (options[card_idx] >= 0)
396 option = options[card_idx];
397 if (full_duplex[card_idx] >= 0)
398 duplex = full_duplex[card_idx];
399 }
400
401 dev = init_etherdev(dev, 0);
402
403 dev->base_addr = ioaddr;
404 dev->irq = irq;
405 printk(KERN_INFO "%s: SMC EPIC/100 at %#lx, IRQ %d, ",
406 dev->name, ioaddr, dev->irq);
407
408 /* Bring the chip out of low-power mode. */
409 outl(0x4200, ioaddr + GENCTL);
410 /* Magic?! If we don't set this bit the MII interface won't work. */
411 outl(0x0008, ioaddr + TEST1);
412
413 /* Turn on the MII transceiver. */
414 outl(0x12, ioaddr + MIICfg);
415 if (chip_idx == 1)
416 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
417 outl(0x0200, ioaddr + GENCTL);
418
419 /* This could also be read from the EEPROM. */
420 for (i = 0; i < 3; i++)
421 ((u16 *)dev->dev_addr)[i] = inw(ioaddr + LAN0 + i*4);
422
423 for (i = 0; i < 5; i++)
424 printk("%2.2x:", dev->dev_addr[i]);
425 printk("%2.2x.\n", dev->dev_addr[i]);
426
427 if (epic_debug > 1) {
428 printk(KERN_DEBUG "%s: EEPROM contents\n", dev->name);
429 for (i = 0; i < 64; i++)
430 printk(" %4.4x%s", read_eeprom(ioaddr, i),
431 i % 16 == 15 ? "\n" : "");
432 }
433
434 /* We do a request_region() to register /proc/ioports info. */
435 request_region(ioaddr, EPIC_TOTAL_SIZE, dev->name);
436
437 /* The data structures must be quadword aligned. */
438 ep = kmalloc(sizeof(*ep), GFP_KERNEL | GFP_DMA);
439 memset(ep, 0, sizeof(*ep));
440 dev->priv = ep;
441
442 ep->next_module = root_epic_dev;
443 root_epic_dev = dev;
444
445 ep->pci_bus = pci_bus;
446 ep->pci_dev_fn = pci_devfn;
447 #if defined(PCI_SUPPORT_VER2)
448 ep->chip_id = pci_find_slot(pci_bus, pci_devfn)->device;
449 #else
450 ep->chip_id = chip_tbl[chip_idx].device_id;
451 #endif
452
453 /* Find the connected MII xcvrs.
454 Doing this in open() would allow detecting external xcvrs later, but
455 takes too much time. */
456 {
457 int phy, phy_idx;
458 for (phy = 1, phy_idx = 0; phy < 32 && phy_idx < sizeof(ep->phys);
459 phy++) {
460 int mii_status = mdio_read(ioaddr, phy, 1);
461 if (mii_status != 0xffff && mii_status != 0x0000) {
462 ep->phys[phy_idx++] = phy;
463 printk(KERN_INFO "%s: MII transceiver #%d control "
464 "%4.4x status %4.4x.\n"
465 KERN_INFO "%s: Autonegotiation advertising %4.4x "
466 "link partner %4.4x.\n",
467 dev->name, phy, mdio_read(ioaddr, phy, 0), mii_status,
468 dev->name, mdio_read(ioaddr, phy, 4),
469 mdio_read(ioaddr, phy, 5));
470 }
471 }
472 if (phy_idx == 0) {
473 printk(KERN_WARNING "%s: ***WARNING***: No MII transceiver found!\n",
474 dev->name);
475 /* Use the known PHY address of the EPII. */
476 ep->phys[0] = 3;
477 }
478 }
479
480 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
481 if (ep->chip_id == 6)
482 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
483 outl(0x0008, ioaddr + GENCTL);
484
485 /* The lower four bits are the media type. */
486 ep->force_fd = duplex;
487 ep->default_port = option;
488 if (ep->default_port)
489 ep->medialock = 1;
490
491 /* The Epic-specific entries in the device structure. */
492 dev->open = &epic_open;
493 dev->hard_start_xmit = &epic_start_xmit;
494 dev->stop = &epic_close;
495 dev->get_stats = &epic_get_stats;
496 dev->set_multicast_list = &set_rx_mode;
497 dev->do_ioctl = &mii_ioctl;
498
499 return dev;
500 }
501 \f
502 /* Serial EEPROM section. */
503
504 /* EEPROM_Ctrl bits. */
505 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
506 #define EE_CS 0x02 /* EEPROM chip select. */
507 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
508 #define EE_WRITE_0 0x01
509 #define EE_WRITE_1 0x09
510 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
511 #define EE_ENB (0x0001 | EE_CS)
512
513 /* Delay between EEPROM clock transitions.
514 No extra delay is needed with 33Mhz PCI, but 66Mhz is untested.
515 */
516
517 #ifdef _LINUX_DELAY_H
518 #define eeprom_delay(nanosec) udelay(1)
519 #else
520 #define eeprom_delay(nanosec) do { ; } while (0)
521 #endif
522
523 /* The EEPROM commands include the alway-set leading bit. */
524 #define EE_WRITE_CMD (5 << 6)
525 #define EE_READ64_CMD (6 << 6)
526 #define EE_READ256_CMD (6 << 8)
527 #define EE_ERASE_CMD (7 << 6)
528
529 static int read_eeprom(long ioaddr, int location)
530 {
531 int i;
532 int retval = 0;
533 long ee_addr = ioaddr + EECTL;
534 int read_cmd = location |
535 (inl(ee_addr) & 0x40) ? EE_READ64_CMD : EE_READ256_CMD;
536
537 outl(EE_ENB & ~EE_CS, ee_addr);
538 outl(EE_ENB, ee_addr);
539
540 /* Shift the read command bits out. */
541 for (i = 12; i >= 0; i--) {
542 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
543 outl(EE_ENB | dataval, ee_addr);
544 eeprom_delay(100);
545 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
546 eeprom_delay(150);
547 }
548 outl(EE_ENB, ee_addr);
549
550 for (i = 16; i > 0; i--) {
551 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
552 eeprom_delay(100);
553 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
554 outl(EE_ENB, ee_addr);
555 eeprom_delay(100);
556 }
557
558 /* Terminate the EEPROM access. */
559 outl(EE_ENB & ~EE_CS, ee_addr);
560 return retval;
561 }
562
563 #define MII_READOP 1
564 #define MII_WRITEOP 2
565 static int mdio_read(long ioaddr, int phy_id, int location)
566 {
567 int i;
568
569 outl((phy_id << 9) | (location << 4) | MII_READOP, ioaddr + MIICtrl);
570 /* Typical operation takes < 50 ticks. */
571 for (i = 4000; i > 0; i--)
572 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0)
573 return inw(ioaddr + MIIData);
574 return 0xffff;
575 }
576
577 static void mdio_write(long ioaddr, int phy_id, int location, int value)
578 {
579 int i;
580
581 outw(value, ioaddr + MIIData);
582 outl((phy_id << 9) | (location << 4) | MII_WRITEOP, ioaddr + MIICtrl);
583 for (i = 10000; i > 0; i--) {
584 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
585 break;
586 }
587 return;
588 }
589
590 \f
591 static int
592 epic_open(struct net_device *dev)
593 {
594 struct epic_private *ep = (struct epic_private *)dev->priv;
595 long ioaddr = dev->base_addr;
596 int i;
597 int mii_reg5;
598 ep->full_duplex = ep->force_fd;
599
600 /* Soft reset the chip. */
601 outl(0x4001, ioaddr + GENCTL);
602
603 if (request_irq(dev->irq, &epic_interrupt, SA_SHIRQ, "SMC EPIC/100", dev))
604 return -EAGAIN;
605
606 MOD_INC_USE_COUNT;
607
608 epic_init_ring(dev);
609
610 outl(0x4000, ioaddr + GENCTL);
611 /* This next magic! line by Ken Yamaguchi.. ?? */
612 outl(0x0008, ioaddr + TEST1);
613
614 /* Pull the chip out of low-power mode, enable interrupts, and set for
615 PCI read multiple. The MIIcfg setting and strange write order are
616 required by the details of which bits are reset and the transceiver
617 wiring on the Ositech CardBus card.
618 */
619 outl(0x12, ioaddr + MIICfg);
620 if (ep->chip_id == 6)
621 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
622
623 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
624 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
625 #else
626 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
627 #endif
628
629 for (i = 0; i < 3; i++)
630 outl(((u16*)dev->dev_addr)[i], ioaddr + LAN0 + i*4);
631
632 outl(TX_FIFO_THRESH, ioaddr + TxThresh);
633
634 mii_reg5 = mdio_read(ioaddr, ep->phys[0], 5);
635 if (mii_reg5 != 0xffff) {
636 if ((mii_reg5 & 0x0100) || (mii_reg5 & 0x01C0) == 0x0040)
637 ep->full_duplex = 1;
638 else if (! (mii_reg5 & 0x4000))
639 mdio_write(ioaddr, ep->phys[0], 0, 0x1200);
640 if (epic_debug > 1)
641 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
642 " register read of %4.4x.\n", dev->name,
643 ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
644 }
645
646 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
647 outl(virt_to_bus(ep->rx_ring), ioaddr + PRxCDAR);
648 outl(virt_to_bus(ep->tx_ring), ioaddr + PTxCDAR);
649
650 /* Start the chip's Rx process. */
651 set_rx_mode(dev);
652 outl(0x000A, ioaddr + COMMAND);
653
654 dev->tbusy = 0;
655 dev->interrupt = 0;
656 dev->start = 1;
657
658 /* Enable interrupts by setting the interrupt mask. */
659 outl((ep->chip_id == 6 ? PCIBusErr175 : PCIBusErr170)
660 | CntFull | TxUnderrun | TxDone
661 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
662 ioaddr + INTMASK);
663
664 if (epic_debug > 1)
665 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
666 "%s-duplex.\n",
667 dev->name, ioaddr, dev->irq, inl(ioaddr + GENCTL),
668 ep->full_duplex ? "full" : "half");
669
670 /* Set the timer to switch to check for link beat and perhaps switch
671 to an alternate media type. */
672 init_timer(&ep->timer);
673 ep->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
674 ep->timer.data = (unsigned long)dev;
675 ep->timer.function = &epic_timer; /* timer handler */
676 add_timer(&ep->timer);
677
678 return 0;
679 }
680
681 /* Reset the chip to recover from a PCI transaction error.
682 This may occur at interrupt time. */
683 static void epic_pause(struct net_device *dev)
684 {
685 long ioaddr = dev->base_addr;
686 struct epic_private *ep = (struct epic_private *)dev->priv;
687
688 /* Disable interrupts by clearing the interrupt mask. */
689 outl(0x00000000, ioaddr + INTMASK);
690 /* Stop the chip's Tx and Rx DMA processes. */
691 outw(0x0061, ioaddr + COMMAND);
692
693 /* Update the error counts. */
694 if (inw(ioaddr + COMMAND) != 0xffff) {
695 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
696 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
697 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
698 }
699
700 /* Remove the packets on the Rx queue. */
701 epic_rx(dev);
702 }
703
704 static void epic_restart(struct net_device *dev)
705 {
706 long ioaddr = dev->base_addr;
707 struct epic_private *ep = (struct epic_private *)dev->priv;
708 int i;
709
710 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
711 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
712 /* Soft reset the chip. */
713 outl(0x0001, ioaddr + GENCTL);
714
715 udelay(1);
716 /* Duplicate code from epic_open(). */
717 outl(0x0008, ioaddr + TEST1);
718
719 #if defined(__powerpc__) /* Big endian */
720 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
721 #else
722 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
723 #endif
724 outl(0x12, ioaddr + MIICfg);
725 if (ep->chip_id == 6)
726 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
727
728 for (i = 0; i < 3; i++)
729 outl(((u16*)dev->dev_addr)[i], ioaddr + LAN0 + i*4);
730
731 outl(TX_FIFO_THRESH, ioaddr + TxThresh);
732 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
733 outl(virt_to_bus(&ep->rx_ring[ep->cur_rx%RX_RING_SIZE]), ioaddr + PRxCDAR);
734 outl(virt_to_bus(&ep->tx_ring[ep->dirty_tx%TX_RING_SIZE]),
735 ioaddr + PTxCDAR);
736
737 /* Start the chip's Rx process. */
738 set_rx_mode(dev);
739 outl(0x000A, ioaddr + COMMAND);
740
741 /* Enable interrupts by setting the interrupt mask. */
742 outl((ep->chip_id == 6 ? PCIBusErr175 : PCIBusErr170)
743 | CntFull | TxUnderrun | TxDone
744 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
745 ioaddr + INTMASK);
746 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
747 " interrupt %4.4x.\n",
748 dev->name, inl(ioaddr + COMMAND), inl(ioaddr + GENCTL),
749 inl(ioaddr + INTSTAT));
750 return;
751 }
752
753 static void epic_timer(unsigned long data)
754 {
755 struct net_device *dev = (struct net_device *)data;
756 struct epic_private *ep = (struct epic_private *)dev->priv;
757 long ioaddr = dev->base_addr;
758 int next_tick = 0;
759 int mii_reg5 = mdio_read(ioaddr, ep->phys[0], 5);
760
761 if (epic_debug > 3) {
762 printk(KERN_DEBUG "%s: Media selection tick, Tx status %8.8x.\n",
763 dev->name, inl(ioaddr + TxSTAT));
764 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
765 "IntStatus %4.4x RxStatus %4.4x.\n",
766 dev->name, inl(ioaddr + INTMASK), inl(ioaddr + INTSTAT),
767 inl(ioaddr + RxSTAT));
768 }
769 if (! ep->force_fd && mii_reg5 != 0xffff) {
770 int duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
771 if (ep->full_duplex != duplex) {
772 ep->full_duplex = duplex;
773 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
774 " partner capability of %4.4x.\n", dev->name,
775 ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
776 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
777 }
778 next_tick = 60*HZ;
779 }
780
781 if (next_tick) {
782 ep->timer.expires = RUN_AT(next_tick);
783 add_timer(&ep->timer);
784 }
785 }
786
787 static void epic_tx_timeout(struct net_device *dev)
788 {
789 struct epic_private *ep = (struct epic_private *)dev->priv;
790 long ioaddr = dev->base_addr;
791
792 if (epic_debug > 0) {
793 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
794 "Tx status %4.4x.\n",
795 dev->name, inw(ioaddr + TxSTAT));
796 if (epic_debug > 1) {
797 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
798 dev->name, ep->dirty_tx, ep->cur_tx);
799 }
800 }
801 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
802 ep->stats.tx_fifo_errors++;
803 /* Restart the transmit process. */
804 outl(0x0080, ioaddr + COMMAND);
805 }
806
807 /* Perhaps stop and restart the chip's Tx processes . */
808 /* Trigger a transmit demand. */
809 outl(0x0004, dev->base_addr + COMMAND);
810
811 dev->trans_start = jiffies;
812 ep->stats.tx_errors++;
813 return;
814 }
815
816 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
817 static void
818 epic_init_ring(struct net_device *dev)
819 {
820 struct epic_private *ep = (struct epic_private *)dev->priv;
821 int i;
822
823 ep->tx_full = 0;
824 ep->cur_rx = ep->cur_tx = 0;
825 ep->dirty_rx = ep->dirty_tx = 0;
826
827 for (i = 0; i < RX_RING_SIZE; i++) {
828 ep->rx_ring[i].status = 0x8000; /* Owned by Epic chip */
829 ep->rx_ring[i].buflength = PKT_BUF_SZ;
830 {
831 /* Note the receive buffer must be longword aligned.
832 dev_alloc_skb() provides 16 byte alignment. But do *not*
833 use skb_reserve() to align the IP header! */
834 struct sk_buff *skb;
835 skb = dev_alloc_skb(PKT_BUF_SZ);
836 ep->rx_skbuff[i] = skb;
837 if (skb == NULL)
838 break; /* Bad news! */
839 skb->dev = dev; /* Mark as being used by this device. */
840 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
841 ep->rx_ring[i].bufaddr = virt_to_bus(skb->tail);
842 }
843 ep->rx_ring[i].next = virt_to_bus(&ep->rx_ring[i+1]);
844 }
845 /* Mark the last entry as wrapping the ring. */
846 ep->rx_ring[i-1].next = virt_to_bus(&ep->rx_ring[0]);
847
848 /* The Tx buffer descriptor is filled in as needed, but we
849 do need to clear the ownership bit. */
850 for (i = 0; i < TX_RING_SIZE; i++) {
851 ep->tx_skbuff[i] = 0;
852 ep->tx_ring[i].status = 0x0000;
853 ep->tx_ring[i].next = virt_to_bus(&ep->tx_ring[i+1]);
854 }
855 ep->tx_ring[i-1].next = virt_to_bus(&ep->tx_ring[0]);
856 }
857
858 static int
859 epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
860 {
861 struct epic_private *ep = (struct epic_private *)dev->priv;
862 int entry;
863 u32 flag;
864
865 /* Block a timer-based transmit from overlapping. This could better be
866 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
867 if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
868 if (jiffies - dev->trans_start < TX_TIMEOUT)
869 return 1;
870 epic_tx_timeout(dev);
871 return 1;
872 }
873
874 /* Caution: the write order is important here, set the base address
875 with the "ownership" bits last. */
876
877 /* Calculate the next Tx descriptor entry. */
878 entry = ep->cur_tx % TX_RING_SIZE;
879
880 ep->tx_skbuff[entry] = skb;
881 ep->tx_ring[entry].txlength = (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN);
882 ep->tx_ring[entry].bufaddr = virt_to_bus(skb->data);
883 ep->tx_ring[entry].buflength = skb->len;
884
885 /* tx_bytes counting -- Nolan Leake */
886 ep->stats.tx_bytes += ep->tx_ring[entry].txlength;
887
888 if (ep->cur_tx - ep->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
889 flag = 0x10; /* No interrupt */
890 clear_bit(0, (void*)&dev->tbusy);
891 } else if (ep->cur_tx - ep->dirty_tx == TX_RING_SIZE/2) {
892 flag = 0x14; /* Tx-done intr. */
893 clear_bit(0, (void*)&dev->tbusy);
894 } else if (ep->cur_tx - ep->dirty_tx < TX_RING_SIZE - 2) {
895 flag = 0x10; /* No Tx-done intr. */
896 clear_bit(0, (void*)&dev->tbusy);
897 } else {
898 /* Leave room for two additional entries. */
899 flag = 0x14; /* Tx-done intr. */
900 ep->tx_full = 1;
901 }
902
903 ep->tx_ring[entry].control = flag;
904 ep->tx_ring[entry].status = 0x8000; /* Pass ownership to the chip. */
905 ep->cur_tx++;
906 /* Trigger an immediate transmit demand. */
907 outl(0x0004, dev->base_addr + COMMAND);
908
909 dev->trans_start = jiffies;
910 if (epic_debug > 4)
911 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
912 "flag %2.2x Tx status %8.8x.\n",
913 dev->name, (int)skb->len, entry, flag,
914 inl(dev->base_addr + TxSTAT));
915
916 return 0;
917 }
918
919 /* The interrupt handler does all of the Rx thread work and cleans up
920 after the Tx thread. */
921 static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
922 {
923 struct net_device *dev = (struct net_device *)dev_instance;
924 struct epic_private *ep = (struct epic_private *)dev->priv;
925 long ioaddr = dev->base_addr;
926 int status, boguscnt = max_interrupt_work;
927
928 #if defined(__i386__)
929 /* A lock to prevent simultaneous entry bug on Intel SMP machines. */
930 if (test_and_set_bit(0, (void*)&dev->interrupt)) {
931 printk(KERN_ERR "%s: SMP simultaneous entry of an interrupt handler.\n",
932 dev->name);
933 dev->interrupt = 0; /* Avoid halting machine. */
934 return;
935 }
936 #else
937 if (dev->interrupt) {
938 printk(KERN_ERR "%s: Re-entering the interrupt handler.\n", dev->name);
939 return;
940 }
941 dev->interrupt = 1;
942 #endif
943
944 do {
945 status = inl(ioaddr + INTSTAT);
946 /* Acknowledge all of the current interrupt sources ASAP. */
947 outl(status & 0x00007fff, ioaddr + INTSTAT);
948
949 if (epic_debug > 4)
950 printk("%s: interrupt interrupt=%#8.8x new intstat=%#8.8x.\n",
951 dev->name, status, inl(ioaddr + INTSTAT));
952
953 if ((status & IntrSummary) == 0)
954 break;
955
956 if (status & (RxDone | RxStarted | RxEarlyWarn))
957 epic_rx(dev);
958
959 if (status & (TxEmpty | TxDone)) {
960 int dirty_tx;
961
962 for (dirty_tx = ep->dirty_tx; dirty_tx < ep->cur_tx; dirty_tx++) {
963 int entry = dirty_tx % TX_RING_SIZE;
964 int txstatus = ep->tx_ring[entry].status;
965
966 if (txstatus < 0)
967 break; /* It still hasn't been Txed */
968
969 if ( ! (txstatus & 0x0001)) {
970 /* There was an major error, log it. */
971 #ifndef final_version
972 if (epic_debug > 1)
973 printk("%s: Transmit error, Tx status %8.8x.\n",
974 dev->name, txstatus);
975 #endif
976 ep->stats.tx_errors++;
977 if (txstatus & 0x1050) ep->stats.tx_aborted_errors++;
978 if (txstatus & 0x0008) ep->stats.tx_carrier_errors++;
979 if (txstatus & 0x0040) ep->stats.tx_window_errors++;
980 if (txstatus & 0x0010) ep->stats.tx_fifo_errors++;
981 #ifdef ETHER_STATS
982 if (txstatus & 0x1000) ep->stats.collisions16++;
983 #endif
984 } else {
985 #ifdef ETHER_STATS
986 if ((txstatus & 0x0002) != 0) ep->stats.tx_deferred++;
987 #endif
988 ep->stats.collisions += (txstatus >> 8) & 15;
989 ep->stats.tx_packets++;
990 }
991
992 /* Free the original skb. */
993 DEV_FREE_SKB(ep->tx_skbuff[entry]);
994 ep->tx_skbuff[entry] = 0;
995 }
996
997 #ifndef final_version
998 if (ep->cur_tx - dirty_tx > TX_RING_SIZE) {
999 printk("%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1000 dev->name, dirty_tx, ep->cur_tx, ep->tx_full);
1001 dirty_tx += TX_RING_SIZE;
1002 }
1003 #endif
1004
1005 if (ep->tx_full && dev->tbusy
1006 && dirty_tx > ep->cur_tx - TX_RING_SIZE + 2) {
1007 /* The ring is no longer full, clear tbusy. */
1008 ep->tx_full = 0;
1009 clear_bit(0, (void*)&dev->tbusy);
1010 mark_bh(NET_BH);
1011 }
1012
1013 ep->dirty_tx = dirty_tx;
1014 }
1015
1016 /* Check uncommon events all at once. */
1017 if (status & (CntFull | TxUnderrun | RxOverflow |
1018 PCIBusErr170 | PCIBusErr175)) {
1019 if (status == 0xffffffff) /* Chip failed or removed (CardBus). */
1020 break;
1021 /* Always update the error counts to avoid overhead later. */
1022 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1023 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1024 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1025
1026 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1027 ep->stats.tx_fifo_errors++;
1028 outl(1536, ioaddr + TxThresh);
1029 /* Restart the transmit process. */
1030 outl(0x0080, ioaddr + COMMAND);
1031 }
1032 if (status & RxOverflow) { /* Missed a Rx frame. */
1033 ep->stats.rx_errors++;
1034 }
1035 if (status & PCIBusErr170) {
1036 printk(KERN_ERR "%s: PCI Bus Error! EPIC status %4.4x.\n",
1037 dev->name, status);
1038 epic_pause(dev);
1039 epic_restart(dev);
1040 }
1041 /* Clear all error sources. */
1042 outl(status & 0x7f18, ioaddr + INTSTAT);
1043 }
1044 if (--boguscnt < 0) {
1045 printk(KERN_ERR "%s: Too much work at interrupt, "
1046 "IntrStatus=0x%8.8x.\n",
1047 dev->name, status);
1048 /* Clear all interrupt sources. */
1049 outl(0x0001ffff, ioaddr + INTSTAT);
1050 break;
1051 }
1052 } while (1);
1053
1054 if (epic_debug > 3)
1055 printk(KERN_DEBUG "%s: exiting interrupt, intr_status=%#4.4x.\n",
1056 dev->name, inl(ioaddr + INTSTAT));
1057
1058 #if defined(__i386__)
1059 clear_bit(0, (void*)&dev->interrupt);
1060 #else
1061 dev->interrupt = 0;
1062 #endif
1063 return;
1064 }
1065
1066 static int epic_rx(struct net_device *dev)
1067 {
1068 struct epic_private *ep = (struct epic_private *)dev->priv;
1069 int entry = ep->cur_rx % RX_RING_SIZE;
1070 int work_done = 0;
1071
1072 if (epic_debug > 4)
1073 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1074 ep->rx_ring[entry].status);
1075 /* If we own the next entry, it's a new packet. Send it up. */
1076 while (ep->rx_ring[entry].status >= 0 && ep->rx_skbuff[entry]) {
1077 int status = ep->rx_ring[entry].status;
1078
1079 if (epic_debug > 4)
1080 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1081 if (status & 0x2006) {
1082 if (status & 0x2000) {
1083 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1084 "multiple buffers, status %4.4x!\n", dev->name, status);
1085 ep->stats.rx_length_errors++;
1086 } else if (status & 0x0006)
1087 /* Rx Frame errors are counted in hardware. */
1088 ep->stats.rx_errors++;
1089 } else {
1090 /* Malloc up new buffer, compatible with net-2e. */
1091 /* Omit the four octet CRC from the length. */
1092 short pkt_len = ep->rx_ring[entry].rxlength - 4;
1093 struct sk_buff *skb;
1094
1095 /* Check if the packet is long enough to accept without copying
1096 to a minimally-sized skbuff. */
1097 if (pkt_len < rx_copybreak
1098 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1099 skb->dev = dev;
1100 skb_reserve(skb, 2); /* 16 byte align the IP header */
1101 #if 1 /* USE_IP_COPYSUM */
1102 eth_copy_and_sum(skb, bus_to_virt(ep->rx_ring[entry].bufaddr),
1103 pkt_len, 0);
1104 skb_put(skb, pkt_len);
1105 #else
1106 memcpy(skb_put(skb, pkt_len),
1107 bus_to_virt(ep->rx_ring[entry].bufaddr), pkt_len);
1108 #endif
1109 ep->rx_ring[entry].status = 0x8000;
1110 } else {
1111 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1112 ep->rx_skbuff[entry] = NULL;
1113 }
1114 skb->protocol = eth_type_trans(skb, dev);
1115 netif_rx(skb);
1116 ep->stats.rx_packets++;
1117 /* rx_bytes counting -- Nolan Leake */
1118 ep->stats.rx_bytes += pkt_len;
1119 }
1120 work_done++;
1121 entry = (++ep->cur_rx) % RX_RING_SIZE;
1122 }
1123
1124 /* Refill the Rx ring buffers. */
1125 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1126 entry = ep->dirty_rx % RX_RING_SIZE;
1127 if (ep->rx_skbuff[entry] == NULL) {
1128 struct sk_buff *skb;
1129 skb = ep->rx_skbuff[entry] = dev_alloc_skb(PKT_BUF_SZ);
1130 if (skb == NULL)
1131 break;
1132 skb->dev = dev; /* Mark as being used by this device. */
1133 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1134 ep->rx_ring[entry].bufaddr = virt_to_bus(skb->tail);
1135 work_done++;
1136 }
1137 ep->rx_ring[entry].status = 0x8000;
1138 }
1139 return work_done;
1140 }
1141
1142 static int epic_close(struct net_device *dev)
1143 {
1144 long ioaddr = dev->base_addr;
1145 struct epic_private *ep = (struct epic_private *)dev->priv;
1146 int i;
1147
1148 dev->start = 0;
1149 dev->tbusy = 1;
1150
1151 if (epic_debug > 1)
1152 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1153 dev->name, inl(ioaddr + INTSTAT));
1154
1155 /* Disable interrupts by clearing the interrupt mask. */
1156 outl(0x00000000, ioaddr + INTMASK);
1157 /* Stop the chip's Tx and Rx DMA processes. */
1158 outw(0x0061, ioaddr + COMMAND);
1159
1160 /* Update the error counts. */
1161 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1162 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1163 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1164
1165 del_timer(&ep->timer);
1166
1167 free_irq(dev->irq, dev);
1168
1169 /* Free all the skbuffs in the Rx queue. */
1170 for (i = 0; i < RX_RING_SIZE; i++) {
1171 struct sk_buff *skb = ep->rx_skbuff[i];
1172 ep->rx_skbuff[i] = 0;
1173 ep->rx_ring[i].status = 0; /* Not owned by Epic chip. */
1174 ep->rx_ring[i].buflength = 0;
1175 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1176 if (skb) {
1177 #if LINUX_VERSION_CODE < 0x20100
1178 skb->free = 1;
1179 #endif
1180 DEV_FREE_SKB(skb);
1181 }
1182 }
1183 for (i = 0; i < TX_RING_SIZE; i++) {
1184 if (ep->tx_skbuff[i])
1185 DEV_FREE_SKB(ep->tx_skbuff[i]);
1186 ep->tx_skbuff[i] = 0;
1187 }
1188
1189
1190 /* Green! Leave the chip in low-power mode. */
1191 outl(0x0008, ioaddr + GENCTL);
1192
1193 MOD_DEC_USE_COUNT;
1194
1195 return 0;
1196 }
1197
1198 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1199 {
1200 struct epic_private *ep = (struct epic_private *)dev->priv;
1201 long ioaddr = dev->base_addr;
1202
1203 if (dev->start) {
1204 /* Update the error counts. */
1205 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1206 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1207 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1208 }
1209
1210 return &ep->stats;
1211 }
1212
1213 /* Set or clear the multicast filter for this adaptor.
1214 Note that we only use exclusion around actually queueing the
1215 new frame, not around filling ep->setup_frame. This is non-deterministic
1216 when re-entered but still correct. */
1217
1218 /* The little-endian AUTODIN II ethernet CRC calculation.
1219 N.B. Do not use for bulk data, use a table-based routine instead.
1220 This is common code and should be moved to net/core/crc.c */
1221 static unsigned const ethernet_polynomial_le = 0xedb88320U;
1222 static inline unsigned ether_crc_le(int length, unsigned char *data)
1223 {
1224 unsigned int crc = 0xffffffff; /* Initial value. */
1225 while(--length >= 0) {
1226 unsigned char current_octet = *data++;
1227 int bit;
1228 for (bit = 8; --bit >= 0; current_octet >>= 1) {
1229 if ((crc ^ current_octet) & 1) {
1230 crc >>= 1;
1231 crc ^= ethernet_polynomial_le;
1232 } else
1233 crc >>= 1;
1234 }
1235 }
1236 return crc;
1237 }
1238
1239
1240 static void set_rx_mode(struct net_device *dev)
1241 {
1242 long ioaddr = dev->base_addr;
1243 struct epic_private *ep = (struct epic_private *)dev->priv;
1244 unsigned char mc_filter[8]; /* Multicast hash filter */
1245 int i;
1246
1247 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1248 outl(0x002C, ioaddr + RxCtrl);
1249 /* Unconditionally log net taps. */
1250 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1251 memset(mc_filter, 0xff, sizeof(mc_filter));
1252 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1253 /* There is apparently a chip bug, so the multicast filter
1254 is never enabled. */
1255 /* Too many to filter perfectly -- accept all multicasts. */
1256 memset(mc_filter, 0xff, sizeof(mc_filter));
1257 outl(0x000C, ioaddr + RxCtrl);
1258 } else if (dev->mc_count == 0) {
1259 outl(0x0004, ioaddr + RxCtrl);
1260 return;
1261 } else { /* Never executed, for now. */
1262 struct dev_mc_list *mclist;
1263
1264 memset(mc_filter, 0, sizeof(mc_filter));
1265 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1266 i++, mclist = mclist->next)
1267 set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f,
1268 mc_filter);
1269 }
1270 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1271 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1272 for (i = 0; i < 4; i++)
1273 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1274 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1275 }
1276 return;
1277 }
1278
1279 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1280 {
1281 long ioaddr = dev->base_addr;
1282 u16 *data = (u16 *)&rq->ifr_data;
1283
1284 switch(cmd) {
1285 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1286 data[0] = ((struct epic_private *)dev->priv)->phys[0] & 0x1f;
1287 /* Fall Through */
1288 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1289 if (! dev->start) {
1290 outl(0x0200, ioaddr + GENCTL);
1291 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1292 }
1293 data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f);
1294 if (! dev->start) {
1295 #ifdef notdef
1296 outl(0x0008, ioaddr + GENCTL);
1297 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1298 #endif
1299 }
1300 return 0;
1301 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1302 if (!suser())
1303 return -EPERM;
1304 if (! dev->start) {
1305 outl(0x0200, ioaddr + GENCTL);
1306 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1307 }
1308 mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1309 if (! dev->start) {
1310 #ifdef notdef
1311 outl(0x0008, ioaddr + GENCTL);
1312 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1313 #endif
1314 }
1315 return 0;
1316 default:
1317 return -EOPNOTSUPP;
1318 }
1319 }
1320
1321 \f
1322 #ifdef CARDBUS
1323
1324 #include <pcmcia/driver_ops.h>
1325
1326 static dev_node_t *epic_attach(dev_locator_t *loc)
1327 {
1328 struct net_device *dev;
1329 u16 dev_id;
1330 u32 io;
1331 u8 bus, devfn, irq;
1332
1333 if (loc->bus != LOC_PCI) return NULL;
1334 bus = loc->b.pci.bus; devfn = loc->b.pci.devfn;
1335 printk(KERN_DEBUG "epic_attach(bus %d, function %d)\n", bus, devfn);
1336 pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io);
1337 pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq);
1338 pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id);
1339 io &= ~3;
1340 if (io == 0 || irq == 0) {
1341 printk(KERN_ERR "The EPIC/C CardBus Ethernet interface was not "
1342 "assigned an %s.\n" KERN_ERR " It will not be activated.\n",
1343 io == 0 ? "I/O address" : "IRQ");
1344 return NULL;
1345 }
1346 dev = epic_probe1(bus, devfn, NULL, io, irq, 2, -1);
1347 if (dev) {
1348 dev_node_t *node = kmalloc(sizeof(dev_node_t), GFP_KERNEL);
1349 strcpy(node->dev_name, dev->name);
1350 node->major = node->minor = 0;
1351 node->next = NULL;
1352 MOD_INC_USE_COUNT;
1353 return node;
1354 }
1355 return NULL;
1356 }
1357
1358 static void epic_suspend(dev_node_t *node)
1359 {
1360 struct net_device **devp, **next;
1361 printk(KERN_INFO "epic_suspend(%s)\n", node->dev_name);
1362 for (devp = &root_epic_dev; *devp; devp = next) {
1363 next = &((struct epic_private *)(*devp)->priv)->next_module;
1364 if (strcmp((*devp)->name, node->dev_name) == 0) break;
1365 }
1366 if (*devp) {
1367 long ioaddr = (*devp)->base_addr;
1368 epic_pause(*devp);
1369 /* Put the chip into low-power mode. */
1370 outl(0x0008, ioaddr + GENCTL);
1371 }
1372 }
1373 static void epic_resume(dev_node_t *node)
1374 {
1375 struct net_device **devp, **next;
1376 printk(KERN_INFO "epic_resume(%s)\n", node->dev_name);
1377 for (devp = &root_epic_dev; *devp; devp = next) {
1378 next = &((struct epic_private *)(*devp)->priv)->next_module;
1379 if (strcmp((*devp)->name, node->dev_name) == 0) break;
1380 }
1381 if (*devp) {
1382 epic_restart(*devp);
1383 }
1384 }
1385 static void epic_detach(dev_node_t *node)
1386 {
1387 struct net_device **devp, **next;
1388 printk(KERN_INFO "epic_detach(%s)\n", node->dev_name);
1389 for (devp = &root_epic_dev; *devp; devp = next) {
1390 next = &((struct epic_private *)(*devp)->priv)->next_module;
1391 if (strcmp((*devp)->name, node->dev_name) == 0) break;
1392 }
1393 if (*devp) {
1394 unregister_netdev(*devp);
1395 kfree(*devp);
1396 *devp = *next;
1397 kfree(node);
1398 MOD_DEC_USE_COUNT;
1399 }
1400 }
1401
1402 struct driver_operations epic_ops = {
1403 "epic_cb", epic_attach, epic_suspend, epic_resume, epic_detach
1404 };
1405
1406 #endif /* Cardbus support */
1407
1408 \f
1409 #ifdef MODULE
1410
1411 int init_module(void)
1412 {
1413 if (epic_debug)
1414 printk(KERN_INFO "%s", version);
1415
1416 #ifdef CARDBUS
1417 register_driver(&epic_ops);
1418 return 0;
1419 #else
1420 return epic100_probe(0);
1421 #endif
1422 }
1423
1424 void cleanup_module(void)
1425 {
1426 struct net_device *next_dev;
1427
1428 #ifdef CARDBUS
1429 unregister_driver(&epic_ops);
1430 #endif
1431
1432 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1433 while (root_epic_dev) {
1434 struct epic_private *ep = (struct epic_private *)root_epic_dev->priv;
1435 next_dev = ep->next_module;
1436 unregister_netdev(root_epic_dev);
1437 release_region(root_epic_dev->base_addr, EPIC_TOTAL_SIZE);
1438 kfree(root_epic_dev);
1439 root_epic_dev = next_dev;
1440 kfree(ep);
1441 }
1442 }
1443
1444 #endif /* MODULE */
1445 \f
1446 /*
1447 * Local variables:
1448 * compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c epic100.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`"
1449 * cardbus-compile-command: "gcc -DCARDBUS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c epic100.c -o epic_cb.o -I/usr/src/pcmcia-cs-3.0.5/include/"
1450 * c-indent-level: 4
1451 * c-basic-offset: 4
1452 * tab-width: 4
1453 * End:
1454 */