?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* add p cc
[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / net / sunbmac.c
blobf4a926dc906408a41886adcf0e48ae8bf7188ccc
1 /* sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
2 *
3 * Copyright (C) 1997, 1998 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6 static char *version =
7 "sunbmac.c:v1.1 8/Dec/98 David S. Miller (davem@caipfs.rutgers.edu)\n";
8
9 #include <linux/module.h>
10
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/types.h>
14 #include <linux/fcntl.h>
15 #include <linux/interrupt.h>
16 #include <linux/ptrace.h>
17 #include <linux/ioport.h>
18 #include <linux/in.h>
19 #include <linux/malloc.h>
20 #include <linux/string.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <asm/system.h>
24 #include <asm/bitops.h>
25 #include <asm/io.h>
26 #include <asm/dma.h>
27 #include <linux/errno.h>
28 #include <asm/byteorder.h>
29
30 #include <asm/idprom.h>
31 #include <asm/sbus.h>
32 #include <asm/openprom.h>
33 #include <asm/oplib.h>
34 #include <asm/auxio.h>
35 #include <asm/pgtable.h>
36
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/skbuff.h>
40
41 #include "sunbmac.h"
42
43 #undef DEBUG_PROBE
44 #undef DEBUG_TX
45 #undef DEBUG_IRQ
46
47 #ifdef DEBUG_PROBE
48 #define DP(x) printk x
49 #else
50 #define DP(x)
51 #endif
52
53 #ifdef DEBUG_TX
54 #define DTX(x) printk x
55 #else
56 #define DTX(x)
57 #endif
58
59 #ifdef DEBUG_IRQ
60 #define DIRQ(x) printk x
61 #else
62 #define DIRQ(x)
63 #endif
64
65 #ifdef MODULE
66 static struct bigmac *root_bigmac_dev = NULL;
67 #endif
68
69 #define DEFAULT_JAMSIZE 4 /* Toe jam */
70
71 #define QEC_RESET_TRIES 200
72
73 static inline int qec_global_reset(struct qe_globreg *gregs)
74 {
75 int tries = QEC_RESET_TRIES;
76
77 gregs->ctrl = GLOB_CTRL_RESET;
78 while(--tries) {
79 if(gregs->ctrl & GLOB_CTRL_RESET) {
80 udelay(20);
81 continue;
82 }
83 break;
84 }
85 if(tries)
86 return 0;
87 printk("BigMAC: Cannot reset the QEC.\n");
88 return -1;
89 }
90
91 static void qec_init(struct bigmac *bp)
92 {
93 struct qe_globreg *gregs = bp->gregs;
94 struct linux_sbus_device *qec_sdev = bp->qec_sbus_dev;
95 unsigned char bsizes = bp->bigmac_bursts;
96 unsigned int regval;
97
98 /* 64byte bursts do not work at the moment, do
99 * not even try to enable them. -DaveM
100 */
101 if(bsizes & DMA_BURST32)
102 regval = GLOB_CTRL_B32;
103 else
104 regval = GLOB_CTRL_B16;
105 gregs->ctrl = regval | GLOB_CTRL_BMODE;
106
107 gregs->psize = GLOB_PSIZE_2048;
108
109 /* All of memsize is given to bigmac. */
110 gregs->msize = qec_sdev->reg_addrs[1].reg_size;
111
112 /* Half to the transmitter, half to the receiver. */
113 gregs->rsize = gregs->tsize = qec_sdev->reg_addrs[1].reg_size >> 1;
114 }
115
116 /* XXX auto negotiation on these things might not be pleasant... */
117
118 #define TX_RESET_TRIES 32
119 #define RX_RESET_TRIES 32
120
121 static inline void bigmac_tx_reset(struct BIG_MAC_regs *bregs)
122 {
123 int tries = TX_RESET_TRIES;
124
125 bregs->tx_cfg = 0;
126
127 /* The fifo threshold bit is read-only and does
128 * not clear. -DaveM
129 */
130 while((bregs->tx_cfg & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
131 --tries != 0)
132 udelay(20);
133
134 if(!tries) {
135 printk("BIGMAC: Transmitter will not reset.\n");
136 printk("BIGMAC: tx_cfg is %08x\n", bregs->tx_cfg);
137 }
138 }
139
140 static inline void bigmac_rx_reset(struct BIG_MAC_regs *bregs)
141 {
142 int tries = RX_RESET_TRIES;
143
144 bregs->rx_cfg = 0;
145 while((bregs->rx_cfg) && --tries)
146 udelay(20);
147
148 if(!tries) {
149 printk("BIGMAC: Receiver will not reset.\n");
150 printk("BIGMAC: rx_cfg is %08x\n", bregs->rx_cfg);
151 }
152 }
153
154 /* Reset the transmitter and receiver. */
155 static void bigmac_stop(struct bigmac *bp)
156 {
157 bigmac_tx_reset(bp->bregs);
158 bigmac_rx_reset(bp->bregs);
159 }
160
161 static void bigmac_get_counters(struct bigmac *bp, struct BIG_MAC_regs *bregs)
162 {
163 struct enet_statistics *stats = &bp->enet_stats;
164
165 stats->rx_crc_errors += bregs->rcrce_ctr;
166 bregs->rcrce_ctr = 0;
167
168 stats->rx_frame_errors += bregs->unale_ctr;
169 bregs->unale_ctr = 0;
170
171 stats->rx_length_errors += bregs->gle_ctr;
172 bregs->gle_ctr = 0;
173
174 stats->tx_aborted_errors += bregs->ex_ctr;
175
176 stats->collisions += (bregs->ex_ctr + bregs->lt_ctr);
177 bregs->ex_ctr = bregs->lt_ctr = 0;
178 }
179
180 static inline void bigmac_clean_rings(struct bigmac *bp)
181 {
182 int i;
183
184 for(i = 0; i < RX_RING_SIZE; i++) {
185 if(bp->rx_skbs[i] != NULL) {
186 dev_kfree_skb(bp->rx_skbs[i]);
187 bp->rx_skbs[i] = NULL;
188 }
189 }
190
191 for(i = 0; i < TX_RING_SIZE; i++) {
192 if(bp->tx_skbs[i] != NULL) {
193 dev_kfree_skb(bp->tx_skbs[i]);
194 bp->tx_skbs[i] = NULL;
195 }
196 }
197 }
198
199 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
200 {
201 struct bmac_init_block *bb = bp->bmac_block;
202 struct net_device *dev = bp->dev;
203 int i, gfp_flags = GFP_KERNEL;
204
205 if(from_irq || in_interrupt())
206 gfp_flags = GFP_ATOMIC;
207
208 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
209
210 /* Free any skippy bufs left around in the rings. */
211 bigmac_clean_rings(bp);
212
213 /* Now get new skippy bufs for the receive ring. */
214 for(i = 0; i < RX_RING_SIZE; i++) {
215 struct sk_buff *skb;
216
217 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
218 if(!skb)
219 continue;
220
221 bp->rx_skbs[i] = skb;
222 skb->dev = dev;
223
224 /* Because we reserve afterwards. */
225 skb_put(skb, ETH_FRAME_LEN);
226 skb_reserve(skb, 34);
227
228 bb->be_rxd[i].rx_addr = sbus_dvma_addr(skb->data);
229 bb->be_rxd[i].rx_flags =
230 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
231 }
232
233 for(i = 0; i < TX_RING_SIZE; i++)
234 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
235 }
236
237 #ifndef __sparc_v9__
238 static void sun4c_bigmac_init_rings(struct bigmac *bp)
239 {
240 struct bmac_init_block *bb = bp->bmac_block;
241 __u32 bbufs_dvma = bp->s4c_buf_dvma;
242 int i;
243
244 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
245
246 for(i = 0; i < RX_RING_SIZE; i++) {
247 bb->be_rxd[i].rx_addr = bbufs_dvma + bbuf_offset(rx_buf, i);
248 bb->be_rxd[i].rx_flags =
249 (RXD_OWN | (SUN4C_RX_BUFF_SIZE & RXD_LENGTH));
250 }
251
252 for(i = 0; i < TX_RING_SIZE; i++)
253 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
254 }
255 #endif
256
257 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
258 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
259
260 static inline void idle_transceiver(struct bmac_tcvr *tregs)
261 {
262 volatile unsigned int garbage;
263 int i = 20;
264
265 while(i--) {
266 tregs->mgmt_pal = MGMT_CLKOFF;
267 garbage = tregs->mgmt_pal;
268 tregs->mgmt_pal = MGMT_CLKON;
269 garbage = tregs->mgmt_pal;
270 }
271 }
272
273 static void write_tcvr_bit(struct bigmac *bp, struct bmac_tcvr *tregs, int bit)
274 {
275 volatile unsigned int garbage;
276
277 if(bp->tcvr_type == internal) {
278 bit = (bit & 1) << 3;
279 tregs->mgmt_pal = bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO);
280 garbage = tregs->mgmt_pal;
281 tregs->mgmt_pal = bit | (MGMT_PAL_OENAB |
282 MGMT_PAL_EXT_MDIO |
283 MGMT_PAL_DCLOCK);
284 garbage = tregs->mgmt_pal;
285 } else if(bp->tcvr_type == external) {
286 bit = (bit & 1) << 2;
287 tregs->mgmt_pal = bit | (MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB);
288 garbage = tregs->mgmt_pal;
289 tregs->mgmt_pal = bit | (MGMT_PAL_INT_MDIO |
290 MGMT_PAL_OENAB |
291 MGMT_PAL_DCLOCK);
292 garbage = tregs->mgmt_pal;
293 } else {
294 printk("write_tcvr_bit: No transceiver type known!\n");
295 }
296 }
297
298 static int read_tcvr_bit(struct bigmac *bp, struct bmac_tcvr *tregs)
299 {
300 volatile unsigned int garbage;
301 int retval = 0;
302
303 if(bp->tcvr_type == internal) {
304 tregs->mgmt_pal = MGMT_PAL_EXT_MDIO;
305 garbage = tregs->mgmt_pal;
306 tregs->mgmt_pal = MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK;
307 garbage = tregs->mgmt_pal;
308 retval = (tregs->mgmt_pal & MGMT_PAL_INT_MDIO) >> 3;
309 } else if(bp->tcvr_type == external) {
310 tregs->mgmt_pal = MGMT_PAL_INT_MDIO;
311 garbage = tregs->mgmt_pal;
312 tregs->mgmt_pal = MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK;
313 garbage = tregs->mgmt_pal;
314 retval = (tregs->mgmt_pal & MGMT_PAL_EXT_MDIO) >> 2;
315 } else {
316 printk("read_tcvr_bit: No transceiver type known!\n");
317 }
318 return retval;
319 }
320
321 static int read_tcvr_bit2(struct bigmac *bp, struct bmac_tcvr *tregs)
322 {
323 volatile unsigned int garbage;
324 int retval = 0;
325
326 if(bp->tcvr_type == internal) {
327 tregs->mgmt_pal = MGMT_PAL_EXT_MDIO;
328 garbage = tregs->mgmt_pal;
329 retval = (tregs->mgmt_pal & MGMT_PAL_INT_MDIO) >> 3;
330 tregs->mgmt_pal = (MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK);
331 garbage = tregs->mgmt_pal;
332 } else if(bp->tcvr_type == external) {
333 tregs->mgmt_pal = MGMT_PAL_INT_MDIO;
334 garbage = tregs->mgmt_pal;
335 retval = (tregs->mgmt_pal & MGMT_PAL_EXT_MDIO) >> 2;
336 tregs->mgmt_pal = (MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK);
337 garbage = tregs->mgmt_pal;
338 } else {
339 printk("read_tcvr_bit2: No transceiver type known!\n");
340 }
341 return retval;
342 }
343
344 static inline void put_tcvr_byte(struct bigmac *bp,
345 struct bmac_tcvr *tregs,
346 unsigned int byte)
347 {
348 int shift = 4;
349
350 do {
351 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
352 shift -= 1;
353 } while (shift >= 0);
354 }
355
356 static void bigmac_tcvr_write(struct bigmac *bp, struct bmac_tcvr *tregs,
357 int reg, unsigned short val)
358 {
359 int shift;
360
361 reg &= 0xff;
362 val &= 0xffff;
363 switch(bp->tcvr_type) {
364 case internal:
365 case external:
366 break;
367
368 default:
369 printk("bigmac_tcvr_read: Whoops, no known transceiver type.\n");
370 return;
371 };
372
373 idle_transceiver(tregs);
374 write_tcvr_bit(bp, tregs, 0);
375 write_tcvr_bit(bp, tregs, 1);
376 write_tcvr_bit(bp, tregs, 0);
377 write_tcvr_bit(bp, tregs, 1);
378
379 put_tcvr_byte(bp, tregs,
380 ((bp->tcvr_type == internal) ?
381 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
382
383 put_tcvr_byte(bp, tregs, reg);
384
385 write_tcvr_bit(bp, tregs, 1);
386 write_tcvr_bit(bp, tregs, 0);
387
388 shift = 15;
389 do {
390 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
391 shift -= 1;
392 } while(shift >= 0);
393 }
394
395 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
396 struct bmac_tcvr *tregs,
397 int reg)
398 {
399 unsigned short retval = 0;
400
401 reg &= 0xff;
402 switch(bp->tcvr_type) {
403 case internal:
404 case external:
405 break;
406
407 default:
408 printk("bigmac_tcvr_read: Whoops, no known transceiver type.\n");
409 return 0xffff;
410 };
411
412 idle_transceiver(tregs);
413 write_tcvr_bit(bp, tregs, 0);
414 write_tcvr_bit(bp, tregs, 1);
415 write_tcvr_bit(bp, tregs, 1);
416 write_tcvr_bit(bp, tregs, 0);
417
418 put_tcvr_byte(bp, tregs,
419 ((bp->tcvr_type == internal) ?
420 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
421
422 put_tcvr_byte(bp, tregs, reg);
423
424 if(bp->tcvr_type == external) {
425 int shift = 15;
426
427 (void) read_tcvr_bit2(bp, tregs);
428 (void) read_tcvr_bit2(bp, tregs);
429
430 do {
431 int tmp;
432
433 tmp = read_tcvr_bit2(bp, tregs);
434 retval |= ((tmp & 1) << shift);
435 shift -= 1;
436 } while(shift >= 0);
437
438 (void) read_tcvr_bit2(bp, tregs);
439 (void) read_tcvr_bit2(bp, tregs);
440 (void) read_tcvr_bit2(bp, tregs);
441 } else {
442 int shift = 15;
443
444 (void) read_tcvr_bit(bp, tregs);
445 (void) read_tcvr_bit(bp, tregs);
446
447 do {
448 int tmp;
449
450 tmp = read_tcvr_bit(bp, tregs);
451 retval |= ((tmp & 1) << shift);
452 shift -= 1;
453 } while(shift >= 0);
454
455 (void) read_tcvr_bit(bp, tregs);
456 (void) read_tcvr_bit(bp, tregs);
457 (void) read_tcvr_bit(bp, tregs);
458 }
459 return retval;
460 }
461
462 static void bigmac_tcvr_init(struct bigmac *bp)
463 {
464 volatile unsigned int garbage;
465 struct bmac_tcvr *tregs = bp->tregs;
466
467 idle_transceiver(tregs);
468 tregs->mgmt_pal = (MGMT_PAL_INT_MDIO |
469 MGMT_PAL_EXT_MDIO |
470 MGMT_PAL_DCLOCK);
471 garbage = tregs->mgmt_pal;
472
473 /* Only the bit for the present transceiver (internal or
474 * external) will stick, set them both and see what stays.
475 */
476 tregs->mgmt_pal = (MGMT_PAL_INT_MDIO |
477 MGMT_PAL_EXT_MDIO);
478 garbage = tregs->mgmt_pal;
479 udelay(20);
480
481 if(tregs->mgmt_pal & MGMT_PAL_EXT_MDIO) {
482 bp->tcvr_type = external;
483 tregs->tcvr_pal = ~(TCVR_PAL_EXTLBACK |
484 TCVR_PAL_MSENSE |
485 TCVR_PAL_LTENABLE);
486 garbage = tregs->tcvr_pal;
487 } else if(tregs->mgmt_pal & MGMT_PAL_INT_MDIO) {
488 bp->tcvr_type = internal;
489 tregs->tcvr_pal = ~(TCVR_PAL_SERIAL |
490 TCVR_PAL_EXTLBACK |
491 TCVR_PAL_MSENSE |
492 TCVR_PAL_LTENABLE);
493 garbage = tregs->tcvr_pal;
494 } else {
495 printk("BIGMAC: AIEEE, neither internal nor "
496 "external MDIO available!\n");
497 printk("BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
498 tregs->mgmt_pal, tregs->tcvr_pal);
499 }
500 }
501
502 static int bigmac_init(struct bigmac *, int);
503
504 static int try_next_permutation(struct bigmac *bp, struct bmac_tcvr *tregs)
505 {
506 if(bp->sw_bmcr & BMCR_SPEED100) {
507 int timeout;
508
509 /* Reset the PHY. */
510 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
511 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
512 bp->sw_bmcr = (BMCR_RESET);
513 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
514
515 timeout = 64;
516 while(--timeout) {
517 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
518 if((bp->sw_bmcr & BMCR_RESET) == 0)
519 break;
520 udelay(20);
521 }
522 if(timeout == 0)
523 printk("%s: PHY reset failed.\n", bp->dev->name);
524
525 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
526
527 /* Now we try 10baseT. */
528 bp->sw_bmcr &= ~(BMCR_SPEED100);
529 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
530 return 0;
531 }
532
533 /* We've tried them all. */
534 return -1;
535 }
536
537 static void bigmac_timer(unsigned long data)
538 {
539 struct bigmac *bp = (struct bigmac *) data;
540 struct bmac_tcvr *tregs = bp->tregs;
541 int restart_timer = 0;
542
543 bp->timer_ticks++;
544 if(bp->timer_state == ltrywait) {
545 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
546 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
547 if(bp->sw_bmsr & BMSR_LSTATUS) {
548 printk("%s: Link is now up at %s.\n",
549 bp->dev->name,
550 (bp->sw_bmcr & BMCR_SPEED100) ?
551 "100baseT" : "10baseT");
552 bp->timer_state = asleep;
553 restart_timer = 0;
554 } else {
555 if(bp->timer_ticks >= 4) {
556 int ret;
557
558 ret = try_next_permutation(bp, tregs);
559 if(ret == -1) {
560 printk("%s: Link down, cable problem?\n",
561 bp->dev->name);
562 ret = bigmac_init(bp, 0);
563 if(ret) {
564 printk("%s: Error, cannot re-init the "
565 "BigMAC.\n", bp->dev->name);
566 }
567 return;
568 }
569 bp->timer_ticks = 0;
570 restart_timer = 1;
571 } else {
572 restart_timer = 1;
573 }
574 }
575 } else {
576 /* Can't happens.... */
577 printk("%s: Aieee, link timer is asleep but we got one anyways!\n",
578 bp->dev->name);
579 restart_timer = 0;
580 bp->timer_ticks = 0;
581 bp->timer_state = asleep; /* foo on you */
582 }
583
584 if(restart_timer != 0) {
585 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
586 add_timer(&bp->bigmac_timer);
587 }
588 }
589
590 /* Well, really we just force the chip into 100baseT then
591 * 10baseT, each time checking for a link status.
592 */
593 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
594 {
595 struct bmac_tcvr *tregs = bp->tregs;
596 int timeout;
597
598 /* Grab new software copies of PHY registers. */
599 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
600 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
601
602 /* Reset the PHY. */
603 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
604 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
605 bp->sw_bmcr = (BMCR_RESET);
606 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
607
608 timeout = 64;
609 while(--timeout) {
610 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
611 if((bp->sw_bmcr & BMCR_RESET) == 0)
612 break;
613 udelay(20);
614 }
615 if(timeout == 0)
616 printk("%s: PHY reset failed.\n", bp->dev->name);
617
618 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
619
620 /* First we try 100baseT. */
621 bp->sw_bmcr |= BMCR_SPEED100;
622 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
623
624 bp->timer_state = ltrywait;
625 bp->timer_ticks = 0;
626 bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
627 bp->bigmac_timer.data = (unsigned long) bp;
628 bp->bigmac_timer.function = &bigmac_timer;
629 add_timer(&bp->bigmac_timer);
630 }
631
632 static int bigmac_init(struct bigmac *bp, int from_irq)
633 {
634 struct qe_globreg *gregs = bp->gregs;
635 struct qe_creg *cregs = bp->creg;
636 struct BIG_MAC_regs *bregs = bp->bregs;
637 unsigned char *e = &bp->dev->dev_addr[0];
638
639 /* Latch current counters into statistics. */
640 bigmac_get_counters(bp, bregs);
641
642 /* Reset QEC. */
643 qec_global_reset(gregs);
644
645 /* Init QEC. */
646 qec_init(bp);
647
648 /* Alloc and reset the tx/rx descriptor chains. */
649 #ifndef __sparc_v9__
650 if(sparc_cpu_model == sun4c)
651 sun4c_bigmac_init_rings(bp);
652 else
653 #endif
654 bigmac_init_rings(bp, from_irq);
655
656 /* Initialize the PHY. */
657 bigmac_tcvr_init(bp);
658
659 /* Stop transmitter and receiver. */
660 bigmac_stop(bp);
661
662 /* Set hardware ethernet address. */
663 bregs->mac_addr2 = ((e[4] << 8) | e[5]);
664 bregs->mac_addr1 = ((e[2] << 8) | e[3]);
665 bregs->mac_addr0 = ((e[0] << 8) | e[1]);
666
667 /* Clear the hash table until mc upload occurs. */
668 bregs->htable3 = 0;
669 bregs->htable2 = 0;
670 bregs->htable1 = 0;
671 bregs->htable0 = 0;
672
673 /* Enable Big Mac hash table filter. */
674 bregs->rx_cfg = (BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO);
675
676 udelay(20);
677
678 /* Ok, configure the Big Mac transmitter. */
679 bregs->tx_cfg = BIGMAC_TXCFG_FIFO;
680
681 /* The HME docs recommend to use the 10LSB of our MAC here. */
682 bregs->rand_seed = ((e[5] | e[4] << 8) & 0x3ff);
683
684 /* Enable the output drivers no matter what. */
685 bregs->xif_cfg = (BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV);
686
687 /* Tell the QEC where the ring descriptors are. */
688 cregs->rxds = bp->bblock_dvma + bib_offset(be_rxd, 0);
689 cregs->txds = bp->bblock_dvma + bib_offset(be_txd, 0);
690
691 /* Setup the FIFO pointers into QEC local memory. */
692 cregs->rxwbufptr = cregs->rxrbufptr = 0;
693 cregs->txwbufptr = cregs->txrbufptr = gregs->rsize;
694
695 /* Tell bigmac what interrupts we don't want to hear about. */
696 bregs->imask = (BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME);
697
698 /* Enable the various other irq's. */
699 cregs->rimask = 0;
700 cregs->timask = 0;
701 cregs->qmask = 0;
702 cregs->bmask = 0;
703
704 /* Set jam size to a reasonable default. */
705 bregs->jsize = DEFAULT_JAMSIZE;
706
707 /* Clear collision counter. */
708 cregs->ccnt = 0;
709
710 /* Enable transmitter and receiver. */
711 bregs->tx_cfg |= BIGMAC_TXCFG_ENABLE;
712 bregs->rx_cfg |= BIGMAC_RXCFG_ENABLE;
713
714 /* Ok, start detecting link speed/duplex. */
715 bigmac_begin_auto_negotiation(bp);
716
717 /* Success. */
718 return 0;
719 }
720
721 /* Error interrupts get sent here. */
722 static void bigmac_is_medium_rare(struct bigmac *bp,
723 unsigned int qec_status,
724 unsigned int bmac_status)
725 {
726 printk("bigmac_is_medium_rare: ");
727 if(qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
728 if(qec_status & GLOB_STAT_ER)
729 printk("QEC_ERROR, ");
730 if(qec_status & GLOB_STAT_BM)
731 printk("QEC_BMAC_ERROR, ");
732 }
733 if(bmac_status & CREG_STAT_ERRORS) {
734 if(bmac_status & CREG_STAT_BERROR)
735 printk("BMAC_ERROR, ");
736 if(bmac_status & CREG_STAT_TXDERROR)
737 printk("TXD_ERROR, ");
738 if(bmac_status & CREG_STAT_TXLERR)
739 printk("TX_LATE_ERROR, ");
740 if(bmac_status & CREG_STAT_TXPERR)
741 printk("TX_PARITY_ERROR, ");
742 if(bmac_status & CREG_STAT_TXSERR)
743 printk("TX_SBUS_ERROR, ");
744
745 if(bmac_status & CREG_STAT_RXDROP)
746 printk("RX_DROP_ERROR, ");
747
748 if(bmac_status & CREG_STAT_RXSMALL)
749 printk("RX_SMALL_ERROR, ");
750 if(bmac_status & CREG_STAT_RXLERR)
751 printk("RX_LATE_ERROR, ");
752 if(bmac_status & CREG_STAT_RXPERR)
753 printk("RX_PARITY_ERROR, ");
754 if(bmac_status & CREG_STAT_RXSERR)
755 printk("RX_SBUS_ERROR, ");
756 }
757
758 printk(" RESET\n");
759 bigmac_init(bp, 1);
760 }
761
762 /* BigMAC transmit complete service routines. */
763 static inline void bigmac_tx(struct bigmac *bp)
764 {
765 struct be_txd *txbase = &bp->bmac_block->be_txd[0];
766 struct be_txd *this;
767 int elem = bp->tx_old;
768
769 DTX(("bigmac_tx: tx_old[%d] ", elem));
770 while(elem != bp->tx_new) {
771 struct sk_buff *skb;
772
773 this = &txbase[elem];
774
775 DTX(("this(%p) [flags(%08x)addr(%08x)]",
776 this, this->tx_flags, this->tx_addr));
777
778 if(this->tx_flags & TXD_OWN)
779 break;
780 skb = bp->tx_skbs[elem];
781 DTX(("skb(%p) ", skb));
782 bp->tx_skbs[elem] = NULL;
783 dev_kfree_skb(skb);
784
785 bp->enet_stats.tx_packets++;
786 elem = NEXT_TX(elem);
787 }
788 DTX((" DONE, tx_old=%d\n", elem));
789 bp->tx_old = elem;
790 }
791
792 #ifndef __sparc_v9__
793 static inline void sun4c_bigmac_tx(struct bigmac *bp)
794 {
795 struct be_txd *txbase = &bp->bmac_block->be_txd[0];
796 struct be_txd *this;
797 int elem = bp->tx_old;
798
799 while(elem != bp->tx_new) {
800 this = &txbase[elem];
801 if(this->tx_flags & TXD_OWN)
802 break;
803 bp->enet_stats.tx_packets++;
804 elem = NEXT_TX(elem);
805 }
806 bp->tx_old = elem;
807 }
808 #endif
809
810 /* BigMAC receive complete service routines. */
811 static inline void bigmac_rx(struct bigmac *bp)
812 {
813 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
814 struct be_rxd *this;
815 int elem = bp->rx_new, drops = 0;
816
817 this = &rxbase[elem];
818 while(!(this->rx_flags & RXD_OWN)) {
819 struct sk_buff *skb;
820 unsigned int flags = this->rx_flags;
821 int len = (flags & RXD_LENGTH); /* FCS not included */
822
823 /* Check for errors. */
824 if(len < ETH_ZLEN) {
825 bp->enet_stats.rx_errors++;
826 bp->enet_stats.rx_length_errors++;
827
828 drop_it:
829 /* Return it to the BigMAC. */
830 bp->enet_stats.rx_dropped++;
831 this->rx_addr = sbus_dvma_addr(bp->rx_skbs[elem]->data);
832 this->rx_flags =
833 (RXD_OWN | (RX_BUF_ALLOC_SIZE & RXD_LENGTH));
834 goto next;
835 }
836 skb = bp->rx_skbs[elem];
837 #ifdef NEED_DMA_SYNCHRONIZATION
838 #ifdef __sparc_v9__
839 if ((unsigned long) (skb->data + skb->len) >= MAX_DMA_ADDRESS) {
840 printk("sunbmac: Bogus DMA buffer address "
841 "[%016lx]\n", ((unsigned long) skb->data));
842 panic("DMA address too large, tell DaveM");
843 }
844 #endif
845 mmu_sync_dma(sbus_dvma_addr(skb->data),
846 skb->len, bp->bigmac_sbus_dev->my_bus);
847 #endif
848 if(len > RX_COPY_THRESHOLD) {
849 struct sk_buff *new_skb;
850
851 /* Now refill the entry, if we can. */
852 new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
853 if(!new_skb) {
854 drops++;
855 goto drop_it;
856 }
857 bp->rx_skbs[elem] = new_skb;
858 new_skb->dev = bp->dev;
859 skb_put(new_skb, ETH_FRAME_LEN);
860 skb_reserve(new_skb, 34);
861 rxbase[elem].rx_addr = sbus_dvma_addr(new_skb->data);
862 rxbase[elem].rx_flags =
863 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
864
865 /* Trim the original skb for the netif. */
866 skb_trim(skb, len);
867 } else {
868 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
869
870 if(!copy_skb) {
871 drops++;
872 goto drop_it;
873 }
874 copy_skb->dev = bp->dev;
875 skb_reserve(copy_skb, 2);
876 skb_put(copy_skb, len);
877 eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
878
879 /* Reuse otiginal ring buffer. */
880 rxbase[elem].rx_addr = sbus_dvma_addr(skb->data);
881 rxbase[elem].rx_flags =
882 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
883
884 skb = copy_skb;
885 }
886
887 /* No checksums done by the BigMAC ;-( */
888 skb->protocol = eth_type_trans(skb, bp->dev);
889 netif_rx(skb);
890 bp->enet_stats.rx_packets++;
891 next:
892 elem = NEXT_RX(elem);
893 this = &rxbase[elem];
894 }
895 bp->rx_new = elem;
896 if(drops)
897 printk("%s: Memory squeeze, deferring packet.\n", bp->dev->name);
898 }
899
900 #ifndef __sparc_v9__
901 static inline void sun4c_bigmac_rx(struct bigmac *bp)
902 {
903 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
904 struct be_rxd *this;
905 struct bigmac_buffers *bbufs = bp->sun4c_buffers;
906 __u32 bbufs_dvma = bp->s4c_buf_dvma;
907 int elem = bp->rx_new, drops = 0;
908
909 this = &rxbase[elem];
910 while(!(this->rx_flags & RXD_OWN)) {
911 struct sk_buff *skb;
912 unsigned char *this_bbuf =
913 bbufs->rx_buf[elem & (SUN4C_RX_RING_SIZE - 1)];
914 __u32 this_bbuf_dvma = bbufs_dvma +
915 bbuf_offset(rx_buf, (elem & (SUN4C_RX_RING_SIZE - 1)));
916 struct be_rxd *end_rxd =
917 &rxbase[(elem+SUN4C_RX_RING_SIZE)&(RX_RING_SIZE-1)];
918 unsigned int flags = this->rx_flags;
919 int len = (flags & RXD_LENGTH) - 4; /* FCS not included */
920
921 /* Check for errors. */
922 if(len < ETH_ZLEN) {
923 bp->enet_stats.rx_errors++;
924 bp->enet_stats.rx_length_errors++;
925 bp->enet_stats.rx_dropped++;
926 } else {
927 skb = dev_alloc_skb(len + 2);
928 if(skb == 0) {
929 drops++;
930 bp->enet_stats.rx_dropped++;
931 } else {
932 skb->dev = bp->dev;
933 skb_reserve(skb, 2);
934 skb_put(skb, len);
935 eth_copy_and_sum(skb, (unsigned char *)this_bbuf,
936 len, 0);
937 skb->protocol = eth_type_trans(skb, bp->dev);
938 netif_rx(skb);
939 bp->enet_stats.rx_packets++;
940 }
941 }
942 end_rxd->rx_addr = this_bbuf_dvma;
943 end_rxd->rx_flags = (RXD_OWN | (SUN4C_RX_BUFF_SIZE & RXD_LENGTH));
944
945 elem = NEXT_RX(elem);
946 this = &rxbase[elem];
947 }
948 bp->rx_new = elem;
949 if(drops)
950 printk("%s: Memory squeeze, deferring packet.\n", bp->dev->name);
951 }
952 #endif
953
954 static void bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
955 {
956 struct bigmac *bp = (struct bigmac *) dev_id;
957 unsigned int qec_status, bmac_status;
958
959 DIRQ(("bigmac_interrupt: "));
960
961 /* Latch status registers now. */
962 bmac_status = bp->creg->stat;
963 qec_status = bp->gregs->stat;
964
965 bp->dev->interrupt = 1;
966
967 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
968 if((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
969 (bmac_status & CREG_STAT_ERRORS))
970 bigmac_is_medium_rare(bp, qec_status, bmac_status);
971
972 if(bmac_status & CREG_STAT_TXIRQ)
973 bigmac_tx(bp);
974
975 if(bmac_status & CREG_STAT_RXIRQ)
976 bigmac_rx(bp);
977
978 if(bp->dev->tbusy && (TX_BUFFS_AVAIL(bp) >= 0)) {
979 bp->dev->tbusy = 0;
980 mark_bh(NET_BH);
981 }
982
983 bp->dev->interrupt = 0;
984 }
985
986 #ifndef __sparc_v9__
987 static void sun4c_bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
988 {
989 struct bigmac *bp = (struct bigmac *) dev_id;
990 unsigned int qec_status, bmac_status;
991
992 /* Latch status registers now. */
993 bmac_status = bp->creg->stat;
994 qec_status = bp->gregs->stat;
995
996 bp->dev->interrupt = 1;
997
998 if(qec_status & (GLOB_STAT_ER | GLOB_STAT_BM) ||
999 (bmac_status & CREG_STAT_ERRORS))
1000 bigmac_is_medium_rare(bp, qec_status, bmac_status);
1001
1002 if(bmac_status & CREG_STAT_TXIRQ)
1003 sun4c_bigmac_tx(bp);
1004
1005 if(bmac_status & CREG_STAT_RXIRQ)
1006 sun4c_bigmac_rx(bp);
1007
1008 if(bp->dev->tbusy && (SUN4C_TX_BUFFS_AVAIL(bp) >= 0)) {
1009 bp->dev->tbusy = 0;
1010 mark_bh(NET_BH);
1011 }
1012
1013 bp->dev->interrupt = 0;
1014 }
1015 #endif
1016
1017 static int bigmac_open(struct net_device *dev)
1018 {
1019 struct bigmac *bp = (struct bigmac *) dev->priv;
1020 int res;
1021
1022 #ifndef __sparc_v9__
1023 if(sparc_cpu_model == sun4c) {
1024 if(request_irq(dev->irq, &sun4c_bigmac_interrupt,
1025 SA_SHIRQ, "BIG MAC", (void *) bp)) {
1026 printk("BIGMAC: Can't order irq %d to go.\n", dev->irq);
1027 return -EAGAIN;
1028 }
1029 } else
1030 #endif
1031 if(request_irq(dev->irq, &bigmac_interrupt,
1032 SA_SHIRQ, "BIG MAC", (void *) bp)) {
1033 printk("BIGMAC: Can't order irq %d to go.\n", dev->irq);
1034 return -EAGAIN;
1035 }
1036 init_timer(&bp->bigmac_timer);
1037 res = bigmac_init(bp, 0);
1038 if(!res) {
1039 MOD_INC_USE_COUNT;
1040 }
1041 return res;
1042 }
1043
1044 static int bigmac_close(struct net_device *dev)
1045 {
1046 struct bigmac *bp = (struct bigmac *) dev->priv;
1047
1048 del_timer(&bp->bigmac_timer);
1049 bp->timer_state = asleep;
1050 bp->timer_ticks = 0;
1051
1052 bigmac_stop(bp);
1053 bigmac_clean_rings(bp);
1054 free_irq(dev->irq, (void *)bp);
1055 MOD_DEC_USE_COUNT;
1056 return 0;
1057 }
1058
1059 /* Put a packet on the wire. */
1060 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1061 {
1062 struct bigmac *bp = (struct bigmac *) dev->priv;
1063 int len, entry;
1064
1065 if(dev->tbusy) {
1066 int tickssofar = jiffies - dev->trans_start;
1067
1068 if (tickssofar < 40) {
1069 return 1;
1070 } else {
1071 printk ("%s: transmit timed out, resetting\n", dev->name);
1072 bp->enet_stats.tx_errors++;
1073 bigmac_init(bp, 0);
1074 dev->tbusy = 0;
1075 dev->trans_start = jiffies;
1076 dev_kfree_skb(skb);
1077 return 0;
1078 }
1079 }
1080
1081 if(test_and_set_bit(0, (void *) &dev->tbusy) != 0) {
1082 printk("%s: Transmitter access conflict.\n", dev->name);
1083 return 1;
1084 }
1085
1086 if(!TX_BUFFS_AVAIL(bp))
1087 return 1;
1088
1089 #ifdef NEED_DMA_SYNCHRONIZATION
1090 #ifdef __sparc_v9__
1091 if ((unsigned long) (skb->data + skb->len) >= MAX_DMA_ADDRESS) {
1092 struct sk_buff *new_skb = skb_copy(skb, GFP_DMA | GFP_ATOMIC);
1093 if(!new_skb)
1094 return 1;
1095 dev_kfree_skb(skb);
1096 skb = new_skb;
1097 }
1098 #endif
1099 mmu_sync_dma(sbus_dvma_addr(skb->data),
1100 skb->len, bp->bigmac_sbus_dev->my_bus);
1101 #endif
1102 len = skb->len;
1103 entry = bp->tx_new;
1104 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
1105
1106 /* Avoid a race... */
1107 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
1108
1109 bp->tx_skbs[entry] = skb;
1110 bp->bmac_block->be_txd[entry].tx_addr = sbus_dvma_addr(skb->data);
1111 bp->bmac_block->be_txd[entry].tx_flags =
1112 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
1113 dev->trans_start = jiffies;
1114 bp->tx_new = NEXT_TX(entry);
1115
1116 /* Get it going. */
1117 bp->creg->ctrl = CREG_CTRL_TWAKEUP;
1118
1119 if(TX_BUFFS_AVAIL(bp))
1120 dev->tbusy = 0;
1121
1122 return 0;
1123 }
1124
1125 #ifndef __sparc_v9__
1126 static int sun4c_bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1127 {
1128 struct bigmac *bp = (struct bigmac *) dev->priv;
1129 struct bigmac_buffers *bbufs = bp->sun4c_buffers;
1130 __u32 txbuf_dvma, bbufs_dvma = bp->s4c_buf_dvma;
1131 unsigned char *txbuf;
1132 int len, entry;
1133
1134 if(dev->tbusy) {
1135 int tickssofar = jiffies - dev->trans_start;
1136
1137 if (tickssofar < 40) {
1138 return 1;
1139 } else {
1140 printk ("%s: transmit timed out, resetting\n", dev->name);
1141 bp->enet_stats.tx_errors++;
1142 bigmac_init(bp, 0);
1143 dev->tbusy = 0;
1144 dev->trans_start = jiffies;
1145 return 0;
1146 }
1147 }
1148
1149 if(test_and_set_bit(0, (void *) &dev->tbusy) != 0) {
1150 printk("%s: Transmitter access conflict.\n", dev->name);
1151 return 1;
1152 }
1153
1154 if(!SUN4C_TX_BUFFS_AVAIL(bp))
1155 return 1;
1156
1157 len = skb->len;
1158 entry = bp->tx_new;
1159
1160 txbuf = &bbufs->tx_buf[entry][0];
1161 txbuf_dvma = bbufs_dvma + bbuf_offset(tx_buf, entry);
1162 memcpy(txbuf, skb->data, len);
1163
1164 /* Avoid a race... */
1165 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
1166
1167 bp->bmac_block->be_txd[entry].tx_addr = txbuf_dvma;
1168 bp->bmac_block->be_txd[entry].tx_flags =
1169 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
1170 bp->tx_new = NEXT_TX(entry);
1171
1172 /* Get it going. */
1173 dev->trans_start = jiffies;
1174 bp->creg->ctrl = CREG_CTRL_TWAKEUP;
1175
1176 dev_kfree_skb(skb);
1177
1178 if(SUN4C_TX_BUFFS_AVAIL(bp))
1179 dev->tbusy = 0;
1180
1181 return 0;
1182 }
1183 #endif
1184
1185 static struct enet_statistics *bigmac_get_stats(struct net_device *dev)
1186 {
1187 struct bigmac *bp = (struct bigmac *) dev->priv;
1188
1189 bigmac_get_counters(bp, bp->bregs);
1190 return &bp->enet_stats;
1191 }
1192
1193 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
1194 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
1195
1196 static void bigmac_set_multicast(struct net_device *dev)
1197 {
1198 struct bigmac *bp = (struct bigmac *) dev->priv;
1199 struct BIG_MAC_regs *bregs = bp->bregs;
1200 struct dev_mc_list *dmi = dev->mc_list;
1201 char *addrs;
1202 int i, j, bit, byte;
1203 u32 crc, poly = CRC_POLYNOMIAL_LE;
1204
1205 /* Disable the receiver. The bit self-clears when
1206 * the operation is complete.
1207 */
1208 bregs->rx_cfg &= ~(BIGMAC_RXCFG_ENABLE);
1209 while((bregs->rx_cfg & BIGMAC_RXCFG_ENABLE) != 0)
1210 udelay(20);
1211
1212 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1213 bregs->htable0 = 0xffff;
1214 bregs->htable1 = 0xffff;
1215 bregs->htable2 = 0xffff;
1216 bregs->htable3 = 0xffff;
1217 } else if(dev->flags & IFF_PROMISC) {
1218 bregs->rx_cfg |= BIGMAC_RXCFG_PMISC;
1219 } else {
1220 u16 hash_table[4];
1221
1222 for(i = 0; i < 4; i++)
1223 hash_table[i] = 0;
1224
1225 for(i = 0; i < dev->mc_count; i++) {
1226 addrs = dmi->dmi_addr;
1227 dmi = dmi->next;
1228
1229 if(!(*addrs & 1))
1230 continue;
1231
1232 crc = 0xffffffffU;
1233 for(byte = 0; byte < 6; byte++) {
1234 for(bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1235 int test;
1236
1237 test = ((bit ^ crc) & 0x01);
1238 crc >>= 1;
1239 if(test)
1240 crc = crc ^ poly;
1241 }
1242 }
1243 crc >>= 26;
1244 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1245 }
1246 bregs->htable0 = hash_table[0];
1247 bregs->htable1 = hash_table[1];
1248 bregs->htable2 = hash_table[2];
1249 bregs->htable3 = hash_table[3];
1250 }
1251
1252 /* Re-enable the receiver. */
1253 bregs->rx_cfg |= BIGMAC_RXCFG_ENABLE;
1254 }
1255
1256 static int __init bigmac_ether_init(struct net_device *dev, struct linux_sbus_device *qec_sdev)
1257 {
1258 static unsigned version_printed = 0;
1259 struct bigmac *bp = 0;
1260 unsigned char bsizes, bsizes_more;
1261 int i, j, num_qranges, res = ENOMEM;
1262 struct linux_prom_ranges qranges[8];
1263
1264 /* Get a new device struct for this interface. */
1265 dev = init_etherdev(0, sizeof(struct bigmac));
1266
1267 if(version_printed++ == 0)
1268 printk(version);
1269
1270 /* Report what we have found to the user. */
1271 printk("%s: BigMAC 100baseT Ethernet ", dev->name);
1272 dev->base_addr = (long) qec_sdev;
1273 for(i = 0; i < 6; i++)
1274 printk("%2.2x%c", dev->dev_addr[i] = idprom->id_ethaddr[i],
1275 i == 5 ? ' ' : ':');
1276 printk("\n");
1277
1278 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1279 bp = (struct bigmac *) dev->priv;
1280 bp->qec_sbus_dev = qec_sdev;
1281 bp->bigmac_sbus_dev = qec_sdev->child;
1282
1283 /* All further failures we find return this. */
1284 res = ENODEV;
1285
1286 /* Verify the registers we expect, are actually there. */
1287 if((bp->bigmac_sbus_dev->num_registers != 3) ||
1288 (bp->qec_sbus_dev->num_registers != 2)) {
1289 printk("BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1290 bp->qec_sbus_dev->num_registers,
1291 bp->bigmac_sbus_dev->num_registers);
1292 printk("BIGMAC: Would you like that for here or to go?\n");
1293 goto fail_and_cleanup;
1294 }
1295
1296 /* Fun with QEC ranges... */
1297 if(bp->bigmac_sbus_dev->ranges_applied == 0) {
1298 i = prom_getproperty(bp->qec_sbus_dev->prom_node, "ranges",
1299 (char *)&qranges[0], sizeof(qranges));
1300 num_qranges = (i / sizeof(struct linux_prom_ranges));
1301
1302 /* Now, apply all the ranges for the BigMAC. */
1303 for(j = 0; j < bp->bigmac_sbus_dev->num_registers; j++) {
1304 int k;
1305
1306 for(k = 0; k < num_qranges; k++)
1307 if(bp->bigmac_sbus_dev->reg_addrs[j].which_io ==
1308 qranges[k].ot_child_space)
1309 break;
1310 if(k >= num_qranges) {
1311 printk("BigMAC: Aieee, bogus QEC range for space %08x\n",
1312 bp->bigmac_sbus_dev->reg_addrs[j].which_io);
1313 goto fail_and_cleanup;
1314 }
1315 bp->bigmac_sbus_dev->reg_addrs[j].which_io = qranges[k].ot_parent_space;
1316 bp->bigmac_sbus_dev->reg_addrs[j].phys_addr += qranges[k].ot_parent_base;
1317 }
1318
1319 /* Next, apply SBUS ranges on top of what we just changed. */
1320 prom_apply_sbus_ranges(bp->bigmac_sbus_dev->my_bus,
1321 &bp->bigmac_sbus_dev->reg_addrs[0],
1322 bp->bigmac_sbus_dev->num_registers,
1323 bp->bigmac_sbus_dev);
1324 }
1325
1326 /* Apply SBUS ranges for the QEC parent. */
1327 prom_apply_sbus_ranges(bp->qec_sbus_dev->my_bus,
1328 &bp->qec_sbus_dev->reg_addrs[0],
1329 bp->qec_sbus_dev->num_registers,
1330 bp->qec_sbus_dev);
1331
1332 /* Map in QEC global control registers. */
1333 bp->gregs = sparc_alloc_io(bp->qec_sbus_dev->reg_addrs[0].phys_addr,
1334 0,
1335 sizeof(struct qe_globreg),
1336 "BigMAC QEC Global Regs",
1337 bp->qec_sbus_dev->reg_addrs[0].which_io,
1338 0);
1339 if(!bp->gregs) {
1340 printk("BIGMAC: Cannot map QEC global registers.\n");
1341 goto fail_and_cleanup;
1342 }
1343
1344 /* Make sure QEC is in BigMAC mode. */
1345 if((bp->gregs->ctrl & 0xf0000000) != GLOB_CTRL_BMODE) {
1346 printk("BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1347 goto fail_and_cleanup;
1348 }
1349
1350 /* Reset the QEC. */
1351 if(qec_global_reset(bp->gregs))
1352 goto fail_and_cleanup;
1353
1354 /* Get supported SBUS burst sizes. */
1355 bsizes = prom_getintdefault(bp->qec_sbus_dev->prom_node,
1356 "burst-sizes",
1357 0xff);
1358
1359 bsizes_more = prom_getintdefault(bp->qec_sbus_dev->my_bus->prom_node,
1360 "burst-sizes",
1361 0xff);
1362
1363 bsizes &= 0xff;
1364 if(bsizes_more != 0xff)
1365 bsizes &= bsizes_more;
1366 if(bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1367 (bsizes & DMA_BURST32) == 0)
1368 bsizes = (DMA_BURST32 - 1);
1369 bp->bigmac_bursts = bsizes;
1370
1371 /* Perform QEC initialization. */
1372 qec_init(bp);
1373
1374 /* Map in the BigMAC channel registers. */
1375 bp->creg = sparc_alloc_io(bp->bigmac_sbus_dev->reg_addrs[0].phys_addr,
1376 0,
1377 sizeof(struct qe_creg),
1378 "BigMAC QEC Channel Regs",
1379 bp->bigmac_sbus_dev->reg_addrs[0].which_io,
1380 0);
1381 if(!bp->creg) {
1382 printk("BIGMAC: Cannot map QEC channel registers.\n");
1383 goto fail_and_cleanup;
1384 }
1385
1386 /* Map in the BigMAC control registers. */
1387 bp->bregs = sparc_alloc_io(bp->bigmac_sbus_dev->reg_addrs[1].phys_addr,
1388 0,
1389 sizeof(struct BIG_MAC_regs),
1390 "BigMAC Primary Regs",
1391 bp->bigmac_sbus_dev->reg_addrs[1].which_io,
1392 0);
1393 if(!bp->bregs) {
1394 printk("BIGMAC: Cannot map BigMAC primary registers.\n");
1395 goto fail_and_cleanup;
1396 }
1397
1398 /* Map in the BigMAC transceiver registers, this is how you poke at
1399 * the BigMAC's PHY.
1400 */
1401 bp->tregs = sparc_alloc_io(bp->bigmac_sbus_dev->reg_addrs[2].phys_addr,
1402 0,
1403 sizeof(struct bmac_tcvr),
1404 "BigMAC Transceiver Regs",
1405 bp->bigmac_sbus_dev->reg_addrs[2].which_io,
1406 0);
1407 if(!bp->tregs) {
1408 printk("BIGMAC: Cannot map BigMAC transceiver registers.\n");
1409 goto fail_and_cleanup;
1410 }
1411
1412 /* Stop the BigMAC. */
1413 bigmac_stop(bp);
1414
1415 /* Allocate transmit/receive descriptor DVMA block. */
1416 bp->bmac_block = (struct bmac_init_block *)
1417 sparc_dvma_malloc(PAGE_SIZE, "BigMAC Init Block",
1418 &bp->bblock_dvma);
1419
1420 /* Get the board revision of this BigMAC. */
1421 bp->board_rev = prom_getintdefault(bp->bigmac_sbus_dev->prom_node,
1422 "board-version", 1);
1423
1424 /* If on sun4c, we use a static buffer pool, on sun4m we DMA directly
1425 * in and out of sk_buffs instead for speed and one copy to userspace.
1426 */
1427 #ifndef __sparc_v9__
1428 if(sparc_cpu_model == sun4c)
1429 bp->sun4c_buffers = (struct bigmac_buffers *)
1430 sparc_dvma_malloc(sizeof(struct bigmac_buffers),
1431 "BigMAC Bufs",
1432 &bp->s4c_buf_dvma);
1433 else
1434 #endif
1435 bp->sun4c_buffers = 0;
1436
1437 /* Init auto-negotiation timer state. */
1438 init_timer(&bp->bigmac_timer);
1439 bp->timer_state = asleep;
1440 bp->timer_ticks = 0;
1441
1442 /* Backlink to generic net device struct. */
1443 bp->dev = dev;
1444
1445 /* Set links to our BigMAC open and close routines. */
1446 dev->open = &bigmac_open;
1447 dev->stop = &bigmac_close;
1448
1449 /* Choose transmit routine based upon buffering scheme. */
1450 #ifndef __sparc_v9__
1451 if(sparc_cpu_model == sun4c)
1452 dev->hard_start_xmit = &sun4c_bigmac_start_xmit;
1453 else
1454 #endif
1455 dev->hard_start_xmit = &bigmac_start_xmit;
1456
1457 /* Set links to BigMAC statistic and multi-cast loading code. */
1458 dev->get_stats = &bigmac_get_stats;
1459 dev->set_multicast_list = &bigmac_set_multicast;
1460
1461 /* Finish net device registration. */
1462 dev->irq = bp->bigmac_sbus_dev->irqs[0];
1463 dev->dma = 0;
1464 ether_setup(dev);
1465
1466 #ifdef MODULE
1467 /* Put us into the list of instances attached for later module unloading. */
1468 bp->next_module = root_bigmac_dev;
1469 root_bigmac_dev = bp;
1470 #endif
1471 return 0;
1472
1473 fail_and_cleanup:
1474 /* Something went wrong, undo whatever we did so far. */
1475 if(bp) {
1476 /* Free register mappings if any. */
1477 if(bp->gregs)
1478 sparc_free_io(bp->gregs, sizeof(struct qe_globreg));
1479 if(bp->creg)
1480 sparc_free_io(bp->creg, sizeof(struct qe_creg));
1481 if(bp->bregs)
1482 sparc_free_io(bp->bregs, sizeof(struct BIG_MAC_regs));
1483 if(bp->tregs)
1484 sparc_free_io(bp->tregs, sizeof(struct bmac_tcvr));
1485
1486 /* XXX todo, bmac_block and sun4c_buffers */
1487
1488 /* Free the BigMAC softc. */
1489 kfree(bp);
1490 dev->priv = 0;
1491 }
1492 return res; /* Return error code. */
1493 }
1494
1495 int __init bigmac_probe(struct net_device *dev)
1496 {
1497 struct linux_sbus *bus;
1498 struct linux_sbus_device *sdev = 0;
1499 static int called = 0;
1500 int cards = 0, v;
1501
1502 if(called)
1503 return ENODEV;
1504 called++;
1505
1506 for_each_sbus(bus) {
1507 for_each_sbusdev(sdev, bus) {
1508 if(cards) dev = NULL;
1509
1510 /* QEC can be the parent of either QuadEthernet or
1511 * a BigMAC. We want the latter.
1512 */
1513 if(!strcmp(sdev->prom_name, "qec") && sdev->child &&
1514 !strcmp(sdev->child->prom_name, "be")) {
1515 cards++;
1516 if((v = bigmac_ether_init(dev, sdev)))
1517 return v;
1518 }
1519 }
1520 }
1521 if(!cards)
1522 return ENODEV;
1523 return 0;
1524 }
1525
1526 #ifdef MODULE
1527
1528 int
1529 init_module(void)
1530 {
1531 root_bigmac_dev = NULL;
1532 return bigmac_probe(NULL);
1533 }
1534
1535 void
1536 cleanup_module(void)
1537 {
1538 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1539 while (root_bigmac_dev) {
1540 struct bigmac *bp = root_bigmac_dev;
1541 struct bigmac *bp_nxt = root_bigmac_dev->next_module;
1542
1543 sparc_free_io(bp->gregs, sizeof(struct qe_globreg));
1544 sparc_free_io(bp->creg, sizeof(struct qe_creg));
1545 sparc_free_io(bp->bregs, sizeof(struct BIG_MAC_regs));
1546 sparc_free_io(bp->tregs, sizeof(struct bmac_tcvr));
1547
1548 /* XXX todo, bmac_block and sun4c_buffers */
1549
1550 unregister_netdev(bp->dev);
1551 kfree(bp->dev);
1552 root_bigmac_dev = bp_nxt;
1553 }
1554 }
1555
1556 #endif /* MODULE */