i386/linux/linux-2.3.21/drivers/net/tlan.h

   1 #ifndef TLAN_H
   2 #define TLAN_H
   3 /********************************************************************
   4  *
   5  *  Linux ThunderLAN Driver
   6  *
   7  *  tlan.h
   8  *  by James Banks
   9  *
  10  *  (C) 1997-1998 Caldera, Inc.
  11  *
  12  *  This software may be used and distributed according to the terms
  13  *  of the GNU Public License, incorporated herein by reference.
  14  *
  15  ** This file is best viewed/edited with tabstop=4, colums>=132
  16  *
  17  ********************************************************************/
  18
  19
  20 #include <asm/io.h>
  21 #include <asm/types.h>
  22 #include <linux/netdevice.h>
  23
  24 #if LINUX_VERSION_CODE <= 0x20100
  25 #define net_device_stats        enet_statistics
  26 #endif
  27
  28
  29
  30
  31         /*****************************************************************
  32          * TLan Definitions
  33          *
  34          ****************************************************************/
  35
  36 #define FALSE                   0
  37 #define TRUE                    1
  38
  39 #define TLAN_MIN_FRAME_SIZE     64
  40 #define TLAN_MAX_FRAME_SIZE     1600
  41
  42 #define TLAN_NUM_RX_LISTS       4
  43 #define TLAN_NUM_TX_LISTS       8
  44
  45 #define TLAN_IGNORE             0
  46 #define TLAN_RECORD             1
  47
  48 #define TLAN_DBG(lvl, format, args...)  if (debug&lvl) printk( format, ##args );
  49 #define TLAN_DEBUG_GNRL         0x0001
  50 #define TLAN_DEBUG_TX           0x0002
  51 #define TLAN_DEBUG_RX           0x0004
  52 #define TLAN_DEBUG_LIST         0x0008
  53
  54
  55
  56
  57         /*****************************************************************
  58          * Device Identification Definitions
  59          *
  60          ****************************************************************/
  61
  62 #define PCI_DEVICE_ID_NETELLIGENT_10                    0xAE34
  63 #define PCI_DEVICE_ID_NETELLIGENT_10_100                0xAE32
  64 #define PCI_DEVICE_ID_NETFLEX_3P_INTEGRATED             0xAE35
  65 #define PCI_DEVICE_ID_NETFLEX_3P                        0xF130
  66 #define PCI_DEVICE_ID_NETFLEX_3P_BNC                    0xF150
  67 #define PCI_DEVICE_ID_NETELLIGENT_10_100_PROLIANT       0xAE43
  68 #define PCI_DEVICE_ID_NETELLIGENT_10_100_DUAL           0xAE40
  69 #define PCI_DEVICE_ID_DESKPRO_4000_5233MMX              0xB011
  70 #define PCI_DEVICE_ID_NETELLIGENT_10_T2                 0xB012
  71 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100        0xB030
  72 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
  73 #define PCI_DEVICE_ID_OLICOM_OC2183                     0x0013
  74 #endif
  75 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
  76 #define PCI_DEVICE_ID_OLICOM_OC2325                     0x0012
  77 #endif
  78 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
  79 #define PCI_DEVICE_ID_OLICOM_OC2326                     0x0014
  80 #endif
  81
  82 typedef struct tlan_adapter_entry {
  83         u16     vendorId;
  84         u16     deviceId;
  85         char    *deviceLabel;
  86         u32     flags;
  87         u16     addrOfs;
  88 } TLanAdapterEntry;
  89
  90 #define TLAN_ADAPTER_NONE               0x00000000
  91 #define TLAN_ADAPTER_UNMANAGED_PHY      0x00000001
  92 #define TLAN_ADAPTER_BIT_RATE_PHY       0x00000002
  93 #define TLAN_ADAPTER_USE_INTERN_10      0x00000004
  94 #define TLAN_ADAPTER_ACTIVITY_LED       0x00000008
  95
  96 #define TLAN_SPEED_DEFAULT      0
  97 #define TLAN_SPEED_10           10
  98 #define TLAN_SPEED_100          100
  99
 100 #define TLAN_DUPLEX_DEFAULT     0
 101 #define TLAN_DUPLEX_HALF        1
 102 #define TLAN_DUPLEX_FULL        2
 103
 104
 105
 106
 107         /*****************************************************************
 108          * Rx/Tx List Definitions
 109          *
 110          ****************************************************************/
 111
 112 #define TLAN_BUFFERS_PER_LIST   10
 113 #define TLAN_LAST_BUFFER        0x80000000
 114 #define TLAN_CSTAT_UNUSED       0x8000
 115 #define TLAN_CSTAT_FRM_CMP      0x4000
 116 #define TLAN_CSTAT_READY        0x3000
 117 #define TLAN_CSTAT_EOC          0x0800
 118 #define TLAN_CSTAT_RX_ERROR     0x0400
 119 #define TLAN_CSTAT_PASS_CRC     0x0200
 120 #define TLAN_CSTAT_DP_PR        0x0100
 121
 122
 123 typedef struct tlan_buffer_ref_tag {
 124         u32     count;
 125         u32     address;
 126 } TLanBufferRef;
 127
 128
 129 typedef struct tlan_list_tag {
 130         u32             forward;
 131         u16             cStat;
 132         u16             frameSize;
 133         TLanBufferRef   buffer[TLAN_BUFFERS_PER_LIST];
 134 } TLanList;
 135
 136
 137 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
 138
 139
 140
 141
 142         /*****************************************************************
 143          * PHY definitions
 144          *
 145          ****************************************************************/
 146
 147 #define TLAN_PHY_MAX_ADDR       0x1F
 148 #define TLAN_PHY_NONE           0x20
 149
 150
 151
 152
 153         /*****************************************************************
 154          * TLAN Private Information Structure
 155          *
 156          ****************************************************************/
 157
 158 typedef struct tlan_private_tag {
 159         struct net_device           *nextDevice;
 160         void                    *dmaStorage;
 161         u8                      *padBuffer;
 162         TLanList                *rxList;
 163         u8                      *rxBuffer;
 164         u32                     rxHead;
 165         u32                     rxTail;
 166         u32                     rxEocCount;
 167         TLanList                *txList;
 168         u8                      *txBuffer;
 169         u32                     txHead;
 170         u32                     txInProgress;
 171         u32                     txTail;
 172         u32                     txBusyCount;
 173         u32                     phyOnline;
 174         u32                     timerSetAt;
 175         u32                     timerType;
 176         struct timer_list       timer;
 177         struct net_device_stats stats;
 178         TLanAdapterEntry        *adapter;
 179         u32                     adapterRev;
 180         u32                     aui;
 181         u32                     debug;
 182         u32                     duplex;
 183         u32                     phy[2];
 184         u32                     phyNum;
 185         u32                     sa_int;
 186         u32                     speed;
 187         u8                      tlanRev;
 188         u8                      tlanFullDuplex;
 189         char                    devName[8];
 190 } TLanPrivateInfo;
 191
 192
 193
 194
 195         /*****************************************************************
 196          * TLan Driver Timer Definitions
 197          *
 198          ****************************************************************/
 199
 200 #define TLAN_TIMER_LINK                 1
 201 #define TLAN_TIMER_ACTIVITY             2
 202 #define TLAN_TIMER_PHY_PDOWN            3
 203 #define TLAN_TIMER_PHY_PUP              4
 204 #define TLAN_TIMER_PHY_RESET            5
 205 #define TLAN_TIMER_PHY_START_LINK       6
 206 #define TLAN_TIMER_PHY_FINISH_AN        7
 207 #define TLAN_TIMER_FINISH_RESET         8
 208
 209 #define TLAN_TIMER_ACT_DELAY            10
 210
 211
 212
 213
 214         /*****************************************************************
 215          * TLan Driver Eeprom Definitions
 216          *
 217          ****************************************************************/
 218
 219 #define TLAN_EEPROM_ACK         0
 220 #define TLAN_EEPROM_STOP        1
 221
 222
 223
 224
 225         /*****************************************************************
 226          * Host Register Offsets and Contents
 227          *
 228          ****************************************************************/
 229
 230 #define TLAN_HOST_CMD                   0x00
 231 #define         TLAN_HC_GO              0x80000000
 232 #define         TLAN_HC_STOP            0x40000000
 233 #define         TLAN_HC_ACK             0x20000000
 234 #define         TLAN_HC_CS_MASK         0x1FE00000
 235 #define         TLAN_HC_EOC             0x00100000
 236 #define         TLAN_HC_RT              0x00080000
 237 #define         TLAN_HC_NES             0x00040000
 238 #define         TLAN_HC_AD_RST          0x00008000
 239 #define         TLAN_HC_LD_TMR          0x00004000
 240 #define         TLAN_HC_LD_THR          0x00002000
 241 #define         TLAN_HC_REQ_INT         0x00001000
 242 #define         TLAN_HC_INT_OFF         0x00000800
 243 #define         TLAN_HC_INT_ON          0x00000400
 244 #define         TLAN_HC_AC_MASK         0x000000FF
 245 #define TLAN_CH_PARM                    0x04
 246 #define TLAN_DIO_ADR                    0x08
 247 #define         TLAN_DA_ADR_INC         0x8000
 248 #define         TLAN_DA_RAM_ADR         0x4000
 249 #define TLAN_HOST_INT                   0x0A
 250 #define         TLAN_HI_IV_MASK         0x1FE0
 251 #define         TLAN_HI_IT_MASK         0x001C
 252 #define TLAN_DIO_DATA                   0x0C
 253
 254
 255 /* ThunderLAN Internal Register DIO Offsets */
 256
 257 #define TLAN_NET_CMD                    0x00
 258 #define         TLAN_NET_CMD_NRESET     0x80
 259 #define         TLAN_NET_CMD_NWRAP      0x40
 260 #define         TLAN_NET_CMD_CSF        0x20
 261 #define         TLAN_NET_CMD_CAF        0x10
 262 #define         TLAN_NET_CMD_NOBRX      0x08
 263 #define         TLAN_NET_CMD_DUPLEX     0x04
 264 #define         TLAN_NET_CMD_TRFRAM     0x02
 265 #define         TLAN_NET_CMD_TXPACE     0x01
 266 #define TLAN_NET_SIO                    0x01
 267 #define         TLAN_NET_SIO_MINTEN     0x80
 268 #define         TLAN_NET_SIO_ECLOK      0x40
 269 #define         TLAN_NET_SIO_ETXEN      0x20
 270 #define         TLAN_NET_SIO_EDATA      0x10
 271 #define         TLAN_NET_SIO_NMRST      0x08
 272 #define         TLAN_NET_SIO_MCLK       0x04
 273 #define         TLAN_NET_SIO_MTXEN      0x02
 274 #define         TLAN_NET_SIO_MDATA      0x01
 275 #define TLAN_NET_STS                    0x02
 276 #define         TLAN_NET_STS_MIRQ       0x80
 277 #define         TLAN_NET_STS_HBEAT      0x40
 278 #define         TLAN_NET_STS_TXSTOP     0x20
 279 #define         TLAN_NET_STS_RXSTOP     0x10
 280 #define         TLAN_NET_STS_RSRVD      0x0F
 281 #define TLAN_NET_MASK                   0x03
 282 #define         TLAN_NET_MASK_MASK7     0x80
 283 #define         TLAN_NET_MASK_MASK6     0x40
 284 #define         TLAN_NET_MASK_MASK5     0x20
 285 #define         TLAN_NET_MASK_MASK4     0x10
 286 #define         TLAN_NET_MASK_RSRVD     0x0F
 287 #define TLAN_NET_CONFIG                 0x04
 288 #define         TLAN_NET_CFG_RCLK       0x8000
 289 #define         TLAN_NET_CFG_TCLK       0x4000
 290 #define         TLAN_NET_CFG_BIT        0x2000
 291 #define         TLAN_NET_CFG_RXCRC      0x1000
 292 #define         TLAN_NET_CFG_PEF        0x0800
 293 #define         TLAN_NET_CFG_1FRAG      0x0400
 294 #define         TLAN_NET_CFG_1CHAN      0x0200
 295 #define         TLAN_NET_CFG_MTEST      0x0100
 296 #define         TLAN_NET_CFG_PHY_EN     0x0080
 297 #define         TLAN_NET_CFG_MSMASK     0x007F
 298 #define TLAN_MAN_TEST                   0x06
 299 #define TLAN_DEF_VENDOR_ID              0x08
 300 #define TLAN_DEF_DEVICE_ID              0x0A
 301 #define TLAN_DEF_REVISION               0x0C
 302 #define TLAN_DEF_SUBCLASS               0x0D
 303 #define TLAN_DEF_MIN_LAT                0x0E
 304 #define TLAN_DEF_MAX_LAT                0x0F
 305 #define TLAN_AREG_0                     0x10
 306 #define TLAN_AREG_1                     0x16
 307 #define TLAN_AREG_2                     0x1C
 308 #define TLAN_AREG_3                     0x22
 309 #define TLAN_HASH_1                     0x28
 310 #define TLAN_HASH_2                     0x2C
 311 #define TLAN_GOOD_TX_FRMS               0x30
 312 #define TLAN_TX_UNDERUNS                0x33
 313 #define TLAN_GOOD_RX_FRMS               0x34
 314 #define TLAN_RX_OVERRUNS                0x37
 315 #define TLAN_DEFERRED_TX                0x38
 316 #define TLAN_CRC_ERRORS                 0x3A
 317 #define TLAN_CODE_ERRORS                0x3B
 318 #define TLAN_MULTICOL_FRMS              0x3C
 319 #define TLAN_SINGLECOL_FRMS             0x3E
 320 #define TLAN_EXCESSCOL_FRMS             0x40
 321 #define TLAN_LATE_COLS                  0x41
 322 #define TLAN_CARRIER_LOSS               0x42
 323 #define TLAN_ACOMMIT                    0x43
 324 #define TLAN_LED_REG                    0x44
 325 #define         TLAN_LED_ACT            0x10
 326 #define         TLAN_LED_LINK           0x01
 327 #define TLAN_BSIZE_REG                  0x45
 328 #define TLAN_MAX_RX                     0x46
 329 #define TLAN_INT_DIS                    0x48
 330 #define         TLAN_ID_TX_EOC          0x04
 331 #define         TLAN_ID_RX_EOF          0x02
 332 #define         TLAN_ID_RX_EOC          0x01
 333
 334
 335
 336 /* ThunderLAN Interrupt Codes */
 337
 338 #define TLAN_INT_NUMBER_OF_INTS 8
 339
 340 #define TLAN_INT_NONE                   0x0000
 341 #define TLAN_INT_TX_EOF                 0x0001
 342 #define TLAN_INT_STAT_OVERFLOW          0x0002
 343 #define TLAN_INT_RX_EOF                 0x0003
 344 #define TLAN_INT_DUMMY                  0x0004
 345 #define TLAN_INT_TX_EOC                 0x0005
 346 #define TLAN_INT_STATUS_CHECK           0x0006
 347 #define TLAN_INT_RX_EOC                 0x0007
 348
 349
 350
 351 /* ThunderLAN MII Registers */
 352
 353 /* Generic MII/PHY Registers */
 354
 355 #define MII_GEN_CTL                     0x00
 356 #define         MII_GC_RESET            0x8000
 357 #define         MII_GC_LOOPBK           0x4000
 358 #define         MII_GC_SPEEDSEL         0x2000
 359 #define         MII_GC_AUTOENB          0x1000
 360 #define         MII_GC_PDOWN            0x0800
 361 #define         MII_GC_ISOLATE          0x0400
 362 #define         MII_GC_AUTORSRT         0x0200
 363 #define         MII_GC_DUPLEX           0x0100
 364 #define         MII_GC_COLTEST          0x0080
 365 #define         MII_GC_RESERVED         0x007F
 366 #define MII_GEN_STS                     0x01
 367 #define         MII_GS_100BT4           0x8000
 368 #define         MII_GS_100BTXFD         0x4000
 369 #define         MII_GS_100BTXHD         0x2000
 370 #define         MII_GS_10BTFD           0x1000
 371 #define         MII_GS_10BTHD           0x0800
 372 #define         MII_GS_RESERVED         0x07C0
 373 #define         MII_GS_AUTOCMPLT        0x0020
 374 #define         MII_GS_RFLT             0x0010
 375 #define         MII_GS_AUTONEG          0x0008
 376 #define         MII_GS_LINK             0x0004
 377 #define         MII_GS_JABBER           0x0002
 378 #define         MII_GS_EXTCAP           0x0001
 379 #define MII_GEN_ID_HI                   0x02
 380 #define MII_GEN_ID_LO                   0x03
 381 #define         MII_GIL_OUI             0xFC00
 382 #define         MII_GIL_MODEL           0x03F0
 383 #define         MII_GIL_REVISION        0x000F
 384 #define MII_AN_ADV                      0x04
 385 #define MII_AN_LPA                      0x05
 386 #define MII_AN_EXP                      0x06
 387
 388 /* ThunderLAN Specific MII/PHY Registers */
 389
 390 #define TLAN_TLPHY_ID                   0x10
 391 #define TLAN_TLPHY_CTL                  0x11
 392 #define         TLAN_TC_IGLINK          0x8000
 393 #define         TLAN_TC_SWAPOL          0x4000
 394 #define         TLAN_TC_AUISEL          0x2000
 395 #define         TLAN_TC_SQEEN           0x1000
 396 #define         TLAN_TC_MTEST           0x0800
 397 #define         TLAN_TC_RESERVED        0x07F8
 398 #define         TLAN_TC_NFEW            0x0004
 399 #define         TLAN_TC_INTEN           0x0002
 400 #define         TLAN_TC_TINT            0x0001
 401 #define TLAN_TLPHY_STS                  0x12
 402 #define         TLAN_TS_MINT            0x8000
 403 #define         TLAN_TS_PHOK            0x4000
 404 #define         TLAN_TS_POLOK           0x2000
 405 #define         TLAN_TS_TPENERGY        0x1000
 406 #define         TLAN_TS_RESERVED        0x0FFF
 407
 408
 409 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
 410
 411 /* Routines to access internal registers. */
 412
 413 inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
 414 {
 415         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 416         return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
 417
 418 } /* TLan_DioRead8 */
 419
 420
 421
 422
 423 inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
 424 {
 425         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 426         return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
 427
 428 } /* TLan_DioRead16 */
 429
 430
 431
 432
 433 inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
 434 {
 435         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 436         return (inl(base_addr + TLAN_DIO_DATA));
 437
 438 } /* TLan_DioRead32 */
 439
 440
 441
 442
 443 inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
 444 {
 445         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 446         outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
 447
 448 }
 449
 450
 451
 452
 453 inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
 454 {
 455         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 456         outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
 457
 458 }
 459
 460
 461
 462
 463 inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
 464 {
 465         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 466         outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
 467
 468 }
 469
 470
 471
 472 #if 0
 473 inline void TLan_ClearBit(u8 bit, u16 port)
 474 {
 475         outb_p(inb_p(port) & ~bit, port);
 476 }
 477
 478
 479
 480
 481 inline int TLan_GetBit(u8 bit, u16 port)
 482 {
 483         return ((int) (inb_p(port) & bit));
 484 }
 485
 486
 487
 488
 489 inline void TLan_SetBit(u8 bit, u16 port)
 490 {
 491         outb_p(inb_p(port) | bit, port);
 492 }
 493 #endif
 494
 495 #define TLan_ClearBit( bit, port )      outb_p(inb_p(port) & ~bit, port)
 496 #define TLan_GetBit( bit, port )        ((int) (inb_p(port) & bit))
 497 #define TLan_SetBit( bit, port )        outb_p(inb_p(port) | bit, port)
 498
 499 #ifdef I_LIKE_A_FAST_HASH_FUNCTION
 500 /* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */
 501 /* the code below is about seven times as fast as the original code */
 502 inline u32 TLan_HashFunc( u8 *a )
 503 {
 504         u8     hash;
 505
 506         hash = (a[0]^a[3]);             /* & 077 */
 507         hash ^= ((a[0]^a[3])>>6);       /* & 003 */
 508         hash ^= ((a[1]^a[4])<<2);       /* & 074 */
 509         hash ^= ((a[1]^a[4])>>4);       /* & 017 */
 510         hash ^= ((a[2]^a[5])<<4);       /* & 060 */
 511         hash ^= ((a[2]^a[5])>>2);       /* & 077 */
 512
 513         return (hash & 077);
 514 }
 515
 516 #else /* original code */
 517
 518 inline  u32     xor( u32 a, u32 b )
 519 {
 520         return ( ( a && ! b ) || ( ! a && b ) );
 521 }
 522 #define XOR8( a, b, c, d, e, f, g, h )  xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
 523 #define DA( a, bit )                                    ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
 524
 525 inline u32 TLan_HashFunc( u8 *a )
 526 {
 527         u32     hash;
 528
 529         hash  = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), DA(a,36), DA(a,42) );
 530         hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), DA(a,37), DA(a,43) ) << 1;
 531         hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), DA(a,38), DA(a,44) ) << 2;
 532         hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), DA(a,39), DA(a,45) ) << 3;
 533         hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), DA(a,40), DA(a,46) ) << 4;
 534         hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), DA(a,41), DA(a,47) ) << 5;
 535
 536         return hash;
 537
 538 }
 539
 540 #endif /* I_LIKE_A_FAST_HASH_FUNCTION */
 541 #endif