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[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / scsi / 53c7,8xx.h
blob994577ab059fc738cc520df681ea4da8a9fa09fd
1 /*
2 * NCR 53c{7,8}0x0 driver, header file
3 *
4 * Sponsored by
5 * iX Multiuser Multitasking Magazine
6 * Hannover, Germany
7 * hm@ix.de
8 *
9 * Copyright 1993, 1994, 1995 Drew Eckhardt
10 * Visionary Computing
11 * (Unix and Linux consulting and custom programming)
12 * drew@PoohSticks.ORG
13 * +1 (303) 786-7975
14 *
15 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
16 *
17 * PRE-ALPHA
18 *
19 * For more information, please consult
20 *
21 * NCR 53C700/53C700-66
22 * SCSI I/O Processor
23 * Data Manual
24 *
25 * NCR 53C810
26 * PCI-SCSI I/O Processor
27 * Data Manual
28 *
29 * NCR Microelectronics
30 * 1635 Aeroplaza Drive
31 * Colorado Springs, CO 80916
32 * +1 (719) 578-3400
33 *
34 * Toll free literature number
35 * +1 (800) 334-5454
36 *
37 */
38
39 #ifndef NCR53c7x0_H
40 #define NCR53c7x0_H
41 #if !defined(LINUX_1_2) && !defined(LINUX_1_3)
42 #include <linux/version.h>
43 #if LINUX_VERSION_CODE > 65536 + 3 * 256
44 #define LINUX_1_3
45 #else
46 #define LINUX_1_2
47 #endif
48 #endif
49
50 /*
51 * Prevent name space pollution in hosts.c, and only provide the
52 * define we need to get the NCR53c7x0 driver into the host template
53 * array.
54 */
55
56 #if defined(HOSTS_C) || defined(MODULE)
57 #include <scsi/scsicam.h>
58
59 extern int NCR53c7xx_abort(Scsi_Cmnd *);
60 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
61 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
62 extern int NCR53c7xx_reset(Scsi_Cmnd *, unsigned int);
63 #ifdef MODULE
64 extern int NCR53c7xx_release(struct Scsi_Host *);
65 #else
66 #define NCR53c7xx_release NULL
67 #endif
68
69 #define NCR53c7xx { \
70 name: "NCR53c{7,8}xx (rel 17)", \
71 detect: NCR53c7xx_detect, \
72 queuecommand: NCR53c7xx_queue_command, \
73 abort: NCR53c7xx_abort, \
74 reset: NCR53c7xx_reset, \
75 bios_param: scsicam_bios_param, \
76 can_queue: 24, \
77 this_id: 7, \
78 sg_tablesize: 127, \
79 cmd_per_lun: 3, \
80 use_clustering: DISABLE_CLUSTERING}
81
82 #endif /* defined(HOSTS_C) || defined(MODULE) */
83
84 #ifndef HOSTS_C
85
86 /* Register addresses, ordered numerically */
87
88 /* SCSI control 0 rw, default = 0xc0 */
89 #define SCNTL0_REG 0x00
90 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
91 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
92 #define SCNTL0_STRT 0x20 /* Start Sequence */
93 #define SCNTL0_WATN 0x10 /* Select with ATN */
94 #define SCNTL0_EPC 0x08 /* Enable parity checking */
95 /* Bit 2 is reserved on 800 series chips */
96 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
97 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
98 #define SCNTL0_TRG 0x01 /* Target mode */
99
100 /* SCSI control 1 rw, default = 0x00 */
101
102 #define SCNTL1_REG 0x01
103 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
104 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
105 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
106 and reselection */
107 #define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
108 target mode only */
109 #define SCNTL1_CON 0x10 /* Connected */
110 #define SCNTL1_RST 0x08 /* SCSI RST/ */
111 #define SCNTL1_AESP 0x04 /* Force bad parity */
112 #define SCNTL1_SND_700 0x02 /* Start SCSI send */
113 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
114 arbitration immediately after
115 busfree is detected */
116 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
117 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
118
119 /* SCSI control 2 rw, */
120
121 #define SCNTL2_REG_800 0x02
122 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
123
124 /* SCSI control 3 rw */
125
126 #define SCNTL3_REG_800 0x03
127 #define SCNTL3_800_SCF_SHIFT 4
128 #define SCNTL3_800_SCF_MASK 0x70
129 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
130 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
131 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
132 /* 0x20 = SCLK/1.5
133 0x30 = SCLK/2
134 0x40 = SCLK/3 */
135
136 #define SCNTL3_800_CCF_SHIFT 0
137 #define SCNTL3_800_CCF_MASK 0x07
138 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
139 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
140 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
141 0x03 37.51 - 50
142 0x04 50.01 - 66 */
143
144 /*
145 * SCSI destination ID rw - the appropriate bit is set for the selected
146 * target ID. This is written by the SCSI SCRIPTS processor.
147 * default = 0x00
148 */
149 #define SDID_REG_700 0x02
150 #define SDID_REG_800 0x06
151
152 #define GP_REG_800 0x07 /* General purpose IO */
153 #define GP_800_IO1 0x02
154 #define GP_800_IO2 0x01
155
156
157 /* SCSI interrupt enable rw, default = 0x00 */
158 #define SIEN_REG_700 0x03
159 #define SIEN0_REG_800 0x40
160 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
161 #define SIEN_FC 0x40 /* Function complete */
162 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
163 #define SIEN_800_SEL 0x20 /* Selected */
164 #define SIEN_700_SEL 0x10 /* Selected or reselected */
165 #define SIEN_800_RESEL 0x10 /* Reselected */
166 #define SIEN_SGE 0x08 /* SCSI gross error */
167 #define SIEN_UDC 0x04 /* Unexpected disconnect */
168 #define SIEN_RST 0x02 /* SCSI RST/ received */
169 #define SIEN_PAR 0x01 /* Parity error */
170
171 /*
172 * SCSI chip ID rw
173 * NCR53c700 :
174 * When arbitrating, the highest bit is used, when reselection or selection
175 * occurs, the chip responds to all IDs for which a bit is set.
176 * default = 0x00
177 * NCR53c810 :
178 * Uses bit mapping
179 */
180 #define SCID_REG 0x04
181 /* Bit 7 is reserved on 800 series chips */
182 #define SCID_800_RRE 0x40 /* Enable response to reselection */
183 #define SCID_800_SRE 0x20 /* Enable response to selection */
184 /* Bits four and three are reserved on 800 series chips */
185 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
186
187 /* SCSI transfer rw, default = 0x00 */
188 #define SXFER_REG 0x05
189 #define SXFER_DHP 0x80 /* Disable halt on parity */
190
191 #define SXFER_TP2 0x40 /* Transfer period msb */
192 #define SXFER_TP1 0x20
193 #define SXFER_TP0 0x10 /* lsb */
194 #define SXFER_TP_MASK 0x70
195 /* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
196 #define SXFER_TP_SHIFT 5
197 #define SXFER_TP_4 0x00 /* Divisors */
198 #define SXFER_TP_5 0x10<<1
199 #define SXFER_TP_6 0x20<<1
200 #define SXFER_TP_7 0x30<<1
201 #define SXFER_TP_8 0x40<<1
202 #define SXFER_TP_9 0x50<<1
203 #define SXFER_TP_10 0x60<<1
204 #define SXFER_TP_11 0x70<<1
205
206 #define SXFER_MO3 0x08 /* Max offset msb */
207 #define SXFER_MO2 0x04
208 #define SXFER_MO1 0x02
209 #define SXFER_MO0 0x01 /* lsb */
210 #define SXFER_MO_MASK 0x0f
211 #define SXFER_MO_SHIFT 0
212
213 /*
214 * SCSI output data latch rw
215 * The contents of this register are driven onto the SCSI bus when
216 * the Assert Data Bus bit of the SCNTL1 register is set and
217 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
218 */
219 #define SODL_REG_700 0x06
220 #define SODL_REG_800 0x54
221
222
223 /*
224 * SCSI output control latch rw, default = 0
225 * Note that when the chip is being manually programmed as an initiator,
226 * the MSG, CD, and IO bits must be set correctly for the phase the target
227 * is driving the bus in. Otherwise no data transfer will occur due to
228 * phase mismatch.
229 */
230
231 #define SBCL_REG 0x0b
232 #define SBCL_REQ 0x80 /* REQ */
233 #define SBCL_ACK 0x40 /* ACK */
234 #define SBCL_BSY 0x20 /* BSY */
235 #define SBCL_SEL 0x10 /* SEL */
236 #define SBCL_ATN 0x08 /* ATN */
237 #define SBCL_MSG 0x04 /* MSG */
238 #define SBCL_CD 0x02 /* C/D */
239 #define SBCL_IO 0x01 /* I/O */
240 #define SBCL_PHASE_CMDOUT SBCL_CD
241 #define SBCL_PHASE_DATAIN SBCL_IO
242 #define SBCL_PHASE_DATAOUT 0
243 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
244 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
245 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
246 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
247
248 /*
249 * SCSI first byte received latch ro
250 * This register contains the first byte received during a block MOVE
251 * SCSI SCRIPTS instruction, including
252 *
253 * Initiator mode Target mode
254 * Message in Command
255 * Status Message out
256 * Data in Data out
257 *
258 * It also contains the selecting or reselecting device's ID and our
259 * ID.
260 *
261 * Note that this is the register the various IF conditionals can
262 * operate on.
263 */
264 #define SFBR_REG 0x08
265
266 /*
267 * SCSI input data latch ro
268 * In initiator mode, data is latched into this register on the rising
269 * edge of REQ/. In target mode, data is latched on the rising edge of
270 * ACK/
271 */
272 #define SIDL_REG_700 0x09
273 #define SIDL_REG_800 0x50
274
275 /*
276 * SCSI bus data lines ro
277 * This register reflects the instantaneous status of the SCSI data
278 * lines. Note that SCNTL0 must be set to disable parity checking,
279 * otherwise reading this register will latch new parity.
280 */
281 #define SBDL_REG_700 0x0a
282 #define SBDL_REG_800 0x58
283
284 #define SSID_REG_800 0x0a
285 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
286 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
287
288
289 /*
290 * SCSI bus control lines rw,
291 * instantaneous readout of control lines
292 */
293 #define SOCL_REG 0x0b
294 #define SOCL_REQ 0x80 /* REQ ro */
295 #define SOCL_ACK 0x40 /* ACK ro */
296 #define SOCL_BSY 0x20 /* BSY ro */
297 #define SOCL_SEL 0x10 /* SEL ro */
298 #define SOCL_ATN 0x08 /* ATN ro */
299 #define SOCL_MSG 0x04 /* MSG ro */
300 #define SOCL_CD 0x02 /* C/D ro */
301 #define SOCL_IO 0x01 /* I/O ro */
302 /*
303 * Synchronous SCSI Clock Control bits
304 * 0 - set by DCNTL
305 * 1 - SCLK / 1.0
306 * 2 - SCLK / 1.5
307 * 3 - SCLK / 2.0
308 */
309 #define SBCL_SSCF1 0x02 /* wo, -66 only */
310 #define SBCL_SSCF0 0x01 /* wo, -66 only */
311 #define SBCL_SSCF_MASK 0x03
312
313 /*
314 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
315 * insure that 10 clocks elapse between the two
316 */
317 /* DMA status ro */
318 #define DSTAT_REG 0x0c
319 #define DSTAT_DFE 0x80 /* DMA FIFO empty */
320 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
321 #define DSTAT_800_BF 0x20 /* Bus Fault */
322 #define DSTAT_ABRT 0x10 /* Aborted - set on error */
323 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
324 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
325 set when INT instruction is
326 executed */
327 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
328 #define DSTAT_OPC 0x01 /* Illegal instruction */
329 #define DSTAT_800_IID 0x01 /* Same thing, different name */
330
331
332 /* NCR53c800 moves this stuff into SIST0 */
333 #define SSTAT0_REG 0x0d /* SCSI status 0 ro */
334 #define SIST0_REG_800 0x42
335 #define SSTAT0_MA 0x80 /* ini : phase mismatch,
336 * tgt : ATN/ asserted
337 */
338 #define SSTAT0_CMP 0x40 /* function complete */
339 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
340 #define SIST0_800_SEL 0x20 /* Selected */
341 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
342 #define SIST0_800_RSL 0x10 /* Reselected */
343 #define SSTAT0_SGE 0x08 /* SCSI gross error */
344 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
345 #define SSTAT0_RST 0x02 /* SCSI RST/ received */
346 #define SSTAT0_PAR 0x01 /* Parity error */
347
348 /* And uses SSTAT0 for what was SSTAT1 */
349
350 #define SSTAT1_REG 0x0e /* SCSI status 1 ro */
351 #define SSTAT1_ILF 0x80 /* SIDL full */
352 #define SSTAT1_ORF 0x40 /* SODR full */
353 #define SSTAT1_OLF 0x20 /* SODL full */
354 #define SSTAT1_AIP 0x10 /* Arbitration in progress */
355 #define SSTAT1_LOA 0x08 /* Lost arbitration */
356 #define SSTAT1_WOA 0x04 /* Won arbitration */
357 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
358 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
359
360 #define SSTAT2_REG 0x0f /* SCSI status 2 ro */
361 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
362 #define SSTAT2_FF2 0x40 /* data FIFO */
363 #define SSTAT2_FF1 0x20
364 #define SSTAT2_FF0 0x10
365 #define SSTAT2_FF_MASK 0xf0
366 #define SSTAT2_FF_SHIFT 4
367
368 /*
369 * Latched signals, latched on the leading edge of REQ/ for initiators,
370 * ACK/ for targets.
371 */
372 #define SSTAT2_SDP 0x08 /* SDP */
373 #define SSTAT2_MSG 0x04 /* MSG */
374 #define SSTAT2_CD 0x02 /* C/D */
375 #define SSTAT2_IO 0x01 /* I/O */
376 #define SSTAT2_PHASE_CMDOUT SSTAT2_CD
377 #define SSTAT2_PHASE_DATAIN SSTAT2_IO
378 #define SSTAT2_PHASE_DATAOUT 0
379 #define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
380 #define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG)
381 #define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO)
382 #define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
383
384
385 /* NCR53c700-66 only */
386 #define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
387 /* NCR53c710 and higher */
388 #define DSA_REG 0x10 /* DATA structure address */
389
390 #define CTEST0_REG_700 0x14 /* Chip test 0 ro */
391 #define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
392 /* 0x80 - 0x04 are reserved */
393 #define CTEST0_700_RTRG 0x02 /* Real target mode */
394 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
395 * SCSI bus to host, 0 =
396 * host to SCSI.
397 */
398
399 #define CTEST1_REG_700 0x15 /* Chip test 1 ro */
400 #define CTEST1_REG_800 0x19 /* Chip test 1 ro */
401 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
402 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
403 #define CTEST1_FMT1 0x20
404 #define CTEST1_FMT0 0x10
405
406 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
407 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
408 #define CTEST1_FFL1 0x02
409 #define CTEST1_FFL0 0x01
410
411 #define CTEST2_REG_700 0x16 /* Chip test 2 ro */
412 #define CTEST2_REG_800 0x1a /* Chip test 2 ro */
413
414 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
415 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
416 Reading this register clears */
417 #define CTEST2_800_CIO 0x20 /* Configured as IO */.
418 #define CTEST2_800_CM 0x10 /* Configured as memory */
419
420 /* 0x80 - 0x40 are reserved on 700 series chips */
421 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
422 * As an initiator, this bit is
423 * one when the synchronous offset
424 * is zero, as a target this bit
425 * is one when the synchronous
426 * offset is at the maximum
427 * defined in SXFER
428 */
429 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
430 * reading CTEST3 unloads a byte
431 * from the FIFO and sets this
432 */
433 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
434 * reading CTEST6 unloads a byte
435 * from the FIFO and sets this
436 */
437 #define CTEST2_TEOP 0x04 /* SCSI true end of process,
438 * indicates a totally finished
439 * transfer
440 */
441 #define CTEST2_DREQ 0x02 /* Data request signal */
442 /* 0x01 is reserved on 700 series chips */
443 #define CTEST2_800_DACK 0x01
444
445 /*
446 * Chip test 3 ro
447 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
448 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
449 * error results if a read is attempted on this register. Also note
450 * that 16 and 32 bit reads of this register will cause corruption.
451 */
452 #define CTEST3_REG_700 0x17
453 /* Chip test 3 rw */
454 #define CTEST3_REG_800 0x1b
455 #define CTEST3_800_V3 0x80 /* Chip revision */
456 #define CTEST3_800_V2 0x40
457 #define CTEST3_800_V1 0x20
458 #define CTEST3_800_V0 0x10
459 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
460 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
461 #define CTEST3_800_FM 0x02 /* Fetch mode pin */
462 /* bit 0 is reserved on 800 series chips */
463
464 #define CTEST4_REG_700 0x18 /* Chip test 4 rw */
465 #define CTEST4_REG_800 0x21 /* Chip test 4 rw */
466 /* 0x80 is reserved on 700 series chips */
467 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
468 #define CTEST4_ZMOD 0x40 /* High impedance mode */
469 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
470 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
471 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
472 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
473 * redirects writes from SODL
474 * to the SCSI FIFO.
475 */
476 #define CTEST4_800_MPEE 0x08 /* Enable parity checking
477 during master cycles on PCI
478 bus */
479
480 /*
481 * These bits send the contents of the CTEST6 register to the appropriate
482 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
483 * the high bit means the low two bits select the byte lane.
484 */
485 #define CTEST4_FBL2 0x04
486 #define CTEST4_FBL1 0x02
487 #define CTEST4_FBL0 0x01
488 #define CTEST4_FBL_MASK 0x07
489 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
490 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
491 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
492 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
493 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
494
495
496 #define CTEST5_REG_700 0x19 /* Chip test 5 rw */
497 #define CTEST5_REG_800 0x22 /* Chip test 5 rw */
498 /*
499 * Clock Address Incrementor. When set, it increments the
500 * DNAD register to the next bus size boundary. It automatically
501 * resets itself when the operation is complete.
502 */
503 #define CTEST5_ADCK 0x80
504 /*
505 * Clock Byte Counter. When set, it decrements the DBC register to
506 * the next bus size boundary.
507 */
508 #define CTEST5_BBCK 0x40
509 /*
510 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
511 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
512 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
513 * be cleared when a synchronous transfer fails. When written, it is
514 * automatically cleared after the SCSI synchronous offset counter is
515 * reset.
516 */
517 /* Bit 5 is reserved on 800 series chips */
518 #define CTEST5_700_ROFF 0x20
519 /*
520 * Master Control for Set or Reset pulses. When 1, causes the low
521 * four bits of register to set when set, 0 causes the low bits to
522 * clear when set.
523 */
524 #define CTEST5_MASR 0x10
525 #define CTEST5_DDIR 0x08 /* DMA direction */
526 /*
527 * Bits 2-0 are reserved on 800 series chips
528 */
529 #define CTEST5_700_EOP 0x04 /* End of process */
530 #define CTEST5_700_DREQ 0x02 /* Data request */
531 #define CTEST5_700_DACK 0x01 /* Data acknowledge */
532
533 /*
534 * Chip test 6 rw - writing to this register writes to the byte
535 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
536 * register.
537 */
538 #define CTEST6_REG_700 0x1a
539 #define CTEST6_REG_800 0x23
540
541 #define CTEST7_REG 0x1b /* Chip test 7 rw */
542 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
543 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
544 #define CTEST7_10_SC1 0x40 /* Snoop control bits */
545 #define CTEST7_10_SC0 0x20
546 #define CTEST7_10_SC_MASK 0x60
547 /* 0x20 is reserved on the NCR53c700 */
548 #define CTEST7_0060_FM 0x20 /* Fetch mode */
549 #define CTEST7_STD 0x10 /* Selection timeout disable */
550 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
551 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
552 #define CTEST7_10_TT1 0x02 /* Transfer type */
553 #define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
554 fetch */
555 #define CTEST7_DIFF 0x01 /* Differential mode */
556
557 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
558
559
560 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
561
562 #define DFIFO_REG 0x20 /* DMA FIFO rw */
563 /*
564 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
565 * moved into the CTEST8 register.
566 */
567 #define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
568 #define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
569 #define DFIFO_BO6 0x40
570 #define DFIFO_BO5 0x20
571 #define DFIFO_BO4 0x10
572 #define DFIFO_BO3 0x08
573 #define DFIFO_BO2 0x04
574 #define DFIFO_BO1 0x02
575 #define DFIFO_BO0 0x01
576 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
577 #define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
578
579 /*
580 * Interrupt status rw
581 * Note that this is the only register which can be read while SCSI
582 * SCRIPTS are being executed.
583 */
584 #define ISTAT_REG_700 0x21
585 #define ISTAT_REG_800 0x14
586 #define ISTAT_ABRT 0x80 /* Software abort, write
587 *1 to abort, wait for interrupt. */
588 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
589 #define ISTAT_10_SRST 0x40 /* software reset */
590 #define ISTAT_10_SIGP 0x20 /* signal script */
591 /* 0x10 is reserved on NCR53c700 series chips */
592 #define ISTAT_800_SEM 0x10 /* semaphore */
593 #define ISTAT_CON 0x08 /* 1 when connected */
594 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
595 #define ISTAT_700_PRE 0x04 /* Pointer register empty.
596 * Set to 1 when DSPS and DSP
597 * registers are empty in pipeline
598 * mode, always set otherwise.
599 */
600 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
601 * SCSI portion of SIOP see
602 * SSTAT0
603 */
604 #define ISTAT_DIP 0x01 /* DMA interrupt pending
605 * see DSTAT
606 */
607
608 /* NCR53c700-66 and NCR53c710 only */
609 #define CTEST8_REG 0x22 /* Chip test 8 rw */
610 #define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
611 * ie read from SCLK/ rather than CLK/
612 */
613 #define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
614 #define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
615 * pass through. This insures that
616 * bad parity won't reach the host
617 * bus.
618 */
619 #define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
620 * active negation, should only
621 * be used for slow SCSI
622 * non-differential.
623 */
624 #define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
625 #define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
626 * must be set for fast SCSI-II
627 * speeds.
628 */
629 #define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
630 * switching.
631 */
632 #define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
633 * The status of pending
634 * disconnect is maintained by
635 * the core, eliminating
636 * the possibility of missing a
637 * selection or reselection
638 * while waiting to fetch a
639 * WAIT DISCONNECT opcode.
640 */
641
642 #define CTEST8_10_V3 0x80 /* Chip revision */
643 #define CTEST8_10_V2 0x40
644 #define CTEST8_10_V1 0x20
645 #define CTEST8_10_V0 0x10
646 #define CTEST8_10_V_MASK 0xf0
647 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
648 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
649 #define CTEST8_10_FM 0x02 /* Fetch pin mode */
650 #define CTEST8_10_SM 0x01 /* Snoop pin mode */
651
652
653 /*
654 * The CTEST9 register may be used to differentiate between a
655 * NCR53c700 and a NCR53c710.
656 *
657 * Write 0xff to this register.
658 * Read it.
659 * If the contents are 0xff, it is a NCR53c700
660 * If the contents are 0x00, it is a NCR53c700-66 first revision
661 * If the contents are some other value, it is some other NCR53c700-66
662 */
663 #define CTEST9_REG_00 0x23 /* Chip test 9 ro */
664 #define LCRC_REG_10 0x23
665
666 /*
667 * 0x24 through 0x27 are the DMA byte counter register. Instructions
668 * write their high 8 bits into the DCMD register, the low 24 bits into
669 * the DBC register.
670 *
671 * Function is dependent on the command type being executed.
672 */
673
674
675 #define DBC_REG 0x24
676 /*
677 * For Block Move Instructions, DBC is a 24 bit quantity representing
678 * the number of bytes to transfer.
679 * For Transfer Control Instructions, DBC is bit fielded as follows :
680 */
681 /* Bits 20 - 23 should be clear */
682 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
683 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
684 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
685 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
686 /* Bits 8 - 15 are reserved on some implementations ? */
687 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
688 #define DBC_TCI_MASK_SHIFT 8
689 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
690 #define DBC_TCI_DATA_SHIFT 0
691
692 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
693 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
694 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
695 #define DBC_RWRI_ADDRESS_SHIFT 16
696
697
698 /*
699 * DMA command r/w
700 */
701 #define DCMD_REG 0x27
702 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
703 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
704 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
705 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
706 #define DCMD_BMI_MSG 0x04 /* instruction */
707
708 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
709 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
710 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
711
712 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
713
714 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
715 instruction */
716 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
717 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
718 #define DCMD_TCI_MSG 0x04 /* instruction */
719 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
720 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
721 #define DCMD_TCI_OP_CALL 0x08 /* CALL */
722 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
723 #define DCMD_TCI_OP_INT 0x18 /* INT */
724
725 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
726 instruction */
727 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
728 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
729 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
730 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
731
732 #define DCMD_RWRI_OP_MASK 0x07
733 #define DCMD_RWRI_OP_MOVE 0x00
734 #define DCMD_RWRI_OP_SHL 0x01
735 #define DCMD_RWRI_OP_OR 0x02
736 #define DCMD_RWRI_OP_XOR 0x03
737 #define DCMD_RWRI_OP_AND 0x04
738 #define DCMD_RWRI_OP_SHR 0x05
739 #define DCMD_RWRI_OP_ADD 0x06
740 #define DCMD_RWRI_OP_ADDC 0x07
741
742 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
743 (three words) */
744
745
746 #define DNAD_REG 0x28 /* through 0x2b DMA next address for
747 data */
748 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
749 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
750 save rw */
751 #define DMODE_REG_00 0x34 /* DMA mode rw */
752 #define DMODE_00_BL1 0x80 /* Burst length bits */
753 #define DMODE_00_BL0 0x40
754 #define DMODE_BL_MASK 0xc0
755 /* Burst lengths (800) */
756 #define DMODE_BL_2 0x00 /* 2 transfer */
757 #define DMODE_BL_4 0x40 /* 4 transfers */
758 #define DMODE_BL_8 0x80 /* 8 transfers */
759 #define DMODE_BL_16 0xc0 /* 16 transfers */
760
761 #define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
762 #define DMODE_700_286 0x10 /* 286 mode */
763 #define DMODE_700_IOM 0x08 /* Transfer to IO port */
764 #define DMODE_700_FAM 0x04 /* Fixed address mode */
765 #define DMODE_700_PIPE 0x02 /* Pipeline mode disables
766 * automatic fetch / exec
767 */
768 #define DMODE_MAN 0x01 /* Manual start mode,
769 * requires a 1 to be written
770 * to the start DMA bit in the DCNTL
771 * register to run scripts
772 */
773
774 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
775
776 /* NCR53c800 series only */
777 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
778 /* NCR53c710 only */
779 #define SCRATCB_REG_10 0x34 /* through 0x37 scratch B rw */
780
781 #define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
782 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
783 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
784 #define DMODE_800_ERL 0x08 /* Enable Read Line */
785
786 /* 35-38 are reserved on 700 and 700-66 series chips */
787 #define DIEN_REG 0x39 /* DMA interrupt enable rw */
788 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
789 #define DIEN_800_MDPE 0x40 /* Master data parity error */
790 #define DIEN_800_BF 0x20 /* BUS fault */
791 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
792 #define DIEN_SSI 0x08 /* Enable single step interrupt */
793 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
794 * interrupt
795 */
796 /* 0x02 is reserved on 800 series chips */
797 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
798 #define DIEN_700_OPC 0x01 /* Enable illegal instruction
799 * interrupt
800 */
801 #define DIEN_800_IID 0x01 /* Same meaning, different name */
802
803 /*
804 * DMA watchdog timer rw
805 * set in 16 CLK input periods.
806 */
807 #define DWT_REG 0x3a
808
809 /* DMA control rw */
810 #define DCNTL_REG 0x3b
811 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
812 #define DCNTL_700_CF0 0x40
813 #define DCNTL_700_CF_MASK 0xc0
814 /* Clock divisors Divisor SCLK range (MHZ) */
815 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
816 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
817 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
818 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
819
820 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
821 #define DCNTL_SSM 0x10 /* Single step mode */
822 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
823 * after selection */
824 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
825 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
826 /* 0x02 is reserved */
827 #define DCNTL_00_RST 0x01 /* Software reset, resets everything
828 * but 286 mode bit in DMODE. On the
829 * NCR53c710, this bit moved to CTEST8
830 */
831 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
832
833 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
834
835
836 /* NCR53c700-66 only */
837 #define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
838 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
839 /* NCR53c710 only */
840 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
841
842 #define SIEN1_REG_800 0x41
843 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
844 #define SIEN1_800_GEN 0x02 /* general purpose timer */
845 #define SIEN1_800_HTH 0x01 /* handshake to handshake */
846
847 #define SIST1_REG_800 0x43
848 #define SIST1_800_STO 0x04 /* selection/reselection timeout */
849 #define SIST1_800_GEN 0x02 /* general purpose timer */
850 #define SIST1_800_HTH 0x01 /* handshake to handshake */
851
852 #define SLPAR_REG_800 0x44 /* Parity */
853
854 #define MACNTL_REG_800 0x46 /* Memory access control */
855 #define MACNTL_800_TYP3 0x80
856 #define MACNTL_800_TYP2 0x40
857 #define MACNTL_800_TYP1 0x20
858 #define MACNTL_800_TYP0 0x10
859 #define MACNTL_800_DWR 0x08
860 #define MACNTL_800_DRD 0x04
861 #define MACNTL_800_PSCPT 0x02
862 #define MACNTL_800_SCPTS 0x01
863
864 #define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
865
866 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
867 #define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
868 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
869 #define STIME0_800_HTH_SHIFT 4
870 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
871 #define STIME0_800_SEL_SHIFT 0
872
873 #define STIME1_REG_800 0x49
874 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
875
876 #define RESPID_REG_800 0x4a /* Response ID, bit fielded. 8
877 bits on narrow chips, 16 on WIDE */
878
879 #define STEST0_REG_800 0x4c
880 #define STEST0_800_SLT 0x08 /* Selection response logic test */
881 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
882 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
883 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
884
885 #define STEST1_REG_800 0x4d
886 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
887
888 #define STEST2_REG_800 0x4e
889 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
890 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
891 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
892 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
893 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
894 #define STEST2_800_LOW 0x01 /* SCSI low level mode */
895
896 #define STEST3_REG_800 0x4f
897 #define STEST3_800_TE 0x80 /* Enable active negation */
898 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
899 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
900 #define STEST3_800_DSI 0x10 /* Disable single initiator response */
901 #define STEST3_800_TTM 0x04 /* Time test mode */
902 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
903 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
904
905 #define OPTION_PARITY 0x1 /* Enable parity checking */
906 #define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
907 #define OPTION_700 0x8 /* Always run NCR53c700 scripts */
908 #define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
909 #define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
910 #define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
911 simple test code, return
912 DID_NO_CONNECT if any SCSI
913 commands are attempted. */
914 #define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
915 SCSI write is attempted */
916 #define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
917 each address and instruction
918 executed to debug buffer. */
919 #define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
920 instruction */
921 #define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
922 #define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
923 memory mapping */
924 #define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
925 I/O mapping */
926 #define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
927 #define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
928 #define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
929 #define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
930 #define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
931 #define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
932 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
933 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
934 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
935 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
936 #define OPTION_DEBUG_DSA 0x800000
937 #define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
938 #define OPTION_DEBUG_SDTR 0x2000000 /* Debug SDTR problem */
939 #define OPTION_DEBUG_MISMATCH 0x4000000 /* Debug phase mismatches */
940 #define OPTION_DISCONNECT 0x8000000 /* Allow disconnect */
941 #define OPTION_DEBUG_DISCONNECT 0x10000000
942 #define OPTION_ALWAYS_SYNCHRONOUS 0x20000000 /* Negotiate sync. transfers
943 on power up */
944 #define OPTION_DEBUG_QUEUES 0x80000000
945 #define OPTION_DEBUG_ALLOCATION 0x100000000LL
946 #define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL /* Sanity check SXFER and
947 SCNTL3 registers */
948 #define OPTION_NO_ASYNC 0x400000000LL /* Don't automagically send
949 SDTR for async transfers when
950 we haven't been told to do
951 a synchronous transfer. */
952 #define OPTION_NO_PRINT_RACE 0x800000000LL /* Don't print message when
953 the reselect/WAIT DISCONNECT
954 race condition hits */
955 #if !defined(PERM_OPTIONS)
956 #define PERM_OPTIONS 0
957 #endif
958
959 struct NCR53c7x0_synchronous {
960 u32 select_indirect; /* Value used for indirect selection */
961 u32 script[8]; /* Size ?? Script used when target is
962 reselected */
963 unsigned char synchronous_want[5]; /* Per target desired SDTR */
964 /*
965 * Set_synchronous programs these, select_indirect and current settings after
966 * int_debug_should show a match.
967 */
968 unsigned char sxfer_sanity, scntl3_sanity;
969 };
970
971 #define CMD_FLAG_SDTR 1 /* Initiating synchronous
972 transfer negotiation */
973 #define CMD_FLAG_WDTR 2 /* Initiating wide transfer
974 negotiation */
975 #define CMD_FLAG_DID_SDTR 4 /* did SDTR */
976 #define CMD_FLAG_DID_WDTR 8 /* did WDTR */
977
978 struct NCR53c7x0_table_indirect {
979 u32 count;
980 void *address;
981 };
982
983 enum ncr_event {
984 EVENT_NONE = 0,
985 /*
986 * Order is IMPORTANT, since these must correspond to the event interrupts
987 * in 53c7,8xx.scr
988 */
989
990 EVENT_ISSUE_QUEUE = 0x5000000, /* Command was added to issue queue */
991 EVENT_START_QUEUE, /* Command moved to start queue */
992 EVENT_SELECT, /* Command completed selection */
993 EVENT_DISCONNECT, /* Command disconnected */
994 EVENT_RESELECT, /* Command reselected */
995 EVENT_COMPLETE, /* Command completed */
996 EVENT_IDLE,
997 EVENT_SELECT_FAILED,
998 EVENT_BEFORE_SELECT,
999 EVENT_RESELECT_FAILED
1000 };
1001
1002 struct NCR53c7x0_event {
1003 enum ncr_event event; /* What type of event */
1004 unsigned char target;
1005 unsigned char lun;
1006 struct timeval time;
1007 u32 *dsa; /* What's in the DSA register now (virt) */
1008 /*
1009 * A few things from that SCSI pid so we know what happened after
1010 * the Scsi_Cmnd structure in question may have disappeared.
1011 */
1012 unsigned long pid; /* The SCSI PID which caused this
1013 event */
1014 unsigned char cmnd[12];
1015 };
1016
1017 /*
1018 * Things in the NCR53c7x0_cmd structure are split into two parts :
1019 *
1020 * 1. A fixed portion, for things which are not accessed directly by static NCR
1021 * code (ie, are referenced only by the Linux side of the driver,
1022 * or only by dynamically generated code).
1023 *
1024 * 2. The DSA portion, for things which are accessed directly by static NCR
1025 * code.
1026 *
1027 * This is a little ugly, but it
1028 * 1. Avoids conflicts between the NCR code's picture of the structure, and
1029 * Linux code's idea of what it looks like.
1030 *
1031 * 2. Minimizes the pain in the Linux side of the code needed
1032 * to calculate real dsa locations for things, etc.
1033 *
1034 */
1035
1036 struct NCR53c7x0_cmd {
1037 void *real; /* Real, unaligned address for
1038 free function */
1039 void (* free)(void *, int); /* Command to deallocate; NULL
1040 for structures allocated with
1041 scsi_register, etc. */
1042 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
1043 structure, Scsi_Cmnd points
1044 at NCR53c7x0_cmd using
1045 host_scribble structure */
1046
1047 int size; /* scsi_malloc'd size of this
1048 structure */
1049
1050 int flags; /* CMD_* flags */
1051
1052 /*
1053 * SDTR and WIDE messages are an either/or affair
1054 * in this message, since we will go into message out and send
1055 * _the whole mess_ without dropping out of message out to
1056 * let the target go into message in after sending the first
1057 * message.
1058 */
1059
1060 unsigned char select[11]; /* Select message, includes
1061 IDENTIFY
1062 (optional) QUEUE TAG
1063 (optional) SDTR or WDTR
1064 */
1065
1066
1067 volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
1068 running, eventually finished */
1069
1070
1071 u32 *data_transfer_start; /* Start of data transfer routines */
1072 u32 *data_transfer_end; /* Address after end of data transfer o
1073 routines */
1074 /*
1075 * The following three fields were moved from the DSA proper to here
1076 * since only dynamically generated NCR code refers to them, meaning
1077 * we don't need dsa_* absolutes, and it is simpler to let the
1078 * host code refer to them directly.
1079 */
1080
1081 /*
1082 * HARD CODED : residual and saved_residual need to agree with the sizes
1083 * used in NCR53c7,8xx.scr.
1084 *
1085 * FIXME: we want to consider the case where we have odd-length
1086 * scatter/gather buffers and a WIDE transfer, in which case
1087 * we'll need to use the CHAIN MOVE instruction. Ick.
1088 */
1089 u32 residual[6]; /* Residual data transfer which
1090 allows pointer code to work
1091 right.
1092
1093 [0-1] : Conditional call to
1094 appropriate other transfer
1095 routine.
1096 [2-3] : Residual block transfer
1097 instruction.
1098 [4-5] : Jump to instruction
1099 after splice.
1100 */
1101 u32 saved_residual[6]; /* Copy of old residual, so we
1102 can get another partial
1103 transfer and still recover
1104 */
1105
1106 u32 saved_data_pointer; /* Saved data pointer */
1107
1108 u32 dsa_next_addr; /* _Address_ of dsa_next field
1109 in this dsa for RISCy
1110 style constant. */
1111
1112 u32 dsa_addr; /* Address of dsa; RISCy style
1113 constant */
1114
1115 u32 dsa[0]; /* Variable length (depending
1116 on host type, number of scatter /
1117 gather buffers, etc). */
1118 };
1119
1120 struct NCR53c7x0_break {
1121 u32 *address, old_instruction[2];
1122 struct NCR53c7x0_break *next;
1123 unsigned char old_size; /* Size of old instruction */
1124 };
1125
1126 /* Indicates that the NCR is not executing code */
1127 #define STATE_HALTED 0
1128 /*
1129 * Indicates that the NCR is executing the wait for select / reselect
1130 * script. Only used when running NCR53c700 compatible scripts, only
1131 * state during which an ABORT is _not_ considered an error condition.
1132 */
1133 #define STATE_WAITING 1
1134 /* Indicates that the NCR is executing other code. */
1135 #define STATE_RUNNING 2
1136 /*
1137 * Indicates that the NCR was being aborted.
1138 */
1139 #define STATE_ABORTING 3
1140 /* Indicates that the NCR was successfully aborted. */
1141 #define STATE_ABORTED 4
1142 /* Indicates that the NCR has been disabled due to a fatal error */
1143 #define STATE_DISABLED 5
1144
1145 /*
1146 * Where knowledge of SCSI SCRIPT(tm) specified values are needed
1147 * in an interrupt handler, an interrupt handler exists for each
1148 * different SCSI script so we don't have name space problems.
1149 *
1150 * Return values of these handlers are as follows :
1151 */
1152 #define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1153 #define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1154 #define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1155 #define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1156 #define SPECIFIC_INT_DONE 4 /* normal command completion */
1157 #define SPECIFIC_INT_BREAK 5 /* break point encountered */
1158
1159 struct NCR53c7x0_hostdata {
1160 int size; /* Size of entire Scsi_Host
1161 structure */
1162 int board; /* set to board type, useful if
1163 we have host specific things,
1164 ie, a general purpose I/O
1165 bit is being used to enable
1166 termination, etc. */
1167
1168 int chip; /* set to chip type; 700-66 is
1169 700-66, rest are last three
1170 digits of part number */
1171 /*
1172 * PCI bus, device, function, only for NCR53c8x0 chips.
1173 * pci_valid indicates that the PCI configuration information
1174 * is valid, and we can twiddle MAX_LAT, etc. as recommended
1175 * for maximum performance in the NCR documentation.
1176 */
1177 unsigned char pci_bus, pci_device_fn;
1178 unsigned pci_valid:1;
1179
1180 u32 *dsp; /* dsp to restart with after
1181 all stacked interrupts are
1182 handled. */
1183
1184 unsigned dsp_changed:1; /* Has dsp changed within this
1185 set of stacked interrupts ? */
1186
1187 unsigned char dstat; /* Most recent value of dstat */
1188 unsigned dstat_valid:1;
1189
1190 unsigned expecting_iid:1; /* Expect IID interrupt */
1191 unsigned expecting_sto:1; /* Expect STO interrupt */
1192
1193 /*
1194 * The code stays cleaner if we use variables with function
1195 * pointers and offsets that are unique for the different
1196 * scripts rather than having a slew of switch(hostdata->chip)
1197 * statements.
1198 *
1199 * It also means that the #defines from the SCSI SCRIPTS(tm)
1200 * don't have to be visible outside of the script-specific
1201 * instructions, preventing name space pollution.
1202 */
1203
1204 void (* init_fixup)(struct Scsi_Host *host);
1205 void (* init_save_regs)(struct Scsi_Host *host);
1206 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1207 void (* soft_reset)(struct Scsi_Host *host);
1208 int (* run_tests)(struct Scsi_Host *host);
1209
1210 /*
1211 * Called when DSTAT_SIR is set, indicating an interrupt generated
1212 * by the INT instruction, where values are unique for each SCSI
1213 * script. Should return one of the SPEC_* values.
1214 */
1215
1216 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1217
1218 int dsa_len; /* Size of DSA structure */
1219
1220 /*
1221 * Location of DSA fields for the SCSI SCRIPT corresponding to this
1222 * chip.
1223 */
1224
1225 s32 dsa_start;
1226 s32 dsa_end;
1227 s32 dsa_next;
1228 s32 dsa_prev;
1229 s32 dsa_cmnd;
1230 s32 dsa_select;
1231 s32 dsa_msgout;
1232 s32 dsa_cmdout;
1233 s32 dsa_dataout;
1234 s32 dsa_datain;
1235 s32 dsa_msgin;
1236 s32 dsa_msgout_other;
1237 s32 dsa_write_sync;
1238 s32 dsa_write_resume;
1239 s32 dsa_check_reselect;
1240 s32 dsa_status;
1241 s32 dsa_saved_pointer;
1242 s32 dsa_jump_dest;
1243
1244 /*
1245 * Important entry points that generic fixup code needs
1246 * to know about, fixed up.
1247 */
1248
1249 s32 E_accept_message;
1250 s32 E_command_complete;
1251 s32 E_data_transfer;
1252 s32 E_dsa_code_template;
1253 s32 E_dsa_code_template_end;
1254 s32 E_end_data_transfer;
1255 s32 E_msg_in;
1256 s32 E_initiator_abort;
1257 s32 E_other_transfer;
1258 s32 E_other_in;
1259 s32 E_other_out;
1260 s32 E_target_abort;
1261 s32 E_debug_break;
1262 s32 E_reject_message;
1263 s32 E_respond_message;
1264 s32 E_select;
1265 s32 E_select_msgout;
1266 s32 E_test_0;
1267 s32 E_test_1;
1268 s32 E_test_2;
1269 s32 E_test_3;
1270 s32 E_dsa_zero;
1271 s32 E_cmdout_cmdout;
1272 s32 E_wait_reselect;
1273 s32 E_dsa_code_begin;
1274
1275 long long options; /* Bitfielded set of options enabled */
1276 volatile u32 test_completed; /* Test completed */
1277 int test_running; /* Test currently running */
1278 s32 test_source;
1279 volatile s32 test_dest;
1280
1281 volatile int state; /* state of driver, only used for
1282 OPTION_700 */
1283
1284 unsigned char dmode; /*
1285 * set to the address of the DMODE
1286 * register for this chip.
1287 */
1288 unsigned char istat; /*
1289 * set to the address of the ISTAT
1290 * register for this chip.
1291 */
1292
1293 int scsi_clock; /*
1294 * SCSI clock in HZ. 0 may be used
1295 * for unknown, although this will
1296 * disable synchronous negotiation.
1297 */
1298
1299 volatile int intrs; /* Number of interrupts */
1300 volatile int resets; /* Number of SCSI resets */
1301 unsigned char saved_dmode;
1302 unsigned char saved_ctest4;
1303 unsigned char saved_ctest7;
1304 unsigned char saved_dcntl;
1305 unsigned char saved_scntl3;
1306
1307 unsigned char this_id_mask;
1308
1309 /* Debugger information */
1310 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1311 *breakpoint_current; /* Current breakpoint being stepped
1312 through, NULL if we are running
1313 normally. */
1314 #ifdef NCR_DEBUG
1315 int debug_size; /* Size of debug buffer */
1316 volatile int debug_count; /* Current data count */
1317 volatile char *debug_buf; /* Output ring buffer */
1318 volatile char *debug_write; /* Current write pointer */
1319 volatile char *debug_read; /* Current read pointer */
1320 #endif /* def NCR_DEBUG */
1321
1322 /* XXX - primitive debugging junk, remove when working ? */
1323 int debug_print_limit; /* Number of commands to print
1324 out exhaustive debugging
1325 information for if
1326 OPTION_DEBUG_DUMP is set */
1327
1328 unsigned char debug_lun_limit[16]; /* If OPTION_DEBUG_TARGET_LIMIT
1329 set, puke if commands are sent
1330 to other target/lun combinations */
1331
1332 int debug_count_limit; /* Number of commands to execute
1333 before puking to limit debugging
1334 output */
1335
1336
1337 volatile unsigned idle:1; /* set to 1 if idle */
1338
1339 /*
1340 * Table of synchronous+wide transfer parameters set on a per-target
1341 * basis.
1342 */
1343
1344 volatile struct NCR53c7x0_synchronous sync[16];
1345
1346 volatile Scsi_Cmnd *issue_queue;
1347 /* waiting to be issued by
1348 Linux driver */
1349 volatile struct NCR53c7x0_cmd *running_list;
1350 /* commands running, maintained
1351 by Linux driver */
1352
1353 volatile struct NCR53c7x0_cmd *curr; /* currently connected
1354 nexus, ONLY valid for
1355 NCR53c700/NCR53c700-66
1356 */
1357
1358 volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
1359 allocated at probe time,
1360 which we can use for
1361 initialization */
1362 volatile struct NCR53c7x0_cmd *free;
1363 int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
1364 based on number of
1365 scatter/gather segments, etc.
1366 */
1367 volatile int num_cmds; /* Number of commands
1368 allocated */
1369 volatile int extra_allocate;
1370 volatile unsigned char cmd_allocated[16]; /* Have we allocated commands
1371 for this target yet? If not,
1372 do so ASAP */
1373 volatile unsigned char busy[16][8]; /* number of commands
1374 executing on each target
1375 */
1376 /*
1377 * Eventually, I'll switch to a coroutine for calling
1378 * cmd->done(cmd), etc. so that we can overlap interrupt
1379 * processing with this code for maximum performance.
1380 */
1381
1382 volatile struct NCR53c7x0_cmd *finished_queue;
1383
1384
1385 /* Shared variables between SCRIPT and host driver */
1386 volatile u32 *schedule; /* Array of JUMPs to dsa_begin
1387 routines of various DSAs.
1388 When not in use, replace
1389 with jump to next slot */
1390
1391
1392 volatile unsigned char msg_buf[16]; /* buffer for messages
1393 other than the command
1394 complete message */
1395
1396 /* Per-target default synchronous and WIDE messages */
1397 volatile unsigned char synchronous_want[16][5];
1398 volatile unsigned char wide_want[16][4];
1399
1400 /* Bit fielded set of targets we want to speak synchronously with */
1401 volatile u16 initiate_sdtr;
1402 /* Bit fielded set of targets we want to speak wide with */
1403 volatile u16 initiate_wdtr;
1404 /* Bit fielded list of targets we've talked to. */
1405 volatile u16 talked_to;
1406
1407 /* Array of bit-fielded lun lists that we need to request_sense */
1408 volatile unsigned char request_sense[16];
1409
1410 u32 addr_reconnect_dsa_head; /* RISCy style constant,
1411 address of following */
1412 volatile u32 reconnect_dsa_head;
1413 /* Data identifying nexus we are trying to match during reselection */
1414 volatile unsigned char reselected_identify; /* IDENTIFY message */
1415 volatile unsigned char reselected_tag; /* second byte of queue tag
1416 message or 0 */
1417 /* These were static variables before we moved them */
1418
1419 s32 NCR53c7xx_zero;
1420 s32 NCR53c7xx_sink;
1421 u32 NOP_insn;
1422 char NCR53c7xx_msg_reject;
1423 char NCR53c7xx_msg_abort;
1424 char NCR53c7xx_msg_nop;
1425
1426 volatile int event_size, event_index;
1427 volatile struct NCR53c7x0_event *events;
1428
1429 /* If we need to generate code to kill off the currently connected
1430 command, this is where we do it. Should have a BMI instruction
1431 to source or sink the current data, followed by a JUMP
1432 to abort_connected */
1433
1434 u32 *abort_script;
1435
1436 int script_count; /* Size of script in words */
1437 u32 script[0]; /* Relocated SCSI script */
1438
1439 };
1440
1441 #define IRQ_NONE 255
1442 #define DMA_NONE 255
1443 #define IRQ_AUTO 254
1444 #define DMA_AUTO 254
1445
1446 #define BOARD_GENERIC 0
1447
1448 #define NCR53c7x0_insn_size(insn) \
1449 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1450
1451
1452 #define NCR53c7x0_local_declare() \
1453 volatile unsigned char *NCR53c7x0_address_memory; \
1454 unsigned int NCR53c7x0_address_io; \
1455 int NCR53c7x0_memory_mapped
1456
1457 #define NCR53c7x0_local_setup(host) \
1458 NCR53c7x0_address_memory = (void *) (host)->base; \
1459 NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
1460 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1461 host->hostdata)-> options & OPTION_MEMORY_MAPPED
1462
1463 #define NCR53c7x0_read8(address) \
1464 (NCR53c7x0_memory_mapped ? \
1465 (unsigned int)readb(NCR53c7x0_address_memory + (address)) : \
1466 inb(NCR53c7x0_address_io + (address)))
1467
1468 #define NCR53c7x0_read16(address) \
1469 (NCR53c7x0_memory_mapped ? \
1470 (unsigned int)readw(NCR53c7x0_address_memory + (address)) : \
1471 inw(NCR53c7x0_address_io + (address)))
1472
1473 #define NCR53c7x0_read32(address) \
1474 (NCR53c7x0_memory_mapped ? \
1475 (unsigned int) readl(NCR53c7x0_address_memory + (address)) : \
1476 inl(NCR53c7x0_address_io + (address)))
1477
1478 #define NCR53c7x0_write8(address,value) \
1479 (NCR53c7x0_memory_mapped ? \
1480 ({writeb((value), NCR53c7x0_address_memory + (address)); mb();}) : \
1481 outb((value), NCR53c7x0_address_io + (address)))
1482
1483 #define NCR53c7x0_write16(address,value) \
1484 (NCR53c7x0_memory_mapped ? \
1485 ({writew((value), NCR53c7x0_address_memory + (address)); mb();}) : \
1486 outw((value), NCR53c7x0_address_io + (address)))
1487
1488 #define NCR53c7x0_write32(address,value) \
1489 (NCR53c7x0_memory_mapped ? \
1490 ({writel((value), NCR53c7x0_address_memory + (address)); mb();}) : \
1491 outl((value), NCR53c7x0_address_io + (address)))
1492
1493 /* Patch arbitrary 32 bit words in the script */
1494 #define patch_abs_32(script, offset, symbol, value) \
1495 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1496 (u32)); ++i) { \
1497 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1498 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1499 printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1500 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1501 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1502 (offset)]); \
1503 }
1504
1505 /* Patch read/write instruction immediate field */
1506 #define patch_abs_rwri_data(script, offset, symbol, value) \
1507 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1508 (u32)); ++i) \
1509 (script)[A_##symbol##_used[i] - (offset)] = \
1510 ((script)[A_##symbol##_used[i] - (offset)] & \
1511 ~DBC_RWRI_IMMEDIATE_MASK) | \
1512 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1513 DBC_RWRI_IMMEDIATE_MASK)
1514
1515 /* Patch transfer control instruction data field */
1516 #define patch_abs_tci_data(script, offset, symbol, value) \
1517 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1518 (u32)); ++i) \
1519 (script)[A_##symbol##_used[i] - (offset)] = \
1520 ((script)[A_##symbol##_used[i] - (offset)] & \
1521 ~DBC_TCI_DATA_MASK) | \
1522 (((value) << DBC_TCI_DATA_SHIFT) & \
1523 DBC_TCI_DATA_MASK)
1524
1525 /* Patch field in dsa structure (assignment should be +=?) */
1526 #define patch_dsa_32(dsa, symbol, word, value) \
1527 { \
1528 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32) \
1529 + (word)] = (value); \
1530 if (hostdata->options & OPTION_DEBUG_DSA) \
1531 printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
1532 #dsa, #symbol, hostdata->##symbol, \
1533 (word), (u32) le32_to_cpu(value)); \
1534 }
1535
1536 /* Paranoid people could use panic() here. */
1537 #define FATAL(host) shutdown((host));
1538
1539 #endif /* NCR53c7x0_C */
1540 #endif /* NCR53c7x0_H */