i386/linux/linux-2.3.21/include/asm-ppc/irq.h

   1 #include <linux/config.h>
   2
   3 #ifndef _ASM_IRQ_H
   4 #define _ASM_IRQ_H
   5
   6 #include <asm/machdep.h>                /* ppc_md */
   7
   8 extern void disable_irq(unsigned int);
   9 extern void disable_irq_nosync(unsigned int);
  10 extern void enable_irq(unsigned int);
  11
  12 #ifndef CONFIG_8xx
  13
  14 #ifdef CONFIG_APUS
  15 #define enable_irq m68k_enable_irq
  16 #define disable_irq m68k_disable_irq
  17 #include <asm-m68k/irq.h>
  18 #undef enable_irq
  19 #undef disable_irq
  20 #else /* CONFIG_APUS */
  21
  22 /*
  23  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
  24  * so it is the max of them all - which happens to be powermac
  25  * at present (G3 powermacs have 64).
  26  */
  27 #define NR_IRQS                 128
  28
  29 #endif /* CONFIG_APUS */
  30
  31 #define NUM_8259_INTERRUPTS     16
  32 #define IRQ_8259_CASCADE        16
  33 #define openpic_to_irq(n)       ((n)+NUM_8259_INTERRUPTS)
  34 #define irq_to_openpic(n)       ((n)-NUM_8259_INTERRUPTS)
  35
  36 #ifndef CONFIG_APUS
  37 /*
  38  * This gets called from serial.c, which is now used on
  39  * powermacs as well as prep/chrp boxes.
  40  * Prep and chrp both have cascaded 8259 PICs.
  41  */
  42 static __inline__ int irq_cannonicalize(int irq)
  43 {
  44         if (ppc_md.irq_cannonicalize)
  45         {
  46                 return ppc_md.irq_cannonicalize(irq);
  47         }
  48         else
  49         {
  50                 return irq;
  51         }
  52 }
  53 #endif
  54
  55 #else /* CONFIG_8xx */
  56
  57 /* The MPC8xx cores have 16 possible interrupts.  There are eight
  58  * possible level sensitive interrupts assigned and generated internally
  59  * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
  60  * There are eight external interrupts (IRQs) that can be configured
  61  * as either level or edge sensitive.
  62  *
  63  * The 82xx can have up to 64 interrupts on the internal controller.
  64  *
  65  * On some implementations, there is also the possibility of an 8259
  66  * through the PCI and PCI-ISA bridges.
  67  */
  68 #ifdef CONFIG_82xx
  69 #define NR_SIU_INTS     64
  70 #else
  71 #define NR_SIU_INTS     16
  72 #endif
  73
  74 #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS)
  75
  76 /* These values must be zero-based and map 1:1 with the SIU configuration.
  77  * They are used throughout the 8xx/82xx I/O subsystem to generate
  78  * interrupt masks, flags, and other control patterns.  This is why the
  79  * current kernel assumption of the 8259 as the base controller is such
  80  * a pain in the butt.
  81  */
  82 #define SIU_IRQ0        (0)     /* Highest priority */
  83 #define SIU_LEVEL0      (1)
  84 #define SIU_IRQ1        (2)
  85 #define SIU_LEVEL1      (3)
  86 #define SIU_IRQ2        (4)
  87 #define SIU_LEVEL2      (5)
  88 #define SIU_IRQ3        (6)
  89 #define SIU_LEVEL3      (7)
  90 #define SIU_IRQ4        (8)
  91 #define SIU_LEVEL4      (9)
  92 #define SIU_IRQ5        (10)
  93 #define SIU_LEVEL5      (11)
  94 #define SIU_IRQ6        (12)
  95 #define SIU_LEVEL6      (13)
  96 #define SIU_IRQ7        (14)
  97 #define SIU_LEVEL7      (15)
  98
  99 /* The internal interrupts we can configure as we see fit.
 100  * My personal preference is CPM at level 2, which puts it above the
 101  * MBX PCI/ISA/IDE interrupts.
 102  */
 103 #define PIT_INTERRUPT           SIU_LEVEL0
 104 #define CPM_INTERRUPT           SIU_LEVEL2
 105 #define PCMCIA_INTERRUPT        SIU_LEVEL6
 106 #define DEC_INTERRUPT           SIU_LEVEL7
 107
 108 /* Some internal interrupt registers use an 8-bit mask for the interrupt
 109  * level instead of a number.
 110  */
 111 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
 112
 113 /* Now include the board configuration specific associations.
 114 */
 115 #include <asm/mpc8xx.h>
 116
 117 /* always the same on 8xx -- Cort */
 118 static __inline__ int irq_cannonicalize(int irq)
 119 {
 120         return irq;
 121 }
 122
 123 #endif /* CONFIG_8xx */
 124
 125 #endif