i386/linux/linux-2.3.21/include/asm-ppc/mmu.h

   1 /*
   2  * PowerPC memory management structures
   3  */
   4
   5 #ifndef _PPC_MMU_H_
   6 #define _PPC_MMU_H_
   7
   8 #include <linux/config.h>
   9
  10 #ifndef __ASSEMBLY__
  11 /* Hardware Page Table Entry */
  12 typedef struct _PTE {
  13 #ifdef CONFIG_PPC64
  14         unsigned long long vsid:52;
  15         unsigned long api:5;
  16         unsigned long :5;
  17         unsigned long h:1;
  18         unsigned long v:1;
  19         unsigned long long rpn:52;
  20 #else /* CONFIG_PPC64 */
  21         unsigned long v:1;      /* Entry is valid */
  22         unsigned long vsid:24;  /* Virtual segment identifier */
  23         unsigned long h:1;      /* Hash algorithm indicator */
  24         unsigned long api:6;    /* Abbreviated page index */
  25         unsigned long rpn:20;   /* Real (physical) page number */
  26 #endif /* CONFIG_PPC64 */
  27         unsigned long    :3;    /* Unused */
  28         unsigned long r:1;      /* Referenced */
  29         unsigned long c:1;      /* Changed */
  30         unsigned long w:1;      /* Write-thru cache mode */
  31         unsigned long i:1;      /* Cache inhibited */
  32         unsigned long m:1;      /* Memory coherence */
  33         unsigned long g:1;      /* Guarded */
  34         unsigned long  :1;      /* Unused */
  35         unsigned long pp:2;     /* Page protection */
  36 } PTE;
  37
  38 /* Values for PP (assumes Ks=0, Kp=1) */
  39 #define PP_RWXX 0       /* Supervisor read/write, User none */
  40 #define PP_RWRX 1       /* Supervisor read/write, User read */
  41 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  42 #define PP_RXRX 3       /* Supervisor read,       User read */
  43
  44 /* Segment Register */
  45 typedef struct _SEGREG {
  46         unsigned long t:1;      /* Normal or I/O  type */
  47         unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
  48         unsigned long kp:1;     /* User 'key' (normally 1) */
  49         unsigned long n:1;      /* No-execute */
  50         unsigned long :4;       /* Unused */
  51         unsigned long vsid:24;  /* Virtual Segment Identifier */
  52 } SEGREG;
  53
  54 /* Block Address Translation (BAT) Registers */
  55 typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
  56         unsigned long bepi:15;  /* Effective page index (virtual address) */
  57         unsigned long :8;       /* unused */
  58         unsigned long w:1;
  59         unsigned long i:1;      /* Cache inhibit */
  60         unsigned long m:1;      /* Memory coherence */
  61         unsigned long ks:1;     /* Supervisor key (normally 0) */
  62         unsigned long kp:1;     /* User key (normally 1) */
  63         unsigned long pp:2;     /* Page access protections */
  64 } P601_BATU;
  65
  66 typedef struct _BATU {          /* Upper part of BAT (all except 601) */
  67 #ifdef CONFIG_PPC64
  68         unsigned long long bepi:47;
  69 #else /* CONFIG_PPC64 */
  70         unsigned long bepi:15;  /* Effective page index (virtual address) */
  71 #endif /* CONFIG_PPC64 */
  72         unsigned long :4;       /* Unused */
  73         unsigned long bl:11;    /* Block size mask */
  74         unsigned long vs:1;     /* Supervisor valid */
  75         unsigned long vp:1;     /* User valid */
  76 } BATU;
  77
  78 typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
  79         unsigned long brpn:15;  /* Real page index (physical address) */
  80         unsigned long :10;      /* Unused */
  81         unsigned long v:1;      /* Valid bit */
  82         unsigned long bl:6;     /* Block size mask */
  83 } P601_BATL;
  84
  85 typedef struct _BATL {          /* Lower part of BAT (all except 601) */
  86 #ifdef CONFIG_PPC64
  87         unsigned long long brpn:47;
  88 #else /* CONFIG_PPC64 */
  89         unsigned long brpn:15;  /* Real page index (physical address) */
  90 #endif /* CONFIG_PPC64 */
  91         unsigned long :10;      /* Unused */
  92         unsigned long w:1;      /* Write-thru cache */
  93         unsigned long i:1;      /* Cache inhibit */
  94         unsigned long m:1;      /* Memory coherence */
  95         unsigned long g:1;      /* Guarded (MBZ in IBAT) */
  96         unsigned long :1;       /* Unused */
  97         unsigned long pp:2;     /* Page access protections */
  98 } BATL;
  99
 100 typedef struct _BAT {
 101         BATU batu;              /* Upper register */
 102         BATL batl;              /* Lower register */
 103 } BAT;
 104
 105 typedef struct _P601_BAT {
 106         P601_BATU batu;         /* Upper register */
 107         P601_BATL batl;         /* Lower register */
 108 } P601_BAT;
 109
 110 /*
 111  * Simulated two-level MMU.  This structure is used by the kernel
 112  * to keep track of MMU mappings and is used to update/maintain
 113  * the hardware HASH table which is really a cache of mappings.
 114  *
 115  * The simulated structures mimic the hardware available on other
 116  * platforms, notably the 80x86 and 680x0.
 117  */
 118
 119 typedef struct _pte {
 120         unsigned long page_num:20;
 121         unsigned long flags:12;         /* Page flags (some unused bits) */
 122 } pte;
 123
 124 #define PD_SHIFT (10+12)                /* Page directory */
 125 #define PD_MASK  0x02FF
 126 #define PT_SHIFT (12)                   /* Page Table */
 127 #define PT_MASK  0x02FF
 128 #define PG_SHIFT (12)                   /* Page Entry */
 129
 130
 131 /* MMU context */
 132
 133 typedef struct _MMU_context {
 134         SEGREG  segs[16];       /* Segment registers */
 135         pte     **pmap;         /* Two-level page-map structure */
 136 } MMU_context;
 137
 138 /* invalidate a TLB entry */
 139 extern inline void _tlbie(unsigned long va)
 140 {
 141         asm volatile ("tlbie %0" : : "r"(va));
 142 }
 143
 144 extern void _tlbia(void);               /* invalidate all TLB entries */
 145
 146 #endif /* __ASSEMBLY__ */
 147
 148 /* Block size masks */
 149 #define BL_128K 0x000
 150 #define BL_256K 0x001
 151 #define BL_512K 0x003
 152 #define BL_1M   0x007
 153 #define BL_2M   0x00F
 154 #define BL_4M   0x01F
 155 #define BL_8M   0x03F
 156 #define BL_16M  0x07F
 157 #define BL_32M  0x0FF
 158 #define BL_64M  0x1FF
 159 #define BL_128M 0x3FF
 160 #define BL_256M 0x7FF
 161
 162 /* BAT Access Protection */
 163 #define BPP_XX  0x00            /* No access */
 164 #define BPP_RX  0x01            /* Read only */
 165 #define BPP_RW  0x02            /* Read/write */
 166
 167 /* Used to set up SDR1 register */
 168 #define HASH_TABLE_SIZE_64K     0x00010000
 169 #define HASH_TABLE_SIZE_128K    0x00020000
 170 #define HASH_TABLE_SIZE_256K    0x00040000
 171 #define HASH_TABLE_SIZE_512K    0x00080000
 172 #define HASH_TABLE_SIZE_1M      0x00100000
 173 #define HASH_TABLE_SIZE_2M      0x00200000
 174 #define HASH_TABLE_SIZE_4M      0x00400000
 175 #define HASH_TABLE_MASK_64K     0x000
 176 #define HASH_TABLE_MASK_128K    0x001
 177 #define HASH_TABLE_MASK_256K    0x003
 178 #define HASH_TABLE_MASK_512K    0x007
 179 #define HASH_TABLE_MASK_1M      0x00F
 180 #define HASH_TABLE_MASK_2M      0x01F
 181 #define HASH_TABLE_MASK_4M      0x03F
 182
 183 /* Control/status registers for the MPC8xx.
 184  * A write operation to these registers causes serialized access.
 185  * During software tablewalk, the registers used perform mask/shift-add
 186  * operations when written/read.  A TLB entry is created when the Mx_RPN
 187  * is written, and the contents of several registers are used to
 188  * create the entry.
 189  */
 190 #define MI_CTR          784     /* Instruction TLB control register */
 191 #define MI_GPM          0x80000000      /* Set domain manager mode */
 192 #define MI_PPM          0x40000000      /* Set subpage protection */
 193 #define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 194 #define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 195 #define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 196 #define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
 197 #define MI_RESETVAL     0x00000000      /* Value of register at reset */
 198
 199 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 200  * Ks = 0, Kp = 1.
 201  */
 202 #define MI_AP           786
 203 #define MI_Ks           0x80000000      /* Should not be set */
 204 #define MI_Kp           0x40000000      /* Should always be set */
 205
 206 /* The effective page number register.  When read, contains the information
 207  * about the last instruction TLB miss.  When MI_RPN is written, bits in
 208  * this register are used to create the TLB entry.
 209  */
 210 #define MI_EPN          787
 211 #define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
 212 #define MI_EVALID       0x00000200      /* Entry is valid */
 213 #define MI_ASIDMASK     0x0000000f      /* ASID match value */
 214                                         /* Reset value is undefined */
 215
 216 /* A "level 1" or "segment" or whatever you want to call it register.
 217  * For the instruction TLB, it contains bits that get loaded into the
 218  * TLB entry when the MI_RPN is written.
 219  */
 220 #define MI_TWC          789
 221 #define MI_APG          0x000001e0      /* Access protection group (0) */
 222 #define MI_GUARDED      0x00000010      /* Guarded storage */
 223 #define MI_PSMASK       0x0000000c      /* Mask of page size bits */
 224 #define MI_PS8MEG       0x0000000c      /* 8M page size */
 225 #define MI_PS512K       0x00000004      /* 512K page size */
 226 #define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
 227 #define MI_SVALID       0x00000001      /* Segment entry is valid */
 228                                         /* Reset value is undefined */
 229
 230 /* Real page number.  Defined by the pte.  Writing this register
 231  * causes a TLB entry to be created for the instruction TLB, using
 232  * additional information from the MI_EPN, and MI_TWC registers.
 233  */
 234 #define MI_RPN          790
 235
 236 /* Define an RPN value for mapping kernel memory to large virtual
 237  * pages for boot initialization.  This has real page number of 0,
 238  * large page size, shared page, cache enabled, and valid.
 239  * Also mark all subpages valid and write access.
 240  */
 241 #define MI_BOOTINIT     0x000001fd
 242
 243 #define MD_CTR          792     /* Data TLB control register */
 244 #define MD_GPM          0x80000000      /* Set domain manager mode */
 245 #define MD_PPM          0x40000000      /* Set subpage protection */
 246 #define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 247 #define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
 248 #define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 249 #define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
 250 #define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 251 #define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
 252 #define MD_RESETVAL     0x04000000      /* Value of register at reset */
 253
 254 #define M_CASID         793     /* Address space ID (context) to match */
 255 #define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
 256
 257
 258 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 259  * Ks = 0, Kp = 1.
 260  */
 261 #define MD_AP           794
 262 #define MD_Ks           0x80000000      /* Should not be set */
 263 #define MD_Kp           0x40000000      /* Should always be set */
 264
 265 /* The effective page number register.  When read, contains the information
 266  * about the last instruction TLB miss.  When MD_RPN is written, bits in
 267  * this register are used to create the TLB entry.
 268  */
 269 #define MD_EPN          795
 270 #define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
 271 #define MD_EVALID       0x00000200      /* Entry is valid */
 272 #define MD_ASIDMASK     0x0000000f      /* ASID match value */
 273                                         /* Reset value is undefined */
 274
 275 /* The pointer to the base address of the first level page table.
 276  * During a software tablewalk, reading this register provides the address
 277  * of the entry associated with MD_EPN.
 278  */
 279 #define M_TWB           796
 280 #define M_L1TB          0xfffff000      /* Level 1 table base address */
 281 #define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
 282                                         /* Reset value is undefined */
 283
 284 /* A "level 1" or "segment" or whatever you want to call it register.
 285  * For the data TLB, it contains bits that get loaded into the TLB entry
 286  * when the MD_RPN is written.  It is also provides the hardware assist
 287  * for finding the PTE address during software tablewalk.
 288  */
 289 #define MD_TWC          797
 290 #define MD_L2TB         0xfffff000      /* Level 2 table base address */
 291 #define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
 292 #define MD_APG          0x000001e0      /* Access protection group (0) */
 293 #define MD_GUARDED      0x00000010      /* Guarded storage */
 294 #define MD_PSMASK       0x0000000c      /* Mask of page size bits */
 295 #define MD_PS8MEG       0x0000000c      /* 8M page size */
 296 #define MD_PS512K       0x00000004      /* 512K page size */
 297 #define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
 298 #define MD_WT           0x00000002      /* Use writethrough page attribute */
 299 #define MD_SVALID       0x00000001      /* Segment entry is valid */
 300                                         /* Reset value is undefined */
 301
 302
 303 /* Real page number.  Defined by the pte.  Writing this register
 304  * causes a TLB entry to be created for the data TLB, using
 305  * additional information from the MD_EPN, and MD_TWC registers.
 306  */
 307 #define MD_RPN          798
 308
 309 /* This is a temporary storage register that could be used to save
 310  * a processor working register during a tablewalk.
 311  */
 312 #define M_TW            799
 313 #endif /* _PPC_MMU_H_ */