i386/linux/linux-2.3.21/include/net/irda/smc-ircc.h

   1 /*********************************************************************
   2  *
   3  * Filename:      smc.h
   4  * Version:
   5  * Description:
   6  * Status:        Experimental.
   7  * Author:        Thomas Davis (tadavis@jps.net)
   8  *
   9  *     Copyright (c) 1998, 1999 Thomas Davis (tadavis@jps.net>
  10  *     All Rights Reserved
  11  *
  12  *     This program is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of
  15  *     the License, or (at your option) any later version.
  16  *
  17  *     I, Thomas Davis, admit no liability nor provide warranty for any
  18  *     of this software. This material is provided "AS-IS" and at no charge.
  19  *
  20  * Definitions for the SMC IrCC controller.
  21  *
  22  ********************************************************************/
  23
  24 #ifndef SMC_IRCC_H
  25 #define SMC_IRCC_H
  26
  27 #define UART_MASTER                     0x07
  28 #define UART_MASTER_POWERDOWN   1<<7
  29 #define UART_MASTER_RESET               1<<6
  30 #define UART_MASTER_INT_EN              1<<5
  31 #define UART_MASTER_ERROR_RESET 1<<4
  32
  33 /* Register block 0 */
  34
  35 #define UART_IIR        0x01
  36 #define UART_IER        0x02
  37 #define UART_LSR        0x03
  38 #define UART_LCR_A      0x04
  39 #define UART_LCR_B      0x05
  40 #define UART_BSR        0x06
  41
  42 #define UART_IIR_ACTIVE_FRAME   1<<7
  43 #define UART_IIR_EOM            1<<6
  44 #define UART_IIR_RAW_MODE               1<<5
  45 #define UART_IIR_FIFO           1<<4
  46
  47 #define UART_IER_ACTIVE_FRAME   1<<7
  48 #define UART_IER_EOM            1<<6
  49 #define UART_IER_RAW_MODE               1<<5
  50 #define UART_IER_FIFO           1<<4
  51
  52 #define UART_LSR_UNDERRUN               1<<7
  53 #define UART_LSR_OVERRUN                1<<6
  54 #define UART_LSR_FRAME_ERROR    1<<5
  55 #define UART_LSR_SIZE_ERROR             1<<4
  56 #define UART_LSR_CRC_ERROR              1<<3
  57 #define UART_LSR_FRAME_ABORT    1<<2
  58
  59 #define UART_LCR_A_FIFO_RESET        1<<7
  60 #define UART_LCR_A_FAST              1<<6
  61 #define UART_LCR_A_GP_DATA           1<<5
  62 #define UART_LCR_A_RAW_TX            1<<4
  63 #define UART_LCR_A_RAW_RX            1<<3
  64 #define UART_LCR_A_ABORT             1<<2
  65 #define UART_LCR_A_DATA_DONE         1<<1
  66
  67 #define UART_LCR_B_SCE_DISABLED         0x00<<6
  68 #define UART_LCR_B_SCE_TRANSMIT         0x01<<6
  69 #define UART_LCR_B_SCE_RECEIVE          0x02<<6
  70 #define UART_LCR_B_SCE_UNDEFINED        0x03<<6
  71 #define UART_LCR_B_SIP_ENABLE           1<<5
  72 #define UART_LCR_B_BRICK_WALL           1<<4
  73
  74 #define UART_BSR_NOT_EMPTY      1<<7
  75 #define UART_BSR_FIFO_FULL      1<<6
  76 #define UART_BSR_TIMEOUT        1<<5
  77
  78 /* Register block 1 */
  79
  80 #define UART_SCE_CFGA   0x00
  81 #define UART_SCE_CFGB   0x01
  82 #define UART_FIFO_THRESHOLD     0x02
  83
  84 #define UART_CFGA_AUX_IR                0x01<<7
  85 #define UART_CFGA_HALF_DUPLEX   0x01<<2
  86 #define UART_CFGA_TX_POLARITY   0x01<<1
  87 #define UART_CFGA_RX_POLARITY   0x01
  88
  89 #define UART_CFGA_COM           0x00<<3
  90 #define UART_CFGA_IRDA_SIR_A    0x01<<3
  91 #define UART_CFGA_ASK_SIR               0x02<<3
  92 #define UART_CFGA_IRDA_SIR_B    0x03<<3
  93 #define UART_CFGA_IRDA_HDLC     0x04<<3
  94 #define UART_CFGA_IRDA_4PPM     0x05<<3
  95 #define UART_CFGA_CONSUMER              0x06<<3
  96 #define UART_CFGA_RAW_IR                0x07<<3
  97 #define UART_CFGA_OTHER         0x08<<3
  98
  99 #define UART_IR_HDLC                    0x04
 100 #define UART_IR_4PPM                    0x01
 101 #define UART_IR_CONSUMER                0x02
 102
 103 #define UART_CFGB_LOOPBACK              0x01<<5
 104 #define UART_CFGB_LPBCK_TX_CRC  0x01<<4
 105 #define UART_CFGB_NOWAIT                0x01<<3
 106 #define UART_CFGB_STRING_MOVE   0x01<<2
 107 #define UART_CFGB_DMA_BURST     0x01<<1
 108 #define UART_CFGB_DMA_ENABLE    0x01
 109
 110 #define UART_CFGB_COM           0x00<<6
 111 #define UART_CFGB_IR            0x01<<6
 112 #define UART_CFGB_AUX           0x02<<6
 113 #define UART_CFGB_INACTIVE              0x03<<6
 114
 115 /* Register block 2 - Consumer IR - not used */
 116
 117 /* Register block 3 - Identification Registers! */
 118
 119 #define UART_ID_HIGH    0x00   /* 0x10 */
 120 #define UART_ID_LOW     0x01   /* 0xB8 */
 121 #define UART_CHIP_ID    0x02   /* 0xF1 */
 122 #define UART_VERSION    0x03   /* 0x01 */
 123 #define UART_INTERFACE  0x04   /* low 4 = DMA, high 4 = IRQ */
 124
 125 /* Register block 4 - IrDA */
 126 #define UART_CONTROL        0x00
 127 #define UART_BOF_COUNT_LO      0x01
 128 #define UART_BRICKWALL_CNT_LO 0x02
 129 #define UART_BRICKWALL_TX_CNT_HI   0x03
 130 #define UART_TX_SIZE_LO   0x04
 131 #define UART_RX_SIZE_HI   0x05
 132 #define UART_RX_SIZE_LO   0x06
 133
 134 #define UART_1152     0x01<<7
 135 #define UART_CRC      0x01<<6
 136
 137 /* For storing entries in the status FIFO */
 138 struct st_fifo_entry {
 139         int status;
 140         int len;
 141 };
 142
 143 struct st_fifo {
 144         struct st_fifo_entry entries[10];
 145         int head;
 146         int tail;
 147         int len;
 148 };
 149
 150 /* Private data for each instance */
 151 struct ircc_cb {
 152         struct st_fifo st_fifo;
 153
 154         int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
 155         int tx_len;          /* Number of frames in tx_buff */
 156
 157         struct irda_device idev;
 158 };
 159
 160 #endif