i386/linux/linux-2.3.21/arch/alpha/kernel/core_t2.c

   1 /*
   2  *      linux/arch/alpha/kernel/core_t2.c
   3  *
   4  * Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
   5  * December 1996.
   6  *
   7  * based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
   8  *
   9  * Code common to all T2 core logic chips.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/pci.h>
  15 #include <linux/sched.h>
  16 #include <linux/init.h>
  17
  18 #include <asm/ptrace.h>
  19 #include <asm/system.h>
  20
  21 #define __EXTERN_INLINE
  22 #include <asm/io.h>
  23 #include <asm/core_t2.h>
  24 #undef __EXTERN_INLINE
  25
  26 #include "proto.h"
  27 #include "pci_impl.h"
  28
  29
  30 /*
  31  * NOTE: Herein lie back-to-back mb instructions.  They are magic.
  32  * One plausible explanation is that the i/o controller does not properly
  33  * handle the system transaction.  Another involves timing.  Ho hum.
  34  */
  35
  36 /*
  37  * BIOS32-style PCI interface:
  38  */
  39
  40 #define DEBUG_CONFIG 0
  41
  42 #if DEBUG_CONFIG
  43 # define DBG(args)      printk args
  44 #else
  45 # define DBG(args)
  46 #endif
  47
  48
  49 /*
  50  * Given a bus, device, and function number, compute resulting
  51  * configuration space address and setup the T2_HAXR2 register
  52  * accordingly.  It is therefore not safe to have concurrent
  53  * invocations to configuration space access routines, but there
  54  * really shouldn't be any need for this.
  55  *
  56  * Type 0:
  57  *
  58  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  59  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  60  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  61  * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  62  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  63  *
  64  *      31:11   Device select bit.
  65  *      10:8    Function number
  66  *       7:2    Register number
  67  *
  68  * Type 1:
  69  *
  70  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  71  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  72  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  73  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  74  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  75  *
  76  *      31:24   reserved
  77  *      23:16   bus number (8 bits = 128 possible buses)
  78  *      15:11   Device number (5 bits)
  79  *      10:8    function number
  80  *       7:2    register number
  81  *
  82  * Notes:
  83  *      The function number selects which function of a multi-function device
  84  *      (e.g., SCSI and Ethernet).
  85  *
  86  *      The register selects a DWORD (32 bit) register offset.  Hence it
  87  *      doesn't get shifted by 2 bits as we want to "drop" the bottom two
  88  *      bits.
  89  */
  90
  91 static int
  92 mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
  93              unsigned char *type1)
  94 {
  95         unsigned long addr;
  96         u8 bus = dev->bus->number;
  97         u8 device_fn = dev->devfn;
  98
  99         DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
 100              " addr=0x%lx, type1=0x%x)\n",
 101              bus, device_fn, where, pci_addr, type1));
 102
 103         if (bus == 0) {
 104                 int device = device_fn >> 3;
 105
 106                 /* Type 0 configuration cycle.  */
 107
 108                 if (device > 8) {
 109                         DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
 110                              device));
 111                         return -1;
 112                 }
 113
 114                 *type1 = 0;
 115                 addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
 116         } else {
 117                 /* Type 1 configuration cycle.  */
 118                 *type1 = 1;
 119                 addr = (bus << 16) | (device_fn << 8) | (where);
 120         }
 121         *pci_addr = addr;
 122         DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
 123         return 0;
 124 }
 125
 126 static unsigned int
 127 conf_read(unsigned long addr, unsigned char type1)
 128 {
 129         unsigned long flags;
 130         unsigned int value, cpu;
 131         unsigned long t2_cfg = 0;
 132
 133         cpu = smp_processor_id();
 134
 135         __save_and_cli(flags);  /* avoid getting hit by machine check */
 136
 137         DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
 138
 139 #if 0
 140         {
 141           unsigned long stat0;
 142           /* Reset status register to avoid losing errors.  */
 143           stat0 = *(vulp)T2_IOCSR;
 144           *(vulp)T2_IOCSR = stat0;
 145           mb();
 146           DBG(("conf_read: T2 IOCSR was 0x%x\n", stat0));
 147         }
 148 #endif
 149
 150         /* If Type1 access, must set T2 CFG.  */
 151         if (type1) {
 152                 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
 153                 *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
 154                 mb();
 155                 DBG(("conf_read: TYPE1 access\n"));
 156         }
 157         mb();
 158         draina();
 159
 160         mcheck_expected(cpu) = 1;
 161         mcheck_taken(cpu) = 0;
 162         mb();
 163
 164         /* Access configuration space. */
 165         value = *(vuip)addr;
 166         mb();
 167         mb();  /* magic */
 168
 169         if (mcheck_taken(cpu)) {
 170                 mcheck_taken(cpu) = 0;
 171                 value = 0xffffffffU;
 172                 mb();
 173         }
 174         mcheck_expected(cpu) = 0;
 175         mb();
 176
 177         /* If Type1 access, must reset T2 CFG so normal IO space ops work.  */
 178         if (type1) {
 179                 *(vulp)T2_HAE_3 = t2_cfg;
 180                 mb();
 181         }
 182         DBG(("conf_read(): finished\n"));
 183
 184         __restore_flags(flags);
 185         return value;
 186 }
 187
 188 static void
 189 conf_write(unsigned long addr, unsigned int value, unsigned char type1)
 190 {
 191         unsigned long flags;
 192         unsigned int cpu;
 193         unsigned long t2_cfg = 0;
 194
 195         cpu = smp_processor_id();
 196
 197         __save_and_cli(flags);  /* avoid getting hit by machine check */
 198
 199 #if 0
 200         {
 201           unsigned long stat0;
 202           /* Reset status register to avoid losing errors.  */
 203           stat0 = *(vulp)T2_IOCSR;
 204           *(vulp)T2_IOCSR = stat0;
 205           mb();
 206           DBG(("conf_write: T2 ERR was 0x%x\n", stat0));
 207         }
 208 #endif
 209
 210         /* If Type1 access, must set T2 CFG.  */
 211         if (type1) {
 212                 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
 213                 *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
 214                 mb();
 215                 DBG(("conf_write: TYPE1 access\n"));
 216         }
 217         mb();
 218         draina();
 219
 220         mcheck_expected(cpu) = 1;
 221         mb();
 222
 223         /* Access configuration space.  */
 224         *(vuip)addr = value;
 225         mb();
 226         mb();  /* magic */
 227
 228         mcheck_expected(cpu) = 0;
 229         mb();
 230
 231         /* If Type1 access, must reset T2 CFG so normal IO space ops work.  */
 232         if (type1) {
 233                 *(vulp)T2_HAE_3 = t2_cfg;
 234                 mb();
 235         }
 236         DBG(("conf_write(): finished\n"));
 237         __restore_flags(flags);
 238 }
 239
 240 static int
 241 t2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 242 {
 243         unsigned long addr, pci_addr;
 244         unsigned char type1;
 245
 246         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 247                 return PCIBIOS_DEVICE_NOT_FOUND;
 248
 249         addr = (pci_addr << 5) + 0x00 + T2_CONF;
 250         *value = conf_read(addr, type1) >> ((where & 3) * 8);
 251         return PCIBIOS_SUCCESSFUL;
 252 }
 253
 254 static int
 255 t2_read_config_word(struct pci_dev *dev, int where, u16 *value)
 256 {
 257         unsigned long addr, pci_addr;
 258         unsigned char type1;
 259
 260         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 261                 return PCIBIOS_DEVICE_NOT_FOUND;
 262
 263         addr = (pci_addr << 5) + 0x08 + T2_CONF;
 264         *value = conf_read(addr, type1) >> ((where & 3) * 8);
 265         return PCIBIOS_SUCCESSFUL;
 266 }
 267
 268 static int
 269 t2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 270 {
 271         unsigned long addr, pci_addr;
 272         unsigned char type1;
 273
 274         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 275                 return PCIBIOS_DEVICE_NOT_FOUND;
 276
 277         addr = (pci_addr << 5) + 0x18 + T2_CONF;
 278         *value = conf_read(addr, type1);
 279         return PCIBIOS_SUCCESSFUL;
 280 }
 281
 282 static int
 283 t2_write_config(struct pci_dev *dev, int where, u32 value, long mask)
 284 {
 285         unsigned long addr, pci_addr;
 286         unsigned char type1;
 287
 288         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 289                 return PCIBIOS_DEVICE_NOT_FOUND;
 290
 291         addr = (pci_addr << 5) + mask + T2_CONF;
 292         conf_write(addr, value << ((where & 3) * 8), type1);
 293         return PCIBIOS_SUCCESSFUL;
 294 }
 295
 296 static int
 297 t2_write_config_byte(struct pci_dev *dev, int where, u8 value)
 298 {
 299         return t2_write_config(dev, where, value, 0x00);
 300 }
 301
 302 static int
 303 t2_write_config_word(struct pci_dev *dev, int where, u16 value)
 304 {
 305         return t2_write_config(dev, where, value, 0x08);
 306 }
 307
 308 static int
 309 t2_write_config_dword(struct pci_dev *dev, int where, u32 value)
 310 {
 311         return t2_write_config(dev, where, value, 0x18);
 312 }
 313
 314 struct pci_ops t2_pci_ops =
 315 {
 316         read_byte:      t2_read_config_byte,
 317         read_word:      t2_read_config_word,
 318         read_dword:     t2_read_config_dword,
 319         write_byte:     t2_write_config_byte,
 320         write_word:     t2_write_config_word,
 321         write_dword:    t2_write_config_dword
 322 };
 323 \f
 324 void __init
 325 t2_init_arch(unsigned long *mem_start, unsigned long *mem_end)
 326 {
 327         struct pci_controler *hose;
 328         unsigned int i;
 329
 330         for (i = 0; i < NR_CPUS; i++) {
 331                 mcheck_expected(i) = 0;
 332                 mcheck_taken(i) = 0;
 333         }
 334
 335 #if 0
 336         {
 337           /* Set up error reporting.  */
 338           unsigned long t2_err;
 339
 340           t2_err = *(vulp)T2_IOCSR;
 341           t2_err |= (0x1 << 7);   /* master abort */
 342           *(vulp)T2_IOCSR = t2_err;
 343           mb();
 344         }
 345 #endif
 346
 347         printk("t2_init: HBASE was 0x%lx\n", *(vulp)T2_HBASE);
 348 #if 0
 349         printk("t2_init: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
 350                *(vulp)T2_WBASE1,
 351                *(vulp)T2_WMASK1,
 352                *(vulp)T2_TBASE1);
 353         printk("t2_init: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
 354                *(vulp)T2_WBASE2,
 355                *(vulp)T2_WMASK2,
 356                *(vulp)T2_TBASE2);
 357 #endif
 358
 359         /*
 360          * Set up the PCI->physical memory translation windows.
 361          * For now, window 2 is  disabled.  In the future, we may
 362          * want to use it to do scatter/gather DMA.
 363          *
 364          * Window 1 goes at 1 GB and is 1 GB large.
 365          */
 366
 367         /* WARNING!! must correspond to the DMA_WIN params!!! */
 368         *(vulp)T2_WBASE1 = 0x400807ffU;
 369         *(vulp)T2_WMASK1 = 0x3ff00000U;
 370         *(vulp)T2_TBASE1 = 0;
 371
 372         *(vulp)T2_WBASE2 = 0x0;
 373         *(vulp)T2_HBASE = 0x0;
 374
 375         /* Zero HAE.  */
 376         *(vulp)T2_HAE_1 = 0; mb();
 377         *(vulp)T2_HAE_2 = 0; mb();
 378         *(vulp)T2_HAE_3 = 0; mb();
 379 #if 0
 380         *(vulp)T2_HAE_4 = 0; mb(); /* do not touch this */
 381 #endif
 382
 383         /*
 384          * Create our single hose.
 385          */
 386
 387         hose = alloc_pci_controler(mem_start);
 388         hose->io_space = &ioport_resource;
 389         hose->mem_space = &iomem_resource;
 390         hose->config_space = T2_CONF;
 391         hose->index = 0;
 392 }
 393
 394 #define SIC_SEIC (1UL << 33)    /* System Event Clear */
 395
 396 static void
 397 t2_clear_errors(int cpu)
 398 {
 399         struct sable_cpu_csr *cpu_regs;
 400
 401         cpu_regs = (struct sable_cpu_csr *)T2_CPU0_BASE;
 402         if (cpu == 1)
 403                 cpu_regs = (struct sable_cpu_csr *)T2_CPU1_BASE;
 404         if (cpu == 2)
 405                 cpu_regs = (struct sable_cpu_csr *)T2_CPU2_BASE;
 406         if (cpu == 3)
 407                 cpu_regs = (struct sable_cpu_csr *)T2_CPU3_BASE;
 408
 409         cpu_regs->sic &= ~SIC_SEIC;
 410
 411         /* Clear CPU errors.  */
 412         cpu_regs->bcce |= cpu_regs->bcce;
 413         cpu_regs->cbe  |= cpu_regs->cbe;
 414         cpu_regs->bcue |= cpu_regs->bcue;
 415         cpu_regs->dter |= cpu_regs->dter;
 416
 417         *(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
 418         *(vulp)T2_PERR1 |= *(vulp)T2_PERR1;
 419
 420         mb();
 421         mb();  /* magic */
 422 }
 423
 424 void
 425 t2_machine_check(unsigned long vector, unsigned long la_ptr,
 426                  struct pt_regs * regs)
 427 {
 428         int cpu = smp_processor_id();
 429
 430         /* Clear the error before any reporting.  */
 431         mb();
 432         mb();  /* magic */
 433         draina();
 434         t2_clear_errors(cpu);
 435         wrmces(rdmces()|1);     /* ??? */
 436         mb();
 437
 438         process_mcheck_info(vector, la_ptr, regs, "T2", mcheck_expected(cpu));
 439 }