i386/linux/linux-2.3.21/arch/alpha/kernel/sys_rawhide.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_rawhide.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code supporting the RAWHIDE.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/mm.h>
  14 #include <linux/sched.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17
  18 #include <asm/ptrace.h>
  19 #include <asm/system.h>
  20 #include <asm/dma.h>
  21 #include <asm/irq.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/io.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/core_mcpcia.h>
  26
  27 #include "proto.h"
  28 #include "irq_impl.h"
  29 #include "pci_impl.h"
  30 #include "machvec_impl.h"
  31
  32
  33 static void
  34 rawhide_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
  35 {
  36         if (irq >= 40) {
  37                 /* PCI bus 1 with builtin NCR810 SCSI */
  38                 *(vuip)MCPCIA_INT_MASK0(5) =
  39                         (~((mask) >> 40) & 0x00ffffffU) | 0x00fe0000U;
  40                 mb();
  41                 /* ... and read it back to make sure it got written.  */
  42                 *(vuip)MCPCIA_INT_MASK0(5);
  43         }
  44         else if (irq >= 16) {
  45                 /* PCI bus 0 with EISA bridge */
  46                 *(vuip)MCPCIA_INT_MASK0(4) =
  47                         (~((mask) >> 16) & 0x00ffffffU) | 0x00ff0000U;
  48                 mb();
  49                 /* ... and read it back to make sure it got written.  */
  50                 *(vuip)MCPCIA_INT_MASK0(4);
  51         }
  52         else if (irq >= 8)
  53                 outb(mask >> 8, 0xA1);  /* ISA PIC2 */
  54         else
  55                 outb(mask, 0x21);       /* ISA PIC1 */
  56 }
  57
  58 static void
  59 rawhide_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
  60 {
  61         int irq, ack;
  62
  63         ack = irq = (vector - 0x800) >> 4;
  64
  65         /* ??? A 4 bus RAWHIDE has 67 interrupts.  Oops.  We need
  66            something wider than one word for our own internal
  67            manipulations.  */
  68
  69         /*
  70          * The RAWHIDE SRM console reports PCI interrupts with a vector
  71          * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0)
  72          * shows up as IRQ 24, etc, etc. We adjust it down by 8 to have
  73          * it line up with the actual bit numbers from the REQ registers,
  74          * which is how we manage the interrupts/mask. Sigh...
  75          *
  76          * also, PCI #1 interrupts are offset some more... :-(
  77          */
  78         if (irq == 52)
  79                 ack = irq = 56; /* SCSI on PCI 1 is special */
  80         else {
  81                 if (irq >= 24) /* adjust all PCI interrupts down 8 */
  82                         ack = irq = irq - 8;
  83                 if (irq >= 48) /* adjust PCI bus 1 interrupts down another 8 */
  84                         ack = irq = irq - 8;
  85         }
  86
  87         handle_irq(irq, ack, regs);
  88 }
  89
  90 static void __init
  91 rawhide_init_irq(void)
  92 {
  93         STANDARD_INIT_IRQ_PROLOG;
  94
  95         /* HACK ALERT! only PCI busses 0 and 1 are used currently,
  96            (MIDs 4 and 5 respectively) and routing is only to CPU #1*/
  97
  98         *(vuip)MCPCIA_INT_MASK0(4) =
  99                 (~((alpha_irq_mask) >> 16) & 0x00ffffffU) | 0x00ff0000U; mb();
 100         /* ... and read it back to make sure it got written.  */
 101         *(vuip)MCPCIA_INT_MASK0(4);
 102
 103         *(vuip)MCPCIA_INT_MASK0(5) =
 104                 (~((alpha_irq_mask) >> 40) & 0x00ffffffU) | 0x00fe0000U; mb();
 105         /* ... and read it back to make sure it got written.  */
 106         *(vuip)MCPCIA_INT_MASK0(5);
 107
 108         enable_irq(2);
 109 }
 110
 111 /*
 112  * PCI Fixup configuration.
 113  *
 114  * Summary @ MCPCIA_PCI0_INT_REQ:
 115  * Bit      Meaning
 116  * 0        Interrupt Line A from slot 2 PCI0
 117  * 1        Interrupt Line B from slot 2 PCI0
 118  * 2        Interrupt Line C from slot 2 PCI0
 119  * 3        Interrupt Line D from slot 2 PCI0
 120  * 4        Interrupt Line A from slot 3 PCI0
 121  * 5        Interrupt Line B from slot 3 PCI0
 122  * 6        Interrupt Line C from slot 3 PCI0
 123  * 7        Interrupt Line D from slot 3 PCI0
 124  * 8        Interrupt Line A from slot 4 PCI0
 125  * 9        Interrupt Line B from slot 4 PCI0
 126  * 10       Interrupt Line C from slot 4 PCI0
 127  * 11       Interrupt Line D from slot 4 PCI0
 128  * 12       Interrupt Line A from slot 5 PCI0
 129  * 13       Interrupt Line B from slot 5 PCI0
 130  * 14       Interrupt Line C from slot 5 PCI0
 131  * 15       Interrupt Line D from slot 5 PCI0
 132  * 16       EISA interrupt (PCI 0) or SCSI interrupt (PCI 1)
 133  * 17-23    NA
 134  *
 135  * IdSel
 136  *   1   EISA bridge (PCI bus 0 only)
 137  *   2   PCI option slot 2
 138  *   3   PCI option slot 3
 139  *   4   PCI option slot 4
 140  *   5   PCI option slot 5
 141  *
 142  */
 143
 144 static int __init
 145 rawhide_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 146 {
 147         static char irq_tab[5][5] __initlocaldata = {
 148                 /*INT    INTA   INTB   INTC   INTD */
 149                 { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */
 150                 { 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */
 151                 { 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */
 152                 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */
 153                 { 16+12, 16+12, 16+13, 16+14, 16+15}  /* IdSel 5 slot 5 */
 154         };
 155         const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5;
 156
 157         struct pci_controler *hose = dev->sysdata;
 158         int irq = COMMON_TABLE_LOOKUP;
 159         if (irq >= 0)
 160                 irq += 24 * hose->index;
 161         return irq;
 162 }
 163
 164
 165 /*
 166  * The System Vector
 167  */
 168
 169 struct alpha_machine_vector rawhide_mv __initmv = {
 170         vector_name:            "Rawhide",
 171         DO_EV5_MMU,
 172         DO_DEFAULT_RTC,
 173         DO_MCPCIA_IO,
 174         DO_MCPCIA_BUS,
 175         machine_check:          mcpcia_machine_check,
 176         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 177         min_io_address:         DEFAULT_IO_BASE,
 178         min_mem_address:        MCPCIA_DEFAULT_MEM_BASE,
 179
 180         nr_irqs:                64,
 181         irq_probe_mask:         _PROBE_MASK(64),
 182         update_irq_hw:          rawhide_update_irq_hw,
 183         ack_irq:                common_ack_irq,
 184         device_interrupt:       rawhide_srm_device_interrupt,
 185
 186         init_arch:              mcpcia_init_arch,
 187         init_irq:               rawhide_init_irq,
 188         init_pit:               common_init_pit,
 189         init_pci:               common_init_pci,
 190         kill_arch:              common_kill_arch,
 191         pci_map_irq:            rawhide_map_irq,
 192         pci_swizzle:            common_swizzle,
 193 };
 194 ALIAS_MV(rawhide)