i386/linux/linux-2.3.21/drivers/atm/nicstar.h

   1 /******************************************************************************
   2  *
   3  * nicstar.h
   4  *
   5  * Header file for the nicstar device driver.
   6  *
   7  * Author: Rui Prior (rprior@inescn.pt)
   8  * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
   9  *
  10  * (C) INESC 1998
  11  *
  12  ******************************************************************************/
  13
  14
  15 #ifndef _LINUX_NICSTAR_H_
  16 #define _LINUX_NICSTAR_H_
  17
  18
  19 /* Includes *******************************************************************/
  20
  21 #include <linux/types.h>
  22 #include <linux/pci.h>
  23 #include <linux/uio.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/atmdev.h>
  26 #include <linux/atm_nicstar.h>
  27
  28
  29 /* Options ********************************************************************/
  30
  31 #define NS_MAX_CARDS 4          /* Maximum number of NICStAR based cards
  32                                    controlled by the device driver. Must
  33                                    be <= 5 */
  34
  35 #undef RCQ_SUPPORT              /* Do not define this for now */
  36
  37 #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
  38 #define NS_TST_RESERVED 340     /* N. entries reserved for UBR/ABR/VBR */
  39
  40 #define NS_SMBUFSIZE 48         /* 48, 96, 240 or 2048 */
  41 #define NS_LGBUFSIZE 16384      /* 2048, 4096, 8192 or 16384 */
  42 #define NS_RSQSIZE 8192         /* 2048, 4096 or 8192 */
  43 #define NS_VPIBITS 2            /* 0, 1, 2, or 8 */
  44
  45 #define NS_MAX_RCTSIZE 4096     /* Number of entries. 4096 or 16384.
  46                                    Define 4096 only if (all) your card(s)
  47                                    have 32K x 32bit SRAM, in which case
  48                                    setting this to 16384 will just waste a
  49                                    lot of memory.
  50                                    Setting this to 4096 for a card with
  51                                    128K x 32bit SRAM will limit the maximum
  52                                    VCI. */
  53
  54 #define NS_PCI_LATENCY 64       /* Must be a multiple of 32 */
  55
  56         /* Number of buffers initially allocated */
  57 #define NUM_SB 32       /* Must be even */
  58 #define NUM_LB 24       /* Must be even */
  59 #define NUM_HB 8        /* Pre-allocated huge buffers */
  60 #define NUM_IOVB 48     /* Iovec buffers */
  61
  62         /* Lower level for count of buffers */
  63 #define MIN_SB 8        /* Must be even */
  64 #define MIN_LB 8        /* Must be even */
  65 #define MIN_HB 6
  66 #define MIN_IOVB 8
  67
  68         /* Upper level for count of buffers */
  69 #define MAX_SB 64       /* Must be even, <= 508 */
  70 #define MAX_LB 48       /* Must be even, <= 508 */
  71 #define MAX_HB 10
  72 #define MAX_IOVB 80
  73
  74         /* These are the absolute maximum allowed for the ioctl() */
  75 #define TOP_SB 256      /* Must be even, <= 508 */
  76 #define TOP_LB 128      /* Must be even, <= 508 */
  77 #define TOP_HB 64
  78 #define TOP_IOVB 256
  79
  80
  81 #define MAX_TBD_PER_VC 1        /* Number of TBDs before a TSR */
  82 #define MAX_TBD_PER_SCQ 10      /* Only meaningful for variable rate SCQs */
  83
  84 #undef ENABLE_TSQFIE
  85
  86 #define SCQFULL_TIMEOUT (5 * HZ)
  87
  88 #define NS_POLL_PERIOD (HZ)
  89
  90 #define PCR_TOLERANCE (1.0001)
  91
  92
  93
  94 /* ESI stuff ******************************************************************/
  95
  96 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
  97
  98
  99 /* #defines *******************************************************************/
 100
 101 #define NS_IOREMAP_SIZE 4096
 102
 103 #define IDT_25_PCR ((25600000 / 8 - 8000) / 54)
 104
 105 #define BUF_SM 0x00000000       /* These two are used for push_rxbufs() */
 106 #define BUF_LG 0x00000001       /* CMD, Write_FreeBufQ, LBUF bit */
 107
 108 #define NS_HBUFSIZE 65568       /* Size of max. AAL5 PDU */
 109 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
 110                        (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
 111 #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
 112
 113 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
 114 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
 115
 116 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD)        /* 4 bytes */
 117
 118 #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
 119 #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
 120
 121
 122 /* NICStAR structures located in host memory **********************************/
 123
 124
 125
 126 /* RSQ - Receive Status Queue
 127  *
 128  * Written by the NICStAR, read by the device driver.
 129  */
 130
 131 typedef struct ns_rsqe
 132 {
 133    u32 word_1;
 134    u32 buffer_handle;
 135    u32 final_aal5_crc32;
 136    u32 word_4;
 137 } ns_rsqe;
 138
 139 #define ns_rsqe_vpi(ns_rsqep) \
 140         ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
 141 #define ns_rsqe_vci(ns_rsqep) \
 142         (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
 143
 144 #define NS_RSQE_VALID      0x80000000
 145 #define NS_RSQE_NZGFC      0x00004000
 146 #define NS_RSQE_EOPDU      0x00002000
 147 #define NS_RSQE_BUFSIZE    0x00001000
 148 #define NS_RSQE_CONGESTION 0x00000800
 149 #define NS_RSQE_CLP        0x00000400
 150 #define NS_RSQE_CRCERR     0x00000200
 151
 152 #define NS_RSQE_BUFSIZE_SM 0x00000000
 153 #define NS_RSQE_BUFSIZE_LG 0x00001000
 154
 155 #define ns_rsqe_valid(ns_rsqep) \
 156         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
 157 #define ns_rsqe_nzgfc(ns_rsqep) \
 158         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
 159 #define ns_rsqe_eopdu(ns_rsqep) \
 160         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
 161 #define ns_rsqe_bufsize(ns_rsqep) \
 162         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
 163 #define ns_rsqe_congestion(ns_rsqep) \
 164         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
 165 #define ns_rsqe_clp(ns_rsqep) \
 166         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
 167 #define ns_rsqe_crcerr(ns_rsqep) \
 168         (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
 169
 170 #define ns_rsqe_cellcount(ns_rsqep) \
 171         (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
 172 #define ns_rsqe_init(ns_rsqep) \
 173         ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
 174
 175 #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
 176 #define NS_RSQ_ALIGNMENT NS_RSQSIZE
 177
 178
 179
 180 /* RCQ - Raw Cell Queue
 181  *
 182  * Written by the NICStAR, read by the device driver.
 183  */
 184
 185 typedef struct cell_payload
 186 {
 187    u32 word[12];
 188 } cell_payload;
 189
 190 typedef struct ns_rcqe
 191 {
 192    u32 word_1;
 193    u32 word_2;
 194    u32 word_3;
 195    u32 word_4;
 196    cell_payload payload;
 197 } ns_rcqe;
 198
 199 #define NS_RCQE_SIZE 64         /* bytes */
 200
 201 #define ns_rcqe_islast(ns_rcqep) \
 202         (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
 203 #define ns_rcqe_cellheader(ns_rcqep) \
 204         (le32_to_cpu((ns_rcqep)->word_1))
 205 #define ns_rcqe_nextbufhandle(ns_rcqep) \
 206         (le32_to_cpu((ns_rcqep)->word_2))
 207
 208
 209
 210 /* SCQ - Segmentation Channel Queue
 211  *
 212  * Written by the device driver, read by the NICStAR.
 213  */
 214
 215 typedef struct ns_scqe
 216 {
 217    u32 word_1;
 218    u32 word_2;
 219    u32 word_3;
 220    u32 word_4;
 221 } ns_scqe;
 222
 223    /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
 224             or TSR (Transmit Status Requests) */
 225
 226 #define NS_SCQE_TYPE_TBD 0x00000000
 227 #define NS_SCQE_TYPE_TSR 0x80000000
 228
 229
 230 #define NS_TBD_EOPDU 0x40000000
 231 #define NS_TBD_AAL0  0x00000000
 232 #define NS_TBD_AAL34 0x04000000
 233 #define NS_TBD_AAL5  0x08000000
 234
 235 #define NS_TBD_VPI_MASK 0x0FF00000
 236 #define NS_TBD_VCI_MASK 0x000FFFF0
 237 #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
 238
 239 #define NS_TBD_VPI_SHIFT 20
 240 #define NS_TBD_VCI_SHIFT 4
 241
 242 #define ns_tbd_mkword_1(flags, m, n, buflen) \
 243         (cpu_to_le32(flags | m << 23 | n << 16 | buflen))
 244 #define ns_tbd_mkword_1_novbr(flags, buflen) \
 245         (cpu_to_le32(flags | buflen | 0x00810000))
 246 #define ns_tbd_mkword_3(control, pdulen) \
 247         (cpu_to_le32(control << 16 | pdulen))
 248 #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
 249         (cpu_to_le32(gfc << 28 | vpi << 20 | vci << 4 | pt << 1 | clp)))
 250
 251
 252 #define NS_TSR_INTENABLE 0x20000000
 253
 254 #define NS_TSR_SCDISVBR 0xFFFF          /* Use as scdi for VBR SCD */
 255
 256 #define ns_tsr_mkword_1(flags) \
 257         (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
 258 #define ns_tsr_mkword_2(scdi, scqi) \
 259         (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
 260
 261 #define ns_scqe_is_tsr(ns_scqep) \
 262         (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
 263
 264 #define VBR_SCQ_NUM_ENTRIES 512
 265 #define VBR_SCQSIZE 8192
 266 #define CBR_SCQ_NUM_ENTRIES 64
 267 #define CBR_SCQSIZE 1024
 268
 269 #define NS_SCQE_SIZE 16
 270
 271
 272
 273 /* TSQ - Transmit Status Queue
 274  *
 275  * Written by the NICStAR, read by the device driver.
 276  */
 277
 278 typedef struct ns_tsi
 279 {
 280    u32 word_1;
 281    u32 word_2;
 282 } ns_tsi;
 283
 284    /* NOTE: The first word can be a status word copied from the TSR which
 285             originated the TSI, or a timer overflow indicator. In this last
 286             case, the value of the first word is all zeroes. */
 287
 288 #define NS_TSI_EMPTY          0x80000000
 289 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
 290
 291 #define ns_tsi_isempty(ns_tsip) \
 292         (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
 293 #define ns_tsi_gettimestamp(ns_tsip) \
 294         (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
 295
 296 #define ns_tsi_init(ns_tsip) \
 297         ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
 298
 299
 300 #define NS_TSQSIZE 8192
 301 #define NS_TSQ_NUM_ENTRIES 1024
 302 #define NS_TSQ_ALIGNMENT 8192
 303
 304
 305 #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
 306
 307 #define ns_tsi_tmrof(ns_tsip) \
 308         (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
 309 #define ns_tsi_getscdindex(ns_tsip) \
 310         ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
 311 #define ns_tsi_getscqpos(ns_tsip) \
 312         (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
 313
 314
 315
 316 /* NICStAR structures located in local SRAM ***********************************/
 317
 318
 319
 320 /* RCT - Receive Connection Table
 321  *
 322  * Written by both the NICStAR and the device driver.
 323  */
 324
 325 typedef struct ns_rcte
 326 {
 327    u32 word_1;
 328    u32 buffer_handle;
 329    u32 dma_address;
 330    u32 aal5_crc32;
 331 } ns_rcte;
 332
 333 #define NS_RCTE_BSFB            0x00200000  /* Rev. D only */
 334 #define NS_RCTE_NZGFC           0x00100000
 335 #define NS_RCTE_CONNECTOPEN     0x00080000
 336 #define NS_RCTE_AALMASK         0x00070000
 337 #define NS_RCTE_AAL0            0x00000000
 338 #define NS_RCTE_AAL34           0x00010000
 339 #define NS_RCTE_AAL5            0x00020000
 340 #define NS_RCTE_RCQ             0x00030000
 341 #define NS_RCTE_RAWCELLINTEN    0x00008000
 342 #define NS_RCTE_RXCONSTCELLADDR 0x00004000
 343 #define NS_RCTE_BUFFVALID       0x00002000
 344 #define NS_RCTE_FBDSIZE         0x00001000
 345 #define NS_RCTE_EFCI            0x00000800
 346 #define NS_RCTE_CLP             0x00000400
 347 #define NS_RCTE_CRCERROR        0x00000200
 348 #define NS_RCTE_CELLCOUNT_MASK  0x000001FF
 349
 350 #define NS_RCTE_FBDSIZE_SM 0x00000000
 351 #define NS_RCTE_FBDSIZE_LG 0x00001000
 352
 353 #define NS_RCT_ENTRY_SIZE 4     /* Number of dwords */
 354
 355    /* NOTE: We could make macros to contruct the first word of the RCTE,
 356             but that doesn't seem to make much sense... */
 357
 358
 359
 360 /* FBD - Free Buffer Descriptor
 361  *
 362  * Written by the device driver using via the command register.
 363  */
 364
 365 typedef struct ns_fbd
 366 {
 367    u32 buffer_handle;
 368    u32 dma_address;
 369 } ns_fbd;
 370
 371
 372
 373
 374 /* TST - Transmit Schedule Table
 375  *
 376  * Written by the device driver.
 377  */
 378
 379 typedef u32 ns_tste;
 380
 381 #define NS_TST_OPCODE_MASK 0x60000000
 382
 383 #define NS_TST_OPCODE_NULL     0x00000000 /* Insert null cell */
 384 #define NS_TST_OPCODE_FIXED    0x20000000 /* Cell from a fixed rate channel */
 385 #define NS_TST_OPCODE_VARIABLE 0x40000000
 386 #define NS_TST_OPCODE_END      0x60000000 /* Jump */
 387
 388 #define ns_tste_make(opcode, sramad) (opcode | sramad)
 389
 390    /* NOTE:
 391
 392       - When the opcode is FIXED, sramad specifies the SRAM address of the
 393         SCD for that fixed rate channel.
 394       - When the opcode is END, sramad specifies the SRAM address of the
 395         location of the next TST entry to read.
 396     */
 397
 398
 399
 400 /* SCD - Segmentation Channel Descriptor
 401  *
 402  * Written by both the device driver and the NICStAR
 403  */
 404
 405 typedef struct ns_scd
 406 {
 407    u32 word_1;
 408    u32 word_2;
 409    u32 partial_aal5_crc;
 410    u32 reserved;
 411    ns_scqe cache_a;
 412    ns_scqe cache_b;
 413 } ns_scd;
 414
 415 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000         /* Variable rate */
 416 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00         /* Fixed rate */
 417 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
 418 #define NS_SCD_TAIL_MASK_FIX 0x000003F0
 419 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
 420 #define NS_SCD_HEAD_MASK_FIX 0x000003F0
 421 #define NS_SCD_XMITFOREVER   0x02000000
 422
 423    /* NOTE: There are other fields in word 2 of the SCD, but as they should
 424             not be needed in the device driver they are not defined here. */
 425
 426
 427
 428
 429 /* NICStAR local SRAM memory map **********************************************/
 430
 431
 432 #define NS_RCT           0x00000
 433 #define NS_RCT_32_END    0x03FFF
 434 #define NS_RCT_128_END   0x0FFFF
 435 #define NS_UNUSED_32     0x04000
 436 #define NS_UNUSED_128    0x10000
 437 #define NS_UNUSED_END    0x1BFFF
 438 #define NS_TST_FRSCD     0x1C000
 439 #define NS_TST_FRSCD_END 0x1E7DB
 440 #define NS_VRSCD2        0x1E7DC
 441 #define NS_VRSCD2_END    0x1E7E7
 442 #define NS_VRSCD1        0x1E7E8
 443 #define NS_VRSCD1_END    0x1E7F3
 444 #define NS_VRSCD0        0x1E7F4
 445 #define NS_VRSCD0_END    0x1E7FF
 446 #define NS_RXFIFO        0x1E800
 447 #define NS_RXFIFO_END    0x1F7FF
 448 #define NS_SMFBQ         0x1F800
 449 #define NS_SMFBQ_END     0x1FBFF
 450 #define NS_LGFBQ         0x1FC00
 451 #define NS_LGFBQ_END     0x1FFFF
 452
 453
 454
 455 /* NISCtAR operation registers ************************************************/
 456
 457
 458 enum ns_regs
 459 {
 460    DR0 = 0x00,
 461    DR1 = 0x04,
 462    DR2 = 0x08,
 463    DR3 = 0x0C,
 464    CMD = 0x10,
 465    CFG = 0x14,
 466    STAT = 0x18,
 467    RSQB = 0x1C,
 468    RSQT = 0x20,
 469    RSQH = 0x24,
 470    CDC = 0x28,
 471    VPEC = 0x2C,
 472    ICC = 0x30,
 473    RAWCT = 0x34,
 474    TMR = 0x38,
 475    TSTB = 0x3C,
 476    TSQB = 0x40,
 477    TSQT = 0x44,
 478    TSQH = 0x48,
 479    GP = 0x4C,
 480    VPM = 0x50
 481 };
 482
 483
 484 /* NICStAR commands issued to the CMD register ********************************/
 485
 486 #define NS_CMD_NO_OPERATION         0x00000000
 487 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
 488 #define NS_CMD_WRITE_SRAM           0x40000000
 489 #define NS_CMD_READ_SRAM            0x50000000
 490 #define NS_CMD_WRITE_FREEBUFQ       0x60000000
 491 #define NS_CMD_READ_UTILITY         0x80000000
 492 #define NS_CMD_WRITE_UTILITY        0x90000000
 493
 494 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
 495 #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
 496
 497
 498 /* NICStAR configuration bits *************************************************/
 499
 500 #define NS_CFG_SWRST          0x80000000
 501 #define NS_CFG_RXPATH         0x20000000
 502 #define NS_CFG_SMBUFSIZE_MASK 0x18000000
 503 #define NS_CFG_LGBUFSIZE_MASK 0x06000000
 504 #define NS_CFG_EFBIE          0x01000000
 505 #define NS_CFG_RSQSIZE_MASK   0x00C00000
 506 #define NS_CFG_ICACCEPT       0x00200000
 507 #define NS_CFG_IGNOREGFC      0x00100000
 508 #define NS_CFG_VPIBITS_MASK   0x000C0000
 509 #define NS_CFG_RCTSIZE_MASK   0x00030000
 510 #define NS_CFG_VCERRACCEPT    0x00008000
 511 #define NS_CFG_RXINT_MASK     0x00007000
 512 #define NS_CFG_RAWIE          0x00000800
 513 #define NS_CFG_RSQAFIE        0x00000400
 514 #define NS_CFG_RXRM           0x00000200
 515 #define NS_CFG_TMRROIE        0x00000080
 516 #define NS_CFG_TXEN           0x00000020
 517 #define NS_CFG_TXIE           0x00000010
 518 #define NS_CFG_TXURIE         0x00000008
 519 #define NS_CFG_UMODE          0x00000004
 520 #define NS_CFG_TSQFIE         0x00000002
 521 #define NS_CFG_PHYIE          0x00000001
 522
 523 #define NS_CFG_SMBUFSIZE_48    0x00000000
 524 #define NS_CFG_SMBUFSIZE_96    0x08000000
 525 #define NS_CFG_SMBUFSIZE_240   0x10000000
 526 #define NS_CFG_SMBUFSIZE_2048  0x18000000
 527
 528 #define NS_CFG_LGBUFSIZE_2048  0x00000000
 529 #define NS_CFG_LGBUFSIZE_4096  0x02000000
 530 #define NS_CFG_LGBUFSIZE_8192  0x04000000
 531 #define NS_CFG_LGBUFSIZE_16384 0x06000000
 532
 533 #define NS_CFG_RSQSIZE_2048 0x00000000
 534 #define NS_CFG_RSQSIZE_4096 0x00400000
 535 #define NS_CFG_RSQSIZE_8192 0x00800000
 536
 537 #define NS_CFG_VPIBITS_0 0x00000000
 538 #define NS_CFG_VPIBITS_1 0x00040000
 539 #define NS_CFG_VPIBITS_2 0x00080000
 540 #define NS_CFG_VPIBITS_8 0x000C0000
 541
 542 #define NS_CFG_RCTSIZE_4096_ENTRIES  0x00000000
 543 #define NS_CFG_RCTSIZE_8192_ENTRIES  0x00010000
 544 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
 545
 546 #define NS_CFG_RXINT_NOINT   0x00000000
 547 #define NS_CFG_RXINT_NODELAY 0x00001000
 548 #define NS_CFG_RXINT_314US   0x00002000
 549 #define NS_CFG_RXINT_624US   0x00003000
 550 #define NS_CFG_RXINT_899US   0x00004000
 551
 552
 553 /* NICStAR STATus bits ********************************************************/
 554
 555 #define NS_STAT_SFBQC_MASK 0xFF000000
 556 #define NS_STAT_LFBQC_MASK 0x00FF0000
 557 #define NS_STAT_TSIF       0x00008000
 558 #define NS_STAT_TXICP      0x00004000
 559 #define NS_STAT_TSQF       0x00001000
 560 #define NS_STAT_TMROF      0x00000800
 561 #define NS_STAT_PHYI       0x00000400
 562 #define NS_STAT_CMDBZ      0x00000200
 563 #define NS_STAT_SFBQF      0x00000100
 564 #define NS_STAT_LFBQF      0x00000080
 565 #define NS_STAT_RSQF       0x00000040
 566 #define NS_STAT_EOPDU      0x00000020
 567 #define NS_STAT_RAWCF      0x00000010
 568 #define NS_STAT_SFBQE      0x00000008
 569 #define NS_STAT_LFBQE      0x00000004
 570 #define NS_STAT_RSQAF      0x00000002
 571
 572 #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
 573 #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
 574
 575
 576
 577 /* #defines which depend on other #defines ************************************/
 578
 579
 580 #define NS_TST0 NS_TST_FRSCD
 581 #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
 582
 583 #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
 584 #define NS_FRSCD_SIZE 12        /* 12 dwords */
 585 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
 586
 587 #if (NS_SMBUFSIZE == 48)
 588 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
 589 #elif (NS_SMBUFSIZE == 96)
 590 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
 591 #eliif (NS_SMBUFSIZE == 240)
 592 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
 593 #elif (NS_SMBUFSIZE == 2048)
 594 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
 595 #else
 596 #error NS_SMBUFSIZE is incorrect in nicstar.h
 597 #endif /* NS_SMBUFSIZE */
 598
 599 #if (NS_LGBUFSIZE == 2048)
 600 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
 601 #elif (NS_LGBUFSIZE == 4096)
 602 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
 603 #eliif (NS_LGBUFSIZE == 8192)
 604 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
 605 #elif (NS_LGBUFSIZE == 16384)
 606 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
 607 #else
 608 #error NS_LGBUFSIZE is incorrect in nicstar.h
 609 #endif /* NS_LGBUFSIZE */
 610
 611 #if (NS_RSQSIZE == 2048)
 612 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
 613 #elif (NS_RSQSIZE == 4096)
 614 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
 615 #elif (NS_RSQSIZE == 8192)
 616 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
 617 #else
 618 #error NS_RSQSIZE is incorrect in nicstar.h
 619 #endif /* NS_RSQSIZE */
 620
 621 #if (NS_VPIBITS == 0)
 622 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
 623 #elif (NS_VPIBITS == 1)
 624 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
 625 #elif (NS_VPIBITS == 2)
 626 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
 627 #elif (NS_VPIBITS == 8)
 628 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
 629 #else
 630 #error NS_VPIBITS is incorrect in nicstar.h
 631 #endif /* NS_VPIBITS */
 632
 633 #ifdef RCQ_SUPPORT
 634 #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
 635 #else
 636 #define NS_CFG_RAWIE_OPT 0x00000000
 637 #endif /* RCQ_SUPPORT */
 638
 639 #ifdef ENABLE_TSQFIE
 640 #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
 641 #else
 642 #define NS_CFG_TSQFIE_OPT 0x00000000
 643 #endif /* ENABLE_TSQFIE */
 644
 645
 646 /* PCI stuff ******************************************************************/
 647
 648 #ifndef PCI_VENDOR_ID_IDT
 649 #define PCI_VENDOR_ID_IDT 0x111D
 650 #endif /* PCI_VENDOR_ID_IDT */
 651
 652 #ifndef PCI_DEVICE_ID_IDT_IDT77201
 653 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
 654 #endif /* PCI_DEVICE_ID_IDT_IDT77201 */
 655
 656
 657
 658 /* Device driver structures ***************************************************/
 659
 660
 661 typedef struct tsq_info
 662 {
 663    void *org;
 664    ns_tsi *base;
 665    ns_tsi *next;
 666    ns_tsi *last;
 667 } tsq_info;
 668
 669
 670 typedef struct scq_info
 671 {
 672    void *org;
 673    ns_scqe *base;
 674    ns_scqe *last;
 675    ns_scqe *next;
 676    volatile ns_scqe *tail;              /* Not related to the nicstar register */
 677    unsigned num_entries;
 678    struct sk_buff **skb;                /* Pointer to an array of pointers
 679                                            to the sk_buffs used for tx */
 680    u32 scd;                             /* SRAM address of the corresponding
 681                                            SCD */
 682    int tbd_count;                       /* Only meaningful on variable rate */
 683    wait_queue_head_t scqfull_waitq;
 684    volatile char full;                  /* SCQ full indicator */
 685 } scq_info;
 686
 687
 688
 689 typedef struct rsq_info
 690 {
 691    void *org;
 692    ns_rsqe *base;
 693    ns_rsqe *next;
 694    ns_rsqe *last;
 695 } rsq_info;
 696
 697
 698 typedef struct skb_pool
 699 {
 700    volatile int count;                  /* number of buffers in the queue */
 701    struct sk_buff_head queue;
 702 } skb_pool;
 703
 704 /* NOTE: for small and large buffer pools, the count is not used, as the
 705          actual value used for buffer management is the one read from the
 706          card. */
 707
 708
 709 typedef struct vc_map
 710 {
 711    volatile int tx:1;                           /* TX vc? */
 712    volatile int rx:1;                           /* RX vc? */
 713    struct atm_vcc *tx_vcc, *rx_vcc;
 714    struct sk_buff *rx_iov;              /* RX iovector skb */
 715    scq_info *scq;                       /* To keep track of the SCQ */
 716    u32 cbr_scd;                         /* SRAM address of the corresponding
 717                                            SCD. 0x00000000 for UBR/VBR/ABR */
 718    int tbd_count;
 719 } vc_map;
 720
 721
 722 typedef struct ns_dev
 723 {
 724    int index;                           /* Card ID to the device driver */
 725    int sram_size;                       /* In k x 32bit words. 32 or 128 */
 726    u32 membase;                         /* Card's memory base address */
 727    unsigned long max_pcr;
 728    int rct_size;                        /* Number of entries */
 729    int vpibits;
 730    int vcibits;
 731    struct pci_dev *pcidev;
 732    struct atm_dev *atmdev;
 733    tsq_info tsq;
 734    rsq_info rsq;
 735    scq_info *scq0, *scq1, *scq2;        /* VBR SCQs */
 736    skb_pool sbpool;                     /* Small buffers */
 737    skb_pool lbpool;                     /* Large buffers */
 738    skb_pool hbpool;                     /* Pre-allocated huge buffers */
 739    skb_pool iovpool;                    /* iovector buffers */
 740    volatile int efbie;                  /* Empty free buf. queue int. enabled */
 741    volatile u32 tst_addr;               /* SRAM address of the TST in use */
 742    volatile int tst_free_entries;
 743    vc_map vcmap[NS_MAX_RCTSIZE];
 744    vc_map *tste2vc[NS_TST_NUM_ENTRIES];
 745    vc_map *scd2vc[NS_FRSCD_NUM];
 746    buf_nr sbnr;
 747    buf_nr lbnr;
 748    buf_nr hbnr;
 749    buf_nr iovnr;
 750    int sbfqc;
 751    int lbfqc;
 752    u32 sm_handle;
 753    u32 sm_addr;
 754    u32 lg_handle;
 755    u32 lg_addr;
 756    struct sk_buff *rcbuf;               /* Current raw cell buffer */
 757    u32 rawch;                           /* Raw cell queue head */
 758    unsigned intcnt;                     /* Interrupt counter */
 759    volatile int in_handler: 1;
 760    volatile int in_poll: 1;
 761 } ns_dev;
 762
 763
 764    /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
 765             CBR vc. If the entry is not allocated, it must be NULL.
 766
 767             There are two TSTs so the driver can modify them on the fly
 768             without stopping the transmission.
 769
 770             scd2vc allows us to find out unused fixed rate SCDs, because
 771             they must have a NULL pointer here. */
 772
 773
 774 #endif /* _LINUX_NICSTAR_H_ */