i386/linux/linux-2.3.21/drivers/char/drm/gamma_dma.c

   1 /* gamma_dma.c -- DMA support for GMX 2000 -*- linux-c -*-
   2  * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com
   3  * Revised: Fri Aug 20 11:31:45 1999 by faith@precisioninsight.com
   4  *
   5  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * $PI: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/generic/gamma_dma.c,v 1.8 1999/08/30 13:05:00 faith Exp $
  28  * $XFree86$
  29  *
  30  */
  31
  32 #define __NO_VERSION__
  33 #include "drmP.h"
  34 #include "gamma_drv.h"
  35
  36 #include <linux/interrupt.h>    /* For task queue support */
  37
  38
  39 /* WARNING!!! MAGIC NUMBER!!!  The number of regions already added to the
  40    kernel must be specified here.  Currently, the number is 2.  This must
  41    match the order the X server uses for instantiating register regions ,
  42    or must be passed in a new ioctl. */
  43 #define GAMMA_REG(reg)                                             \
  44         (2                                                         \
  45          + ((reg < 0x1000)                                         \
  46             ? 0                                                    \
  47             : ((reg < 0x10000) ? 1 : ((reg < 0x11000) ? 2 : 3))))
  48
  49 #define GAMMA_OFF(reg)                                             \
  50         ((reg < 0x1000)                                            \
  51          ? reg                                                     \
  52          : ((reg < 0x10000)                                        \
  53             ? (reg - 0x1000)                                       \
  54             : ((reg < 0x11000)                                     \
  55                ? (reg - 0x10000)                                   \
  56                : (reg - 0x11000))))
  57
  58 #define GAMMA_BASE(reg)  ((unsigned long)dev->maplist[GAMMA_REG(reg)]->handle)
  59 #define GAMMA_ADDR(reg)  (GAMMA_BASE(reg) + GAMMA_OFF(reg))
  60 #define GAMMA_DEREF(reg) *(__volatile__ int *)GAMMA_ADDR(reg)
  61 #define GAMMA_READ(reg)  GAMMA_DEREF(reg)
  62 #define GAMMA_WRITE(reg,val) do { GAMMA_DEREF(reg) = val; } while (0)
  63
  64 #define GAMMA_BROADCASTMASK    0x9378
  65 #define GAMMA_COMMANDINTENABLE 0x0c48
  66 #define GAMMA_DMAADDRESS       0x0028
  67 #define GAMMA_DMACOUNT         0x0030
  68 #define GAMMA_FILTERMODE       0x8c00
  69 #define GAMMA_GCOMMANDINTFLAGS 0x0c50
  70 #define GAMMA_GCOMMANDMODE     0x0c40
  71 #define GAMMA_GCOMMANDSTATUS   0x0c60
  72 #define GAMMA_GDELAYTIMER      0x0c38
  73 #define GAMMA_GDMACONTROL      0x0060
  74 #define GAMMA_GINTENABLE       0x0808
  75 #define GAMMA_GINTFLAGS        0x0810
  76 #define GAMMA_INFIFOSPACE      0x0018
  77 #define GAMMA_OUTFIFOWORDS     0x0020
  78 #define GAMMA_OUTPUTFIFO       0x2000
  79 #define GAMMA_SYNC             0x8c40
  80 #define GAMMA_SYNC_TAG         0x0188
  81
  82 static inline void gamma_dma_dispatch(drm_device_t *dev, unsigned long address,
  83                                       unsigned long length)
  84 {
  85         GAMMA_WRITE(GAMMA_DMAADDRESS, virt_to_phys((void *)address));
  86         while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4)
  87                 ;
  88         GAMMA_WRITE(GAMMA_DMACOUNT, length / 4);
  89 }
  90
  91 static inline void gamma_dma_quiescent(drm_device_t *dev)
  92 {
  93         while (GAMMA_READ(GAMMA_DMACOUNT))
  94                 ;
  95         while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
  96                 ;
  97         GAMMA_WRITE(GAMMA_BROADCASTMASK, 3);
  98         GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
  99         GAMMA_WRITE(GAMMA_SYNC, 0);
 100
 101                                 /* Read from first MX */
 102         do {
 103                 while (!GAMMA_READ(GAMMA_OUTFIFOWORDS))
 104                         ;
 105         } while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG);
 106
 107
 108                                 /* Read from second MX */
 109         do {
 110                 while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000))
 111                         ;
 112         } while (GAMMA_READ(GAMMA_OUTPUTFIFO + 0x10000) != GAMMA_SYNC_TAG);
 113 }
 114
 115 static inline void gamma_dma_ready(drm_device_t *dev)
 116 {
 117         while (GAMMA_READ(GAMMA_DMACOUNT))
 118                 ;
 119 }
 120
 121 static inline int gamma_dma_is_ready(drm_device_t *dev)
 122 {
 123         return !GAMMA_READ(GAMMA_DMACOUNT);
 124 }
 125
 126 static void gamma_dma_service(int irq, void *device, struct pt_regs *regs)
 127 {
 128         drm_device_t     *dev = (drm_device_t *)device;
 129         drm_device_dma_t *dma = dev->dma;
 130
 131         atomic_inc(&dev->total_irq);
 132         GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */
 133         GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8);
 134         GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001);
 135         if (gamma_dma_is_ready(dev)) {
 136                                 /* Free previous buffer */
 137                 if (test_and_set_bit(0, &dev->dma_flag)) {
 138                         atomic_inc(&dma->total_missed_free);
 139                         return;
 140                 }
 141                 if (dma->this_buffer) {
 142                         drm_free_buffer(dev, dma->this_buffer);
 143                         dma->this_buffer = NULL;
 144                 }
 145                 clear_bit(0, &dev->dma_flag);
 146
 147                                 /* Dispatch new buffer */
 148                 queue_task(&dev->tq, &tq_immediate);
 149                 mark_bh(IMMEDIATE_BH);
 150         }
 151 }
 152
 153 /* Only called by gamma_dma_schedule. */
 154 static int gamma_do_dma(drm_device_t *dev, int locked)
 155 {
 156         unsigned long    address;
 157         unsigned long    length;
 158         drm_buf_t        *buf;
 159         int              retcode = 0;
 160         drm_device_dma_t *dma = dev->dma;
 161 #if DRM_DMA_HISTOGRAM
 162         cycles_t         dma_start, dma_stop;
 163 #endif
 164
 165         if (test_and_set_bit(0, &dev->dma_flag)) {
 166                 atomic_inc(&dma->total_missed_dma);
 167                 return -EBUSY;
 168         }
 169
 170 #if DRM_DMA_HISTOGRAM
 171         dma_start = get_cycles();
 172 #endif
 173
 174         if (!dma->next_buffer) {
 175                 DRM_ERROR("No next_buffer\n");
 176                 clear_bit(0, &dev->dma_flag);
 177                 return -EINVAL;
 178         }
 179
 180         buf     = dma->next_buffer;
 181         address = (unsigned long)buf->address;
 182         length  = buf->used;
 183
 184         DRM_DEBUG("context %d, buffer %d (%ld bytes)\n",
 185                   buf->context, buf->idx, length);
 186
 187         if (buf->list == DRM_LIST_RECLAIM) {
 188                 drm_clear_next_buffer(dev);
 189                 drm_free_buffer(dev, buf);
 190                 clear_bit(0, &dev->dma_flag);
 191                 return -EINVAL;
 192         }
 193
 194         if (!length) {
 195                 DRM_ERROR("0 length buffer\n");
 196                 drm_clear_next_buffer(dev);
 197                 drm_free_buffer(dev, buf);
 198                 clear_bit(0, &dev->dma_flag);
 199                 return 0;
 200         }
 201
 202         if (!gamma_dma_is_ready(dev)) {
 203                 clear_bit(0, &dev->dma_flag);
 204                 return -EBUSY;
 205         }
 206
 207         if (buf->while_locked) {
 208                 if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
 209                         DRM_ERROR("Dispatching buffer %d from pid %d"
 210                                   " \"while locked\", but no lock held\n",
 211                                   buf->idx, buf->pid);
 212                 }
 213         } else {
 214                 if (!locked && !drm_lock_take(&dev->lock.hw_lock->lock,
 215                                               DRM_KERNEL_CONTEXT)) {
 216                         atomic_inc(&dma->total_missed_lock);
 217                         clear_bit(0, &dev->dma_flag);
 218                         return -EBUSY;
 219                 }
 220         }
 221
 222         if (dev->last_context != buf->context
 223             && !(dev->queuelist[buf->context]->flags
 224                  & _DRM_CONTEXT_PRESERVED)) {
 225                                 /* PRE: dev->last_context != buf->context */
 226                 if (drm_context_switch(dev, dev->last_context, buf->context)) {
 227                         drm_clear_next_buffer(dev);
 228                         drm_free_buffer(dev, buf);
 229                 }
 230                 retcode = -EBUSY;
 231                 goto cleanup;
 232
 233                                 /* POST: we will wait for the context
 234                                    switch and will dispatch on a later call
 235                                    when dev->last_context == buf->context.
 236                                    NOTE WE HOLD THE LOCK THROUGHOUT THIS
 237                                    TIME! */
 238         }
 239
 240         drm_clear_next_buffer(dev);
 241         buf->pending     = 1;
 242         buf->waiting     = 0;
 243         buf->list        = DRM_LIST_PEND;
 244 #if DRM_DMA_HISTOGRAM
 245         buf->time_dispatched = get_cycles();
 246 #endif
 247
 248         gamma_dma_dispatch(dev, address, length);
 249         drm_free_buffer(dev, dma->this_buffer);
 250         dma->this_buffer = buf;
 251
 252         atomic_add(length, &dma->total_bytes);
 253         atomic_inc(&dma->total_dmas);
 254
 255         if (!buf->while_locked && !dev->context_flag && !locked) {
 256                 if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
 257                                   DRM_KERNEL_CONTEXT)) {
 258                         DRM_ERROR("\n");
 259                 }
 260         }
 261 cleanup:
 262
 263         clear_bit(0, &dev->dma_flag);
 264
 265 #if DRM_DMA_HISTOGRAM
 266         dma_stop = get_cycles();
 267         atomic_inc(&dev->histo.dma[drm_histogram_slot(dma_stop - dma_start)]);
 268 #endif
 269
 270         return retcode;
 271 }
 272
 273 static void gamma_dma_schedule_timer_wrapper(unsigned long dev)
 274 {
 275         gamma_dma_schedule((drm_device_t *)dev, 0);
 276 }
 277
 278 static void gamma_dma_schedule_tq_wrapper(void *dev)
 279 {
 280         gamma_dma_schedule(dev, 0);
 281 }
 282
 283 int gamma_dma_schedule(drm_device_t *dev, int locked)
 284 {
 285         int              next;
 286         drm_queue_t      *q;
 287         drm_buf_t        *buf;
 288         int              retcode   = 0;
 289         int              processed = 0;
 290         int              missed;
 291         int              expire    = 20;
 292         drm_device_dma_t *dma      = dev->dma;
 293 #if DRM_DMA_HISTOGRAM
 294         cycles_t         schedule_start;
 295 #endif
 296
 297         if (test_and_set_bit(0, &dev->interrupt_flag)) {
 298                                 /* Not reentrant */
 299                 atomic_inc(&dma->total_missed_sched);
 300                 return -EBUSY;
 301         }
 302         missed = atomic_read(&dma->total_missed_sched);
 303
 304 #if DRM_DMA_HISTOGRAM
 305         schedule_start = get_cycles();
 306 #endif
 307
 308 again:
 309         if (dev->context_flag) {
 310                 clear_bit(0, &dev->interrupt_flag);
 311                 return -EBUSY;
 312         }
 313         if (dma->next_buffer) {
 314                                 /* Unsent buffer that was previously
 315                                    selected, but that couldn't be sent
 316                                    because the lock could not be obtained
 317                                    or the DMA engine wasn't ready.  Try
 318                                    again. */
 319                 atomic_inc(&dma->total_tried);
 320                 if (!(retcode = gamma_do_dma(dev, locked))) {
 321                         atomic_inc(&dma->total_hit);
 322                         ++processed;
 323                 }
 324         } else {
 325                 do {
 326                         next = drm_select_queue(dev,
 327                                              gamma_dma_schedule_timer_wrapper);
 328                         if (next >= 0) {
 329                                 q   = dev->queuelist[next];
 330                                 buf = drm_waitlist_get(&q->waitlist);
 331                                 dma->next_buffer = buf;
 332                                 dma->next_queue  = q;
 333                                 if (buf && buf->list == DRM_LIST_RECLAIM) {
 334                                         drm_clear_next_buffer(dev);
 335                                         drm_free_buffer(dev, buf);
 336                                 }
 337                         }
 338                 } while (next >= 0 && !dma->next_buffer);
 339                 if (dma->next_buffer) {
 340                         if (!(retcode = gamma_do_dma(dev, locked))) {
 341                                 ++processed;
 342                         }
 343                 }
 344         }
 345
 346         if (--expire) {
 347                 if (missed != atomic_read(&dma->total_missed_sched)) {
 348                         atomic_inc(&dma->total_lost);
 349                         if (gamma_dma_is_ready(dev)) goto again;
 350                 }
 351                 if (processed && gamma_dma_is_ready(dev)) {
 352                         atomic_inc(&dma->total_lost);
 353                         processed = 0;
 354                         goto again;
 355                 }
 356         }
 357
 358         clear_bit(0, &dev->interrupt_flag);
 359
 360 #if DRM_DMA_HISTOGRAM
 361         atomic_inc(&dev->histo.schedule[drm_histogram_slot(get_cycles()
 362                                                            - schedule_start)]);
 363 #endif
 364         return retcode;
 365 }
 366
 367 static int gamma_dma_priority(drm_device_t *dev, drm_dma_t *d)
 368 {
 369         unsigned long     address;
 370         unsigned long     length;
 371         int               must_free = 0;
 372         int               retcode   = 0;
 373         int               i;
 374         int               idx;
 375         drm_buf_t         *buf;
 376         drm_buf_t         *last_buf = NULL;
 377         drm_device_dma_t  *dma      = dev->dma;
 378         DECLARE_WAITQUEUE(entry, current);
 379
 380                                 /* Turn off interrupt handling */
 381         while (test_and_set_bit(0, &dev->interrupt_flag)) {
 382                 schedule();
 383                 if (signal_pending(current)) return -EINTR;
 384         }
 385         if (!(d->flags & _DRM_DMA_WHILE_LOCKED)) {
 386                 while (!drm_lock_take(&dev->lock.hw_lock->lock,
 387                                       DRM_KERNEL_CONTEXT)) {
 388                         schedule();
 389                         if (signal_pending(current)) {
 390                                 clear_bit(0, &dev->interrupt_flag);
 391                                 return -EINTR;
 392                         }
 393                 }
 394                 ++must_free;
 395         }
 396         atomic_inc(&dma->total_prio);
 397
 398         for (i = 0; i < d->send_count; i++) {
 399                 idx = d->send_indices[i];
 400                 if (idx < 0 || idx >= dma->buf_count) {
 401                         DRM_ERROR("Index %d (of %d max)\n",
 402                                   d->send_indices[i], dma->buf_count - 1);
 403                         continue;
 404                 }
 405                 buf = dma->buflist[ idx ];
 406                 if (buf->pid != current->pid) {
 407                         DRM_ERROR("Process %d using buffer owned by %d\n",
 408                                   current->pid, buf->pid);
 409                         retcode = -EINVAL;
 410                         goto cleanup;
 411                 }
 412                 if (buf->list != DRM_LIST_NONE) {
 413                         DRM_ERROR("Process %d using %d's buffer on list %d\n",
 414                                   current->pid, buf->pid, buf->list);
 415                         retcode = -EINVAL;
 416                         goto cleanup;
 417                 }
 418                                 /* This isn't a race condition on
 419                                    buf->list, since our concern is the
 420                                    buffer reclaim during the time the
 421                                    process closes the /dev/drm? handle, so
 422                                    it can't also be doing DMA. */
 423                 buf->list         = DRM_LIST_PRIO;
 424                 buf->used         = d->send_sizes[i];
 425                 buf->context      = d->context;
 426                 buf->while_locked = d->flags & _DRM_DMA_WHILE_LOCKED;
 427                 address           = (unsigned long)buf->address;
 428                 length            = buf->used;
 429                 if (!length) {
 430                         DRM_ERROR("0 length buffer\n");
 431                 }
 432                 if (buf->pending) {
 433                         DRM_ERROR("Sending pending buffer:"
 434                                   " buffer %d, offset %d\n",
 435                                   d->send_indices[i], i);
 436                         retcode = -EINVAL;
 437                         goto cleanup;
 438                 }
 439                 if (buf->waiting) {
 440                         DRM_ERROR("Sending waiting buffer:"
 441                                   " buffer %d, offset %d\n",
 442                                   d->send_indices[i], i);
 443                         retcode = -EINVAL;
 444                         goto cleanup;
 445                 }
 446                 buf->pending = 1;
 447
 448                 if (dev->last_context != buf->context
 449                     && !(dev->queuelist[buf->context]->flags
 450                          & _DRM_CONTEXT_PRESERVED)) {
 451                         add_wait_queue(&dev->context_wait, &entry);
 452                         current->state = TASK_INTERRUPTIBLE;
 453                                 /* PRE: dev->last_context != buf->context */
 454                         drm_context_switch(dev, dev->last_context,
 455                                            buf->context);
 456                                 /* POST: we will wait for the context
 457                                    switch and will dispatch on a later call
 458                                    when dev->last_context == buf->context.
 459                                    NOTE WE HOLD THE LOCK THROUGHOUT THIS
 460                                    TIME! */
 461                         schedule();
 462                         current->state = TASK_RUNNING;
 463                         remove_wait_queue(&dev->context_wait, &entry);
 464                         if (signal_pending(current)) {
 465                                 retcode = -EINTR;
 466                                 goto cleanup;
 467                         }
 468                         if (dev->last_context != buf->context) {
 469                                 DRM_ERROR("Context mismatch: %d %d\n",
 470                                           dev->last_context,
 471                                           buf->context);
 472                         }
 473                 }
 474
 475 #if DRM_DMA_HISTOGRAM
 476                 buf->time_queued     = get_cycles();
 477                 buf->time_dispatched = buf->time_queued;
 478 #endif
 479                 gamma_dma_dispatch(dev, address, length);
 480                 atomic_add(length, &dma->total_bytes);
 481                 atomic_inc(&dma->total_dmas);
 482
 483                 if (last_buf) {
 484                         drm_free_buffer(dev, last_buf);
 485                 }
 486                 last_buf = buf;
 487         }
 488
 489
 490 cleanup:
 491         if (last_buf) {
 492                 gamma_dma_ready(dev);
 493                 drm_free_buffer(dev, last_buf);
 494         }
 495
 496         if (must_free && !dev->context_flag) {
 497                 if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
 498                                   DRM_KERNEL_CONTEXT)) {
 499                         DRM_ERROR("\n");
 500                 }
 501         }
 502         clear_bit(0, &dev->interrupt_flag);
 503         return retcode;
 504 }
 505
 506 static int gamma_dma_send_buffers(drm_device_t *dev, drm_dma_t *d)
 507 {
 508         DECLARE_WAITQUEUE(entry, current);
 509         drm_buf_t         *last_buf = NULL;
 510         int               retcode   = 0;
 511         drm_device_dma_t  *dma      = dev->dma;
 512
 513         if (d->flags & _DRM_DMA_BLOCK) {
 514                 last_buf = dma->buflist[d->send_indices[d->send_count-1]];
 515                 add_wait_queue(&last_buf->dma_wait, &entry);
 516         }
 517
 518         if ((retcode = drm_dma_enqueue(dev, d))) {
 519                 if (d->flags & _DRM_DMA_BLOCK)
 520                         remove_wait_queue(&last_buf->dma_wait, &entry);
 521                 return retcode;
 522         }
 523
 524         gamma_dma_schedule(dev, 0);
 525
 526         if (d->flags & _DRM_DMA_BLOCK) {
 527                 DRM_DEBUG("%d waiting\n", current->pid);
 528                 current->state = TASK_INTERRUPTIBLE;
 529                 for (;;) {
 530                         if (!last_buf->waiting
 531                             && !last_buf->pending)
 532                                 break; /* finished */
 533                         schedule();
 534                         if (signal_pending(current)) {
 535                                 retcode = -EINTR; /* Can't restart */
 536                                 break;
 537                         }
 538                 }
 539                 current->state = TASK_RUNNING;
 540                 DRM_DEBUG("%d running\n", current->pid);
 541                 remove_wait_queue(&last_buf->dma_wait, &entry);
 542                 if (!retcode
 543                     || (last_buf->list==DRM_LIST_PEND && !last_buf->pending)) {
 544                         if (!waitqueue_active(&last_buf->dma_wait)) {
 545                                 drm_free_buffer(dev, last_buf);
 546                         }
 547                 }
 548                 if (retcode) {
 549                         DRM_ERROR("ctx%d w%d p%d c%d i%d l%d %d/%d\n",
 550                                   d->context,
 551                                   last_buf->waiting,
 552                                   last_buf->pending,
 553                                   DRM_WAITCOUNT(dev, d->context),
 554                                   last_buf->idx,
 555                                   last_buf->list,
 556                                   last_buf->pid,
 557                                   current->pid);
 558                 }
 559         }
 560         return retcode;
 561 }
 562
 563 int gamma_dma(struct inode *inode, struct file *filp, unsigned int cmd,
 564               unsigned long arg)
 565 {
 566         drm_file_t        *priv     = filp->private_data;
 567         drm_device_t      *dev      = priv->dev;
 568         drm_device_dma_t  *dma      = dev->dma;
 569         int               retcode   = 0;
 570         drm_dma_t         d;
 571
 572         copy_from_user_ret(&d, (drm_dma_t *)arg, sizeof(d), -EFAULT);
 573         DRM_DEBUG("%d %d: %d send, %d req\n",
 574                   current->pid, d.context, d.send_count, d.request_count);
 575
 576         if (d.context == DRM_KERNEL_CONTEXT || d.context >= dev->queue_slots) {
 577                 DRM_ERROR("Process %d using context %d\n",
 578                           current->pid, d.context);
 579                 return -EINVAL;
 580         }
 581         if (d.send_count < 0 || d.send_count > dma->buf_count) {
 582                 DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n",
 583                           current->pid, d.send_count, dma->buf_count);
 584                 return -EINVAL;
 585         }
 586         if (d.request_count < 0 || d.request_count > dma->buf_count) {
 587                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
 588                           current->pid, d.request_count, dma->buf_count);
 589                 return -EINVAL;
 590         }
 591
 592         if (d.send_count) {
 593                 if (d.flags & _DRM_DMA_PRIORITY)
 594                         retcode = gamma_dma_priority(dev, &d);
 595                 else
 596                         retcode = gamma_dma_send_buffers(dev, &d);
 597         }
 598
 599         d.granted_count = 0;
 600
 601         if (!retcode && d.request_count) {
 602                 retcode = drm_dma_get_buffers(dev, &d);
 603         }
 604
 605         DRM_DEBUG("%d returning, granted = %d\n",
 606                   current->pid, d.granted_count);
 607         copy_to_user_ret((drm_dma_t *)arg, &d, sizeof(d), -EFAULT);
 608
 609         return retcode;
 610 }
 611
 612 int gamma_irq_install(drm_device_t *dev, int irq)
 613 {
 614         int retcode;
 615
 616         if (!irq)     return -EINVAL;
 617
 618         down(&dev->struct_sem);
 619         if (dev->irq) {
 620                 up(&dev->struct_sem);
 621                 return -EBUSY;
 622         }
 623         dev->irq = irq;
 624         up(&dev->struct_sem);
 625
 626         DRM_DEBUG("%d\n", irq);
 627
 628         dev->context_flag     = 0;
 629         dev->interrupt_flag   = 0;
 630         dev->dma_flag         = 0;
 631
 632         dev->dma->next_buffer = NULL;
 633         dev->dma->next_queue  = NULL;
 634         dev->dma->this_buffer = NULL;
 635
 636         dev->tq.next          = NULL;
 637         dev->tq.sync          = 0;
 638         dev->tq.routine       = gamma_dma_schedule_tq_wrapper;
 639         dev->tq.data          = dev;
 640
 641
 642                                 /* Before installing handler */
 643         GAMMA_WRITE(GAMMA_GCOMMANDMODE, 0);
 644         GAMMA_WRITE(GAMMA_GDMACONTROL, 0);
 645
 646                                 /* Install handler */
 647         if ((retcode = request_irq(dev->irq,
 648                                    gamma_dma_service,
 649                                    0,
 650                                    dev->devname,
 651                                    dev))) {
 652                 down(&dev->struct_sem);
 653                 dev->irq = 0;
 654                 up(&dev->struct_sem);
 655                 return retcode;
 656         }
 657
 658                                 /* After installing handler */
 659         GAMMA_WRITE(GAMMA_GINTENABLE,       0x2001);
 660         GAMMA_WRITE(GAMMA_COMMANDINTENABLE, 0x0008);
 661         GAMMA_WRITE(GAMMA_GDELAYTIMER,     0x39090);
 662
 663         return 0;
 664 }
 665
 666 int gamma_irq_uninstall(drm_device_t *dev)
 667 {
 668         int irq;
 669
 670         down(&dev->struct_sem);
 671         irq      = dev->irq;
 672         dev->irq = 0;
 673         up(&dev->struct_sem);
 674
 675         if (!irq) return -EINVAL;
 676
 677         DRM_DEBUG("%d\n", irq);
 678
 679         GAMMA_WRITE(GAMMA_GDELAYTIMER,      0);
 680         GAMMA_WRITE(GAMMA_COMMANDINTENABLE, 0);
 681         GAMMA_WRITE(GAMMA_GINTENABLE,       0);
 682         free_irq(irq, dev);
 683
 684         return 0;
 685 }
 686
 687
 688 int gamma_control(struct inode *inode, struct file *filp, unsigned int cmd,
 689                   unsigned long arg)
 690 {
 691         drm_file_t      *priv   = filp->private_data;
 692         drm_device_t    *dev    = priv->dev;
 693         drm_control_t   ctl;
 694         int             retcode;
 695
 696         copy_from_user_ret(&ctl, (drm_control_t *)arg, sizeof(ctl), -EFAULT);
 697
 698         switch (ctl.func) {
 699         case DRM_INST_HANDLER:
 700                 if ((retcode = gamma_irq_install(dev, ctl.irq)))
 701                         return retcode;
 702                 break;
 703         case DRM_UNINST_HANDLER:
 704                 if ((retcode = gamma_irq_uninstall(dev)))
 705                         return retcode;
 706                 break;
 707         default:
 708                 return -EINVAL;
 709         }
 710         return 0;
 711 }
 712
 713 int gamma_lock(struct inode *inode, struct file *filp, unsigned int cmd,
 714                unsigned long arg)
 715 {
 716         drm_file_t        *priv   = filp->private_data;
 717         drm_device_t      *dev    = priv->dev;
 718         DECLARE_WAITQUEUE(entry, current);
 719         int               ret   = 0;
 720         drm_lock_t        lock;
 721         drm_queue_t       *q;
 722 #if DRM_DMA_HISTOGRAM
 723         cycles_t          start;
 724
 725         dev->lck_start = start = get_cycles();
 726 #endif
 727
 728         copy_from_user_ret(&lock, (drm_lock_t *)arg, sizeof(lock), -EFAULT);
 729
 730         if (lock.context == DRM_KERNEL_CONTEXT) {
 731                 DRM_ERROR("Process %d using kernel context %d\n",
 732                           current->pid, lock.context);
 733                 return -EINVAL;
 734         }
 735
 736         DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
 737                   lock.context, current->pid, dev->lock.hw_lock->lock,
 738                   lock.flags);
 739
 740         if (lock.context < 0 || lock.context >= dev->queue_count)
 741                 return -EINVAL;
 742         q = dev->queuelist[lock.context];
 743
 744         ret = drm_flush_block_and_flush(dev, lock.context, lock.flags);
 745
 746         if (!ret) {
 747                 if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)
 748                     != lock.context) {
 749                         long j = jiffies - dev->lock.lock_time;
 750
 751                         if (j > 0 && j <= DRM_LOCK_SLICE) {
 752                                 /* Can't take lock if we just had it and
 753                                    there is contention. */
 754                                 current->state = TASK_INTERRUPTIBLE;
 755                                 schedule_timeout(j);
 756                         }
 757                 }
 758                 add_wait_queue(&dev->lock.lock_queue, &entry);
 759                 for (;;) {
 760                         if (!dev->lock.hw_lock) {
 761                                 /* Device has been unregistered */
 762                                 ret = -EINTR;
 763                                 break;
 764                         }
 765                         if (drm_lock_take(&dev->lock.hw_lock->lock,
 766                                           lock.context)) {
 767                                 dev->lock.pid       = current->pid;
 768                                 dev->lock.lock_time = jiffies;
 769                                 atomic_inc(&dev->total_locks);
 770                                 atomic_inc(&q->total_locks);
 771                                 break;  /* Got lock */
 772                         }
 773
 774                                 /* Contention */
 775                         atomic_inc(&dev->total_sleeps);
 776                         current->state = TASK_INTERRUPTIBLE;
 777                         schedule();
 778                         if (signal_pending(current)) {
 779                                 ret = -ERESTARTSYS;
 780                                 break;
 781                         }
 782                 }
 783                 current->state = TASK_RUNNING;
 784                 remove_wait_queue(&dev->lock.lock_queue, &entry);
 785         }
 786
 787         drm_flush_unblock(dev, lock.context, lock.flags); /* cleanup phase */
 788
 789         if (!ret) {
 790                 if (lock.flags & _DRM_LOCK_READY)
 791                         gamma_dma_ready(dev);
 792                 if (lock.flags & _DRM_LOCK_QUIESCENT)
 793                         gamma_dma_quiescent(dev);
 794         }
 795         DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
 796
 797 #if DRM_DMA_HISTOGRAM
 798         atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]);
 799 #endif
 800
 801         return ret;
 802 }