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* added 0.99 linux version
[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / isdn / hisax / isar.c
blob96442ff7d4ddc302d1d5f365dbc328691ea5a2e7
1 /* $Id: isar.c,v 1.5 1999/08/25 16:59:55 keil Exp $
2
3 * isar.c ISAR (Siemens PSB 7110) specific routines
4 *
5 * Author Karsten Keil (keil@isdn4linux.de)
6 *
7 *
8 * $Log: isar.c,v $
9 * Revision 1.5 1999/08/25 16:59:55 keil
10 * Make ISAR V32bis modem running
11 * Make LL->HL interface open for additional commands
12 *
13 * Revision 1.4 1999/08/05 20:43:18 keil
14 * ISAR analog modem support
15 *
16 * Revision 1.3 1999/07/01 08:11:45 keil
17 * Common HiSax version for 2.0, 2.1, 2.2 and 2.3 kernel
18 *
19 * Revision 1.2 1998/11/15 23:54:53 keil
20 * changes from 2.0
21 *
22 * Revision 1.1 1998/08/13 23:33:47 keil
23 * First version, only init
24 *
25 *
26 */
27
28 #define __NO_VERSION__
29 #include "hisax.h"
30 #include "isar.h"
31 #include "isdnl1.h"
32 #include <linux/interrupt.h>
33
34 #define DBG_LOADFIRM 0
35 #define DUMP_MBOXFRAME 2
36
37 #define MIN(a,b) ((a<b)?a:b)
38
39 void isar_setup(struct IsdnCardState *cs);
40
41 static inline int
42 waitforHIA(struct IsdnCardState *cs, int timeout)
43 {
44
45 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
46 udelay(1);
47 timeout--;
48 }
49 if (!timeout)
50 printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
51 return(timeout);
52 }
53
54
55 int
56 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
57 u_char *msg)
58 {
59 long flags;
60 int i;
61
62 if (!waitforHIA(cs, 4000))
63 return(0);
64 #if DUMP_MBOXFRAME
65 if (cs->debug & L1_DEB_HSCX)
66 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
67 #endif
68 save_flags(flags);
69 cli();
70 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
71 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
72 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
73 if (msg && len) {
74 cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
75 for (i=1; i<len; i++)
76 cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
77 #if DUMP_MBOXFRAME>1
78 if (cs->debug & L1_DEB_HSCX_FIFO) {
79 char tmp[256], *t;
80
81 i = len;
82 while (i>0) {
83 t = tmp;
84 t += sprintf(t, "sendmbox cnt %d", len);
85 QuickHex(t, &msg[len-i], (i>64) ? 64:i);
86 debugl1(cs, tmp);
87 i -= 64;
88 }
89 }
90 #endif
91 }
92 cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
93 restore_flags(flags);
94 waitforHIA(cs, 10000);
95 return(1);
96 }
97
98 /* Call only with IRQ disabled !!! */
99 inline void
100 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
101 {
102 int i;
103
104 cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
105 if (msg && ireg->clsb) {
106 msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
107 for (i=1; i < ireg->clsb; i++)
108 msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
109 #if DUMP_MBOXFRAME>1
110 if (cs->debug & L1_DEB_HSCX_FIFO) {
111 char tmp[256], *t;
112
113 i = ireg->clsb;
114 while (i>0) {
115 t = tmp;
116 t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
117 QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
118 debugl1(cs, tmp);
119 i -= 64;
120 }
121 }
122 #endif
123 }
124 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
125 }
126
127 /* Call only with IRQ disabled !!! */
128 inline void
129 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
130 {
131 ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
132 ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
133 ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
134 #if DUMP_MBOXFRAME
135 if (cs->debug & L1_DEB_HSCX)
136 debugl1(cs, "rcv_mbox(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
137 ireg->clsb);
138 #endif
139 }
140
141 int
142 waitrecmsg(struct IsdnCardState *cs, u_char *len,
143 u_char *msg, int maxdelay)
144 {
145 int timeout = 0;
146 long flags;
147 struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
148
149
150 while((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
151 (timeout++ < maxdelay))
152 udelay(1);
153 if (timeout >= maxdelay) {
154 printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
155 return(0);
156 }
157 save_flags(flags);
158 cli();
159 get_irq_infos(cs, ir);
160 rcv_mbox(cs, ir, msg);
161 *len = ir->clsb;
162 restore_flags(flags);
163 return(1);
164 }
165
166 int
167 ISARVersion(struct IsdnCardState *cs, char *s)
168 {
169 int ver;
170 u_char msg[] = ISAR_MSG_HWVER;
171 u_char tmp[64];
172 u_char len;
173 int debug;
174
175 cs->cardmsg(cs, CARD_RESET, NULL);
176 /* disable ISAR IRQ */
177 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
178 debug = cs->debug;
179 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
180 if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg))
181 return(-1);
182 if (!waitrecmsg(cs, &len, tmp, 100000))
183 return(-2);
184 cs->debug = debug;
185 if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
186 if (len == 1) {
187 ver = tmp[0] & 0xf;
188 printk(KERN_INFO "%s ISAR version %d\n", s, ver);
189 return(ver);
190 }
191 return(-3);
192 }
193 return(-4);
194 }
195
196 int
197 isar_load_firmware(struct IsdnCardState *cs, u_char *buf)
198 {
199 int ret, size, cnt, debug;
200 u_char len, nom, noc;
201 u_short sadr, left, *sp;
202 u_char *p = buf;
203 u_char *msg, *tmpmsg, *mp, tmp[64];
204 long flags;
205 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
206
207 struct {u_short sadr;
208 u_short len;
209 u_short d_key;
210 } blk_head;
211
212 #define BLK_HEAD_SIZE 6
213 if (1 != (ret = ISARVersion(cs, "Testing"))) {
214 printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
215 return(1);
216 }
217 debug = cs->debug;
218 #if DBG_LOADFIRM<2
219 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
220 #endif
221 printk(KERN_DEBUG"isar_load_firmware buf %#lx\n", (u_long)buf);
222 if ((ret = verify_area(VERIFY_READ, (void *) p, sizeof(int)))) {
223 printk(KERN_ERR"isar_load_firmware verify_area ret %d\n", ret);
224 return ret;
225 }
226 if ((ret = copy_from_user(&size, p, sizeof(int)))) {
227 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
228 return ret;
229 }
230 p += sizeof(int);
231 printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
232 if ((ret = verify_area(VERIFY_READ, (void *) p, size))) {
233 printk(KERN_ERR"isar_load_firmware verify_area ret %d\n", ret);
234 return ret;
235 }
236 cnt = 0;
237 /* disable ISAR IRQ */
238 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
239 if (!(msg = kmalloc(256, GFP_KERNEL))) {
240 printk(KERN_ERR"isar_load_firmware no buffer\n");
241 return (1);
242 }
243 if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
244 printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
245 kfree(msg);
246 return (1);
247 }
248 while (cnt < size) {
249 if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
250 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
251 goto reterror;
252 }
253 cnt += BLK_HEAD_SIZE;
254 p += BLK_HEAD_SIZE;
255 printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
256 blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
257 sadr = blk_head.sadr;
258 left = blk_head.len;
259 if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
260 printk(KERN_ERR"isar sendmsg dkey failed\n");
261 ret = 1;goto reterror;
262 }
263 if (!waitrecmsg(cs, &len, tmp, 100000)) {
264 printk(KERN_ERR"isar waitrecmsg dkey failed\n");
265 ret = 1;goto reterror;
266 }
267 if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
268 printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
269 ireg->iis, ireg->cmsb, len);
270 ret = 1;goto reterror;
271 }
272 while (left>0) {
273 noc = MIN(126, left);
274 nom = 2*noc;
275 mp = msg;
276 *mp++ = sadr / 256;
277 *mp++ = sadr % 256;
278 left -= noc;
279 *mp++ = noc;
280 if ((ret = copy_from_user(tmpmsg, p, nom))) {
281 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
282 goto reterror;
283 }
284 p += nom;
285 cnt += nom;
286 nom += 3;
287 sp = (u_short *)tmpmsg;
288 #if DBG_LOADFIRM
289 printk(KERN_DEBUG"isar: load %3d words at %04x\n",
290 noc, sadr);
291 #endif
292 sadr += noc;
293 while(noc) {
294 *mp++ = *sp / 256;
295 *mp++ = *sp % 256;
296 sp++;
297 noc--;
298 }
299 if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
300 printk(KERN_ERR"isar sendmsg prog failed\n");
301 ret = 1;goto reterror;
302 }
303 if (!waitrecmsg(cs, &len, tmp, 100000)) {
304 printk(KERN_ERR"isar waitrecmsg prog failed\n");
305 ret = 1;goto reterror;
306 }
307 if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
308 printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
309 ireg->iis, ireg->cmsb, len);
310 ret = 1;goto reterror;
311 }
312 }
313 printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
314 blk_head.len);
315 }
316 /* 10ms delay */
317 cnt = 10;
318 while (cnt--)
319 udelay(1000);
320 msg[0] = 0xff;
321 msg[1] = 0xfe;
322 ireg->bstat = 0;
323 if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
324 printk(KERN_ERR"isar sendmsg start dsp failed\n");
325 ret = 1;goto reterror;
326 }
327 if (!waitrecmsg(cs, &len, tmp, 100000)) {
328 printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
329 ret = 1;goto reterror;
330 }
331 if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
332 printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
333 ireg->iis, ireg->cmsb, len);
334 ret = 1;goto reterror;
335 } else
336 printk(KERN_DEBUG"isar start dsp success\n");
337 /* NORMAL mode entered */
338 /* Enable IRQs of ISAR */
339 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
340 save_flags(flags);
341 sti();
342 cnt = 1000; /* max 1s */
343 while ((!ireg->bstat) && cnt) {
344 udelay(1000);
345 cnt--;
346 }
347 if (!cnt) {
348 printk(KERN_ERR"isar no general status event received\n");
349 ret = 1;goto reterrflg;
350 } else {
351 printk(KERN_DEBUG"isar general status event %x\n",
352 ireg->bstat);
353 }
354 /* 10ms delay */
355 cnt = 10;
356 while (cnt--)
357 udelay(1000);
358 ireg->iis = 0;
359 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
360 printk(KERN_ERR"isar sendmsg self tst failed\n");
361 ret = 1;goto reterrflg;
362 }
363 cnt = 10000; /* max 100 ms */
364 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
365 udelay(10);
366 cnt--;
367 }
368 udelay(1000);
369 if (!cnt) {
370 printk(KERN_ERR"isar no self tst response\n");
371 ret = 1;goto reterrflg;
372 }
373 if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
374 && (ireg->par[0] == 0)) {
375 printk(KERN_DEBUG"isar selftest OK\n");
376 } else {
377 printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
378 ireg->cmsb, ireg->clsb, ireg->par[0]);
379 ret = 1;goto reterror;
380 }
381 ireg->iis = 0;
382 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
383 printk(KERN_ERR"isar RQST SVN failed\n");
384 ret = 1;goto reterror;
385 }
386 cnt = 30000; /* max 300 ms */
387 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
388 udelay(10);
389 cnt--;
390 }
391 udelay(1000);
392 if (!cnt) {
393 printk(KERN_ERR"isar no SVN response\n");
394 ret = 1;goto reterrflg;
395 } else {
396 if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
397 printk(KERN_DEBUG"isar software version %#x\n",
398 ireg->par[0]);
399 else {
400 printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
401 ireg->cmsb, ireg->clsb, cnt);
402 ret = 1;goto reterrflg;
403 }
404 }
405 cs->debug = debug;
406 isar_setup(cs);
407 ret = 0;
408 reterrflg:
409 restore_flags(flags);
410 reterror:
411 cs->debug = debug;
412 if (ret)
413 /* disable ISAR IRQ */
414 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
415 kfree(msg);
416 kfree(tmpmsg);
417 return(ret);
418 }
419
420 extern void BChannel_bh(struct BCState *);
421 #define B_LL_NOCARRIER 8
422 #define B_LL_CONNECT 9
423 #define B_LL_OK 10
424
425 static void
426 isar_bh(struct BCState *bcs)
427 {
428 BChannel_bh(bcs);
429 }
430
431 static void
432 isar_sched_event(struct BCState *bcs, int event)
433 {
434 bcs->event |= 1 << event;
435 queue_task(&bcs->tqueue, &tq_immediate);
436 mark_bh(IMMEDIATE_BH);
437 }
438
439 static inline void
440 isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
441 {
442 u_char *ptr;
443 struct sk_buff *skb;
444 struct isar_reg *ireg = bcs->hw.isar.reg;
445
446 if (!ireg->clsb) {
447 debugl1(cs, "isar zero len frame");
448 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
449 return;
450 }
451 switch (bcs->mode) {
452 case L1_MODE_NULL:
453 debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
454 ireg->iis, ireg->cmsb, ireg->clsb);
455 printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
456 ireg->iis, ireg->cmsb, ireg->clsb);
457 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
458 break;
459 case L1_MODE_TRANS:
460 case L1_MODE_V32:
461 if ((skb = dev_alloc_skb(ireg->clsb))) {
462 SET_SKB_FREE(skb);
463 rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
464 skb_queue_tail(&bcs->rqueue, skb);
465 isar_sched_event(bcs, B_RCVBUFREADY);
466 } else {
467 printk(KERN_WARNING "HiSax: skb out of memory\n");
468 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
469 }
470 break;
471 case L1_MODE_HDLC:
472 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
473 if (cs->debug & L1_DEB_WARN)
474 debugl1(cs, "isar_rcv_frame: incoming packet too large");
475 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
476 bcs->hw.isar.rcvidx = 0;
477 } else if (ireg->cmsb & HDLC_ERROR) {
478 if (cs->debug & L1_DEB_WARN)
479 debugl1(cs, "isar frame error %x len %d",
480 ireg->cmsb, ireg->clsb);
481 bcs->hw.isar.rcvidx = 0;
482 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
483 } else {
484 if (ireg->cmsb & HDLC_FSD)
485 bcs->hw.isar.rcvidx = 0;
486 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
487 bcs->hw.isar.rcvidx += ireg->clsb;
488 rcv_mbox(cs, ireg, ptr);
489 if (ireg->cmsb & HDLC_FED) {
490 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
491 printk(KERN_WARNING "ISAR: HDLC frame too short(%d)\n",
492 bcs->hw.isar.rcvidx);
493 } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx-2))) {
494 printk(KERN_WARNING "ISAR: receive out of memory\n");
495 } else {
496 SET_SKB_FREE(skb);
497 memcpy(skb_put(skb, bcs->hw.isar.rcvidx-2),
498 bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx-2);
499 skb_queue_tail(&bcs->rqueue, skb);
500 isar_sched_event(bcs, B_RCVBUFREADY);
501 }
502 }
503 }
504 break;
505 default:
506 printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
507 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
508 break;
509 }
510 }
511
512 void
513 isar_fill_fifo(struct BCState *bcs)
514 {
515 struct IsdnCardState *cs = bcs->cs;
516 int count;
517 u_char msb;
518 u_char *ptr;
519 long flags;
520
521 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
522 debugl1(cs, "isar_fill_fifo");
523 if (!bcs->tx_skb)
524 return;
525 if (bcs->tx_skb->len <= 0)
526 return;
527 if (!(bcs->hw.isar.reg->bstat &
528 (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
529 return;
530 if (bcs->tx_skb->len > bcs->hw.isar.mml) {
531 msb = 0;
532 count = bcs->hw.isar.mml;
533 } else {
534 count = bcs->tx_skb->len;
535 msb = HDLC_FED;
536 }
537 if (!bcs->hw.isar.txcnt)
538 msb |= HDLC_FST;
539 save_flags(flags);
540 cli();
541 ptr = bcs->tx_skb->data;
542 skb_pull(bcs->tx_skb, count);
543 bcs->tx_cnt -= count;
544 bcs->hw.isar.txcnt += count;
545 switch (bcs->mode) {
546 case L1_MODE_NULL:
547 printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
548 break;
549 case L1_MODE_TRANS:
550 case L1_MODE_V32:
551 if (!sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
552 0, count, ptr)) {
553 if (cs->debug)
554 debugl1(cs, "isar bin data send dp%d failed",
555 bcs->hw.isar.dpath);
556 }
557 break;
558 case L1_MODE_HDLC:
559 if (!sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
560 msb, count, ptr)) {
561 if (cs->debug)
562 debugl1(cs, "isar hdlc data send dp%d failed",
563 bcs->hw.isar.dpath);
564 }
565 break;
566 default:
567 printk(KERN_ERR"isar_fill_fifo mode (%x)error\n", bcs->mode);
568 break;
569 }
570 restore_flags(flags);
571 }
572
573 inline
574 struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
575 {
576 if ((!dpath) || (dpath == 3))
577 return(NULL);
578 if (cs->bcs[0].hw.isar.dpath == dpath)
579 return(&cs->bcs[0]);
580 if (cs->bcs[1].hw.isar.dpath == dpath)
581 return(&cs->bcs[1]);
582 return(NULL);
583 }
584
585 inline void
586 send_frames(struct BCState *bcs)
587 {
588 if (bcs->tx_skb) {
589 if (bcs->tx_skb->len) {
590 isar_fill_fifo(bcs);
591 return;
592 } else {
593 if (bcs->st->lli.l1writewakeup &&
594 (PACKET_NOACK != bcs->tx_skb->pkt_type))
595 bcs->st->lli.l1writewakeup(bcs->st, bcs->hw.isar.txcnt);
596 idev_kfree_skb(bcs->tx_skb, FREE_WRITE);
597 bcs->hw.isar.txcnt = 0;
598 bcs->tx_skb = NULL;
599 }
600 }
601 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
602 bcs->hw.isar.txcnt = 0;
603 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
604 isar_fill_fifo(bcs);
605 } else {
606 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
607 isar_sched_event(bcs, B_XMTBUFREADY);
608 }
609 }
610
611 inline void
612 check_send(struct IsdnCardState *cs, u_char rdm)
613 {
614 struct BCState *bcs;
615
616 if (rdm & BSTAT_RDM1) {
617 if ((bcs = sel_bcs_isar(cs, 1))) {
618 if (bcs->mode) {
619 send_frames(bcs);
620 }
621 }
622 }
623 if (rdm & BSTAT_RDM2) {
624 if ((bcs = sel_bcs_isar(cs, 2))) {
625 if (bcs->mode) {
626 send_frames(bcs);
627 }
628 }
629 }
630
631 }
632 const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200", "NODEF4",
633 "300", "600", "1200", "2400", "4800", "7200",
634 "9600nt", "9600t", "12000", "14400", "WRONG"};
635 const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
636 "Bell103", "V23", "Bell202", "V17", "V29", "V27ter"};
637
638 static void
639 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
640 struct IsdnCardState *cs = bcs->cs;
641 u_char ril = ireg->par[0];
642 u_char rim;
643
644 if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
645 return;
646 if (ril > 14) {
647 if (cs->debug & L1_DEB_WARN)
648 debugl1(cs, "wrong pstrsp ril=%d",ril);
649 ril = 15;
650 }
651 switch(ireg->par[1]) {
652 case 0:
653 rim = 0;
654 break;
655 case 0x20:
656 rim = 2;
657 break;
658 case 0x40:
659 rim = 3;
660 break;
661 case 0x41:
662 rim = 4;
663 break;
664 case 0x51:
665 rim = 5;
666 break;
667 case 0x61:
668 rim = 6;
669 break;
670 case 0x71:
671 rim = 7;
672 break;
673 case 0x82:
674 rim = 8;
675 break;
676 case 0x92:
677 rim = 9;
678 break;
679 case 0xa2:
680 rim = 10;
681 break;
682 default:
683 rim = 1;
684 break;
685 }
686 sprintf(bcs->hw.isar.conmsg,"%s %s", dmril[ril], dmrim[rim]);
687 bcs->conmsg = bcs->hw.isar.conmsg;
688 if (cs->debug & L1_DEB_HSCX)
689 debugl1(cs, "pump strsp %s", bcs->conmsg);
690 }
691
692 static void
693 isar_pump_status_ev(struct BCState *bcs, u_char devt) {
694 struct IsdnCardState *cs = bcs->cs;
695 u_char dps = SET_DPS(bcs->hw.isar.dpath);
696
697 switch(devt) {
698 case PSEV_10MS_TIMER:
699 if (cs->debug & L1_DEB_HSCX)
700 debugl1(cs, "pump stev TIMER");
701 break;
702 case PSEV_CON_ON:
703 if (cs->debug & L1_DEB_HSCX)
704 debugl1(cs, "pump stev CONNECT");
705 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
706 break;
707 case PSEV_CON_OFF:
708 if (cs->debug & L1_DEB_HSCX)
709 debugl1(cs, "pump stev NO CONNECT");
710 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
711 l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
712 break;
713 case PSEV_V24_OFF:
714 if (cs->debug & L1_DEB_HSCX)
715 debugl1(cs, "pump stev V24 OFF");
716 break;
717 case PSEV_CTS_ON:
718 if (cs->debug & L1_DEB_HSCX)
719 debugl1(cs, "pump stev CTS ON");
720 break;
721 case PSEV_CTS_OFF:
722 if (cs->debug & L1_DEB_HSCX)
723 debugl1(cs, "pump stev CTS OFF");
724 break;
725 case PSEV_DCD_ON:
726 if (cs->debug & L1_DEB_HSCX)
727 debugl1(cs, "pump stev CARRIER ON");
728 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
729 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
730 break;
731 case PSEV_DCD_OFF:
732 if (cs->debug & L1_DEB_HSCX)
733 debugl1(cs, "pump stev CARRIER OFF");
734 break;
735 case PSEV_DSR_ON:
736 if (cs->debug & L1_DEB_HSCX)
737 debugl1(cs, "pump stev DSR ON");
738 break;
739 case PSEV_DSR_OFF:
740 if (cs->debug & L1_DEB_HSCX)
741 debugl1(cs, "pump stev DSR_OFF");
742 break;
743 case PSEV_REM_RET:
744 if (cs->debug & L1_DEB_HSCX)
745 debugl1(cs, "pump stev REMOTE RETRAIN");
746 break;
747 case PSEV_REM_REN:
748 if (cs->debug & L1_DEB_HSCX)
749 debugl1(cs, "pump stev REMOTE RENEGOTIATE");
750 break;
751 case PSEV_GSTN_CLR:
752 if (cs->debug & L1_DEB_HSCX)
753 debugl1(cs, "pump stev GSTN CLEAR", devt);
754 break;
755 default:
756 if (cs->debug & L1_DEB_HSCX)
757 debugl1(cs, "unknown pump stev %x", devt);
758 break;
759 }
760 }
761
762 static char debbuf[128];
763
764 void
765 isar_int_main(struct IsdnCardState *cs)
766 {
767 long flags;
768 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
769 struct BCState *bcs;
770
771 save_flags(flags);
772 cli();
773 get_irq_infos(cs, ireg);
774 switch (ireg->iis & ISAR_IIS_MSCMSD) {
775 case ISAR_IIS_RDATA:
776 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
777 isar_rcv_frame(cs, bcs);
778 } else {
779 debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
780 ireg->iis, ireg->cmsb, ireg->clsb);
781 printk(KERN_WARNING"isar spurious IIS_RDATA %x/%x/%x\n",
782 ireg->iis, ireg->cmsb, ireg->clsb);
783 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
784 }
785 break;
786 case ISAR_IIS_GSTEV:
787 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
788 ireg->bstat |= ireg->cmsb;
789 check_send(cs, ireg->cmsb);
790 break;
791 case ISAR_IIS_BSTEV:
792 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
793 if (cs->debug & L1_DEB_WARN)
794 debugl1(cs, "Buffer STEV dpath%d msb(%x)",
795 ireg->iis>>6, ireg->cmsb);
796 case ISAR_IIS_PSTEV:
797 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
798 rcv_mbox(cs, ireg, (u_char *)ireg->par);
799 isar_pump_status_ev(bcs, ireg->cmsb);
800 } else {
801 debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
802 ireg->iis, ireg->cmsb, ireg->clsb);
803 printk(KERN_WARNING"isar spurious IIS_PSTEV %x/%x/%x\n",
804 ireg->iis, ireg->cmsb, ireg->clsb);
805 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
806 }
807 break;
808 case ISAR_IIS_PSTRSP:
809 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
810 rcv_mbox(cs, ireg, (u_char *)ireg->par);
811 isar_pump_status_rsp(bcs, ireg);
812 } else {
813 debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
814 ireg->iis, ireg->cmsb, ireg->clsb);
815 printk(KERN_WARNING"isar spurious IIS_PSTRSP %x/%x/%x\n",
816 ireg->iis, ireg->cmsb, ireg->clsb);
817 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
818 }
819 break;
820 case ISAR_IIS_DIAG:
821 case ISAR_IIS_BSTRSP:
822 case ISAR_IIS_IOM2RSP:
823 rcv_mbox(cs, ireg, (u_char *)ireg->par);
824 if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
825 == L1_DEB_HSCX) {
826 u_char *tp=debbuf;
827
828 tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
829 ireg->iis, ireg->cmsb);
830 QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
831 debugl1(cs, debbuf);
832 }
833 break;
834 case ISAR_IIS_INVMSG:
835 rcv_mbox(cs, ireg, debbuf);
836 if (cs->debug & L1_DEB_WARN)
837 debugl1(cs, "invalid msg his:%x",
838 ireg->cmsb);
839 break;
840 default:
841 rcv_mbox(cs, ireg, debbuf);
842 if (cs->debug & L1_DEB_WARN)
843 debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
844 ireg->iis, ireg->cmsb, ireg->clsb);
845 break;
846 }
847 restore_flags(flags);
848 }
849
850 static void
851 setup_pump(struct BCState *bcs) {
852 struct IsdnCardState *cs = bcs->cs;
853 u_char dps = SET_DPS(bcs->hw.isar.dpath);
854 u_char ctrl, param[6];
855
856 switch (bcs->mode) {
857 case L1_MODE_NULL:
858 case L1_MODE_TRANS:
859 case L1_MODE_HDLC:
860 if (!sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL)) {
861 if (cs->debug)
862 debugl1(cs, "isar pump bypass cfg dp%d failed",
863 bcs->hw.isar.dpath);
864 }
865 break;
866 case L1_MODE_V32:
867 ctrl = PMOD_DATAMODEM;
868 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
869 ctrl |= PCTRL_ORIG;
870 param[5] = PV32P6_CTN;
871 } else {
872 param[5] = PV32P6_ATN;
873 }
874 param[0] = 6; /* 6 db */
875 param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
876 PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
877 param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
878 param[3] = PV32P4_UT144;
879 param[4] = PV32P5_UT144;
880 if (!sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param)) {
881 if (cs->debug)
882 debugl1(cs, "isar pump datamodem cfg dp%d failed",
883 bcs->hw.isar.dpath);
884 }
885 break;
886 case L1_MODE_FAX:
887 ctrl = PMOD_FAX;
888 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
889 ctrl |= PCTRL_ORIG;
890 param[1] = PFAXP2_CTN;
891 } else {
892 param[1] = PFAXP2_ATN;
893 }
894 param[0] = 6; /* 6 db */
895 if (!sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param)) {
896 if (cs->debug)
897 debugl1(cs, "isar pump faxmodem cfg dp%d failed",
898 bcs->hw.isar.dpath);
899 }
900 break;
901 }
902 if (!sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL)) {
903 if (cs->debug)
904 debugl1(cs, "isar pump status req dp%d failed",
905 bcs->hw.isar.dpath);
906 }
907 }
908
909 static void
910 setup_sart(struct BCState *bcs) {
911 struct IsdnCardState *cs = bcs->cs;
912 u_char dps = SET_DPS(bcs->hw.isar.dpath);
913 u_char ctrl, param[2];
914
915 switch (bcs->mode) {
916 case L1_MODE_NULL:
917 if (!sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0, NULL)) {
918 if (cs->debug)
919 debugl1(cs, "isar sart disable dp%d failed",
920 bcs->hw.isar.dpath);
921 }
922 break;
923 case L1_MODE_TRANS:
924 if (!sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2, "\0\0")) {
925 if (cs->debug)
926 debugl1(cs, "isar sart binary dp%d failed",
927 bcs->hw.isar.dpath);
928 }
929 break;
930 case L1_MODE_HDLC:
931 case L1_MODE_FAX:
932 param[0] = 0;
933 if (!sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1, param)) {
934 if (cs->debug)
935 debugl1(cs, "isar sart hdlc dp%d failed",
936 bcs->hw.isar.dpath);
937 }
938 break;
939 case L1_MODE_V32:
940 ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
941 param[0] = S_P1_CHS_8;
942 param[1] = S_P2_BFT_DEF;
943 if (!sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2, param)) {
944 if (cs->debug)
945 debugl1(cs, "isar sart v14 dp%d failed",
946 bcs->hw.isar.dpath);
947 }
948 break;
949 }
950 if (!sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL)) {
951 if (cs->debug)
952 debugl1(cs, "isar buf stat req dp%d failed",
953 bcs->hw.isar.dpath);
954 }
955 }
956
957 static void
958 setup_iom2(struct BCState *bcs) {
959 struct IsdnCardState *cs = bcs->cs;
960 u_char dps = SET_DPS(bcs->hw.isar.dpath);
961 u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD,0,0,0,0};
962
963 if (bcs->channel)
964 msg[1] = msg[3] = 1;
965 switch (bcs->mode) {
966 case L1_MODE_NULL:
967 cmsb = 0;
968 /* dummy slot */
969 msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
970 break;
971 case L1_MODE_TRANS:
972 case L1_MODE_HDLC:
973 break;
974 case L1_MODE_V32:
975 case L1_MODE_FAX:
976 cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
977 break;
978 }
979 if (!sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg)) {
980 if (cs->debug)
981 debugl1(cs, "isar iom2 dp%d failed", bcs->hw.isar.dpath);
982 }
983 if (!sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL)) {
984 if (cs->debug)
985 debugl1(cs, "isar IOM2 cfg req dp%d failed",
986 bcs->hw.isar.dpath);
987 }
988 }
989
990 int
991 modeisar(struct BCState *bcs, int mode, int bc)
992 {
993 struct IsdnCardState *cs = bcs->cs;
994
995 /* Here we are selecting the best datapath for requested mode */
996 if(bcs->mode == L1_MODE_NULL) { /* New Setup */
997 bcs->channel = bc;
998 switch (mode) {
999 case L1_MODE_NULL: /* init */
1000 if (!bcs->hw.isar.dpath)
1001 /* no init for dpath 0 */
1002 return(0);
1003 break;
1004 case L1_MODE_TRANS:
1005 case L1_MODE_HDLC:
1006 /* best is datapath 2 */
1007 if (!test_and_set_bit(ISAR_DP2_USE,
1008 &bcs->hw.isar.reg->Flags))
1009 bcs->hw.isar.dpath = 2;
1010 else if (!test_and_set_bit(ISAR_DP1_USE,
1011 &bcs->hw.isar.reg->Flags))
1012 bcs->hw.isar.dpath = 1;
1013 else {
1014 printk(KERN_WARNING"isar modeisar both pathes in use\n");
1015 return(1);
1016 }
1017 break;
1018 case L1_MODE_V32:
1019 case L1_MODE_FAX:
1020 /* only datapath 1 */
1021 if (!test_and_set_bit(ISAR_DP1_USE,
1022 &bcs->hw.isar.reg->Flags))
1023 bcs->hw.isar.dpath = 1;
1024 else {
1025 printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
1026 debugl1(cs, "isar modeisar analog funktions only with DP1");
1027 return(1);
1028 }
1029 break;
1030 }
1031 }
1032 if (cs->debug & L1_DEB_HSCX)
1033 debugl1(cs, "isar dp%d mode %d->%d ichan %d",
1034 bcs->hw.isar.dpath, bcs->mode, mode, bc);
1035 bcs->mode = mode;
1036 setup_pump(bcs);
1037 setup_iom2(bcs);
1038 setup_sart(bcs);
1039 if (bcs->mode == L1_MODE_NULL) {
1040 /* Clear resources */
1041 if (bcs->hw.isar.dpath == 1)
1042 test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
1043 else if (bcs->hw.isar.dpath == 2)
1044 test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
1045 bcs->hw.isar.dpath = 0;
1046 }
1047 return(0);
1048 }
1049
1050 void
1051 isar_setup(struct IsdnCardState *cs)
1052 {
1053 u_char msg;
1054 int i;
1055
1056 /* Dpath 1, 2 */
1057 msg = 61;
1058 for (i=0; i<2; i++) {
1059 /* Buffer Config */
1060 if (!sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1061 ISAR_HIS_P12CFG, 4, 1, &msg)) {
1062 if (cs->debug)
1063 debugl1(cs, "isar P%dCFG failed", i+1);
1064 }
1065 cs->bcs[i].hw.isar.mml = msg;
1066 cs->bcs[i].mode = 0;
1067 cs->bcs[i].hw.isar.dpath = i + 1;
1068 modeisar(&cs->bcs[i], 0, 0);
1069 cs->bcs[i].tqueue.routine = (void *) (void *) isar_bh;
1070 }
1071 }
1072
1073 void
1074 isar_l2l1(struct PStack *st, int pr, void *arg)
1075 {
1076 struct sk_buff *skb = arg;
1077 long flags;
1078
1079 switch (pr) {
1080 case (PH_DATA | REQUEST):
1081 save_flags(flags);
1082 cli();
1083 if (st->l1.bcs->tx_skb) {
1084 skb_queue_tail(&st->l1.bcs->squeue, skb);
1085 restore_flags(flags);
1086 } else {
1087 st->l1.bcs->tx_skb = skb;
1088 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1089 if (st->l1.bcs->cs->debug & L1_DEB_HSCX)
1090 debugl1(st->l1.bcs->cs, "DRQ set BC_FLG_BUSY");
1091 st->l1.bcs->hw.isar.txcnt = 0;
1092 restore_flags(flags);
1093 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1094 }
1095 break;
1096 case (PH_PULL | INDICATION):
1097 if (st->l1.bcs->tx_skb) {
1098 printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
1099 break;
1100 }
1101 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1102 if (st->l1.bcs->cs->debug & L1_DEB_HSCX)
1103 debugl1(st->l1.bcs->cs, "PUI set BC_FLG_BUSY");
1104 st->l1.bcs->tx_skb = skb;
1105 st->l1.bcs->hw.isar.txcnt = 0;
1106 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1107 break;
1108 case (PH_PULL | REQUEST):
1109 if (!st->l1.bcs->tx_skb) {
1110 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1111 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1112 } else
1113 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1114 break;
1115 case (PH_ACTIVATE | REQUEST):
1116 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1117 st->l1.bcs->hw.isar.conmsg[0] = 0;
1118 if (test_bit(FLG_ORIG, &st->l2.flag))
1119 test_and_set_bit(BC_FLG_ORIG, &st->l1.bcs->Flag);
1120 else
1121 test_and_clear_bit(BC_FLG_ORIG, &st->l1.bcs->Flag);
1122 switch(st->l1.mode) {
1123 case L1_MODE_TRANS:
1124 case L1_MODE_HDLC:
1125 if (modeisar(st->l1.bcs, st->l1.mode, st->l1.bc))
1126 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1127 else
1128 l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
1129 break;
1130 case L1_MODE_V32:
1131 if (modeisar(st->l1.bcs, st->l1.mode, st->l1.bc))
1132 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1133 break;
1134 }
1135 break;
1136 case (PH_DEACTIVATE | REQUEST):
1137 l1_msg_b(st, pr, arg);
1138 break;
1139 case (PH_DEACTIVATE | CONFIRM):
1140 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1141 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1142 if (st->l1.bcs->cs->debug & L1_DEB_HSCX)
1143 debugl1(st->l1.bcs->cs, "PDAC clear BC_FLG_BUSY");
1144 modeisar(st->l1.bcs, 0, st->l1.bc);
1145 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1146 break;
1147 }
1148 }
1149
1150 void
1151 close_isarstate(struct BCState *bcs)
1152 {
1153 modeisar(bcs, 0, bcs->channel);
1154 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1155 if (bcs->hw.isar.rcvbuf) {
1156 kfree(bcs->hw.isar.rcvbuf);
1157 bcs->hw.isar.rcvbuf = NULL;
1158 }
1159 discard_queue(&bcs->rqueue);
1160 discard_queue(&bcs->squeue);
1161 if (bcs->tx_skb) {
1162 idev_kfree_skb(bcs->tx_skb, FREE_WRITE);
1163 bcs->tx_skb = NULL;
1164 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1165 if (bcs->cs->debug & L1_DEB_HSCX)
1166 debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
1167 }
1168 }
1169 }
1170
1171 int
1172 open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
1173 {
1174 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1175 if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
1176 printk(KERN_WARNING
1177 "HiSax: No memory for isar.rcvbuf\n");
1178 return (1);
1179 }
1180 skb_queue_head_init(&bcs->rqueue);
1181 skb_queue_head_init(&bcs->squeue);
1182 }
1183 bcs->tx_skb = NULL;
1184 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1185 if (cs->debug & L1_DEB_HSCX)
1186 debugl1(cs, "openisar clear BC_FLG_BUSY");
1187 bcs->event = 0;
1188 bcs->hw.isar.rcvidx = 0;
1189 bcs->tx_cnt = 0;
1190 return (0);
1191 }
1192
1193 int
1194 setstack_isar(struct PStack *st, struct BCState *bcs)
1195 {
1196 bcs->channel = st->l1.bc;
1197 if (open_isarstate(st->l1.hardware, bcs))
1198 return (-1);
1199 st->l1.bcs = bcs;
1200 st->l2.l2l1 = isar_l2l1;
1201 setstack_manager(st);
1202 bcs->st = st;
1203 setstack_l1_B(st);
1204 return (0);
1205 }
1206
1207 int
1208 isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
1209 u_long adr;
1210 int features;
1211
1212 if (cs->debug & L1_DEB_HSCX)
1213 debugl1(cs, "isar_auxcmd cmd/ch %x/%d", ic->command, ic->arg);
1214 switch (ic->command) {
1215 case (ISDN_CMD_IOCTL):
1216 switch (ic->arg) {
1217 case (9): /* load firmware */
1218 features = ISDN_FEATURE_L2_MODEM;
1219 memcpy(&adr, ic->parm.num, sizeof(ulong));
1220 if (isar_load_firmware(cs, (u_char *)adr))
1221 return(1);
1222 else
1223 ll_run(cs, features);
1224 break;
1225 default:
1226 printk(KERN_DEBUG "HiSax: invalid ioclt %d\n",
1227 (int) ic->arg);
1228 return(-EINVAL);
1229 }
1230 break;
1231 default:
1232 return(-EINVAL);
1233 }
1234 return(0);
1235 }
1236
1237 HISAX_INITFUNC(void
1238 initisar(struct IsdnCardState *cs))
1239 {
1240 cs->bcs[0].BC_SetStack = setstack_isar;
1241 cs->bcs[1].BC_SetStack = setstack_isar;
1242 cs->bcs[0].BC_Close = close_isarstate;
1243 cs->bcs[1].BC_Close = close_isarstate;
1244 }