i386/linux/linux-2.3.21/drivers/net/acenic.h

   1 #ifndef _ACENIC_H_
   2 #define _ACENIC_H_
   3
   4 /*
   5  * Addressing:
   6  *
   7  * The Tigon uses 64-bit host addresses, regardless of their actual
   8  * length, and it expects a big-endian format. For 32 bit systems the
   9  * upper 32 bits of the address are simply ignored (zero), however for
  10  * little endian 64 bit systems (Alpha) this looks strange with the
  11  * two parts of the address word being swapped.
  12  *
  13  * The addresses are split in two 32 bit words for all architectures
  14  * as some of them are in PCI shared memory and it is necessary to use
  15  * readl/writel to access them.
  16  *
  17  * The addressing code is derived from Pete Wyckoff's work, but
  18  * modified to deal properly with readl/writel usage.
  19  */
  20
  21 typedef struct {
  22         u32 addrhi;
  23         u32 addrlo;
  24 } aceaddr;
  25
  26
  27 static inline void set_aceaddr(aceaddr *aa, volatile void *addr)
  28 {
  29         unsigned long baddr = virt_to_bus((void *)addr);
  30 #if (BITS_PER_LONG == 64)
  31         aa->addrlo = baddr & 0xffffffff;
  32         aa->addrhi = baddr >> 32;
  33 #else
  34     /* Don't bother setting zero every time */
  35         aa->addrlo = baddr;
  36 #endif
  37         mb();
  38 }
  39
  40
  41 static inline void set_aceaddr_bus(aceaddr *aa, volatile void *addr)
  42 {
  43         unsigned long baddr = (unsigned long)addr;
  44 #if (BITS_PER_LONG == 64)
  45         aa->addrlo = baddr & 0xffffffff;
  46         aa->addrhi = baddr >> 32;
  47 #else
  48     /* Don't bother setting zero every time */
  49         aa->addrlo = baddr;
  50 #endif
  51         mb();
  52 }
  53
  54
  55 static inline void *get_aceaddr(aceaddr *aa)
  56 {
  57         unsigned long addr;
  58         mb();
  59 #if (BITS_PER_LONG == 64)
  60         addr = (u64)aa->addrhi << 32 | aa->addrlo;
  61 #else
  62         addr = aa->addrlo;
  63 #endif
  64         return bus_to_virt(addr);
  65 }
  66
  67
  68 static inline void *get_aceaddr_bus(aceaddr *aa)
  69 {
  70         unsigned long addr;
  71         mb();
  72 #if (BITS_PER_LONG == 64)
  73         addr = (u64)aa->addrhi << 32 | aa->addrlo;
  74 #else
  75         addr = aa->addrlo;
  76 #endif
  77         return (void *)addr;
  78 }
  79
  80
  81 struct ace_regs {
  82         u32     pad0[16];       /* PCI control registers */
  83
  84         u32     HostCtrl;       /* 0x40 */
  85         u32     LocalCtrl;
  86
  87         u32     pad1[2];
  88
  89         u32     MiscCfg;        /* 0x50 */
  90
  91         u32     pad2[2];
  92
  93         u32     PciState;
  94
  95         u32     pad3[2];        /* 0x60 */
  96
  97         u32     WinBase;
  98         u32     WinData;
  99
 100         u32     pad4[12];       /* 0x70 */
 101
 102         u32     DmaWriteState;  /* 0xa0 */
 103         u32     pad5[3];
 104         u32     DmaReadState;   /* 0xb0 */
 105
 106         u32     pad6[26];
 107
 108         u32     AssistState;
 109
 110         u32     pad7[8];        /* 0x120 */
 111
 112         u32     CpuCtrl;        /* 0x140 */
 113         u32     Pc;
 114
 115         u32     pad8[3];
 116
 117         u32     SramAddr;       /* 0x154 */
 118         u32     SramData;
 119
 120         u32     pad9[49];
 121
 122         u32     MacRxState;     /* 0x220 */
 123
 124         u32     pad10[7];
 125
 126         u32     CpuBCtrl;       /* 0x240 */
 127         u32     PcB;
 128
 129         u32     pad11[3];
 130
 131         u32     SramBAddr;      /* 0x254 */
 132         u32     SramBData;
 133
 134         u32     pad12[105];
 135
 136         u32     pad13[32];      /* 0x400 */
 137         u32     Stats[32];
 138
 139         u32     Mb0Hi;          /* 0x500 */
 140         u32     Mb0Lo;
 141         u32     Mb1Hi;
 142         u32     CmdPrd;
 143         u32     Mb2Hi;
 144         u32     TxPrd;
 145         u32     Mb3Hi;
 146         u32     RxStdPrd; /* RxStdPrd */
 147         u32     Mb4Hi;
 148         u32     RxJumboPrd; /* RxJumboPrd */
 149         u32     Mb5Hi;
 150         u32     RxMiniPrd;
 151         u32     Mb6Hi;
 152         u32     Mb6Lo;
 153         u32     Mb7Hi;
 154         u32     Mb7Lo;
 155         u32     Mb8Hi;
 156         u32     Mb8Lo;
 157         u32     Mb9Hi;
 158         u32     Mb9Lo;
 159         u32     MbAHi;
 160         u32     MbALo;
 161         u32     MbBHi;
 162         u32     MbBLo;
 163         u32     MbCHi;
 164         u32     MbCLo;
 165         u32     MbDHi;
 166         u32     MbDLo;
 167         u32     MbEHi;
 168         u32     MbELo;
 169         u32     MbFHi;
 170         u32     MbFLo;
 171
 172         u32     pad14[32];
 173
 174         u32     MacAddrHi;      /* 0x600 */
 175         u32     MacAddrLo;
 176         u32     InfoPtrHi;
 177         u32     InfoPtrLo;
 178         u32     MultiCastHi;    /* 0x610 */
 179         u32     MultiCastLo;
 180         u32     ModeStat;
 181         u32     DmaReadCfg;
 182         u32     DmaWriteCfg;    /* 0x620 */
 183         u32     TxBufRat;
 184         u32     EvtCsm;
 185         u32     CmdCsm;
 186         u32     TuneRxCoalTicks;/* 0x630 */
 187         u32     TuneTxCoalTicks;
 188         u32     TuneStatTicks;
 189         u32     TuneMaxTxDesc;
 190         u32     TuneMaxRxDesc;  /* 0x640 */
 191         u32     TuneTrace;
 192         u32     TuneLink;
 193         u32     TuneFastLink;
 194         u32     TracePtr;       /* 0x650 */
 195         u32     TraceStrt;
 196         u32     TraceLen;
 197         u32     IfIdx;
 198         u32     IfMtu;          /* 0x660 */
 199         u32     MaskInt;
 200         u32     GigLnkState;
 201         u32     FastLnkState;
 202         u32     pad16[4];       /* 0x670 */
 203         u32     RxRetCsm;       /* 0x680 */
 204
 205         u32     pad17[31];
 206
 207         u32     CmdRng[64];     /* 0x700 */
 208         u32     Window[0x200];
 209 };
 210
 211 #define ACE_WINDOW_SIZE 0x800
 212
 213 #define ACE_JUMBO_MTU 9000
 214 #define ACE_STD_MTU 1500
 215
 216 #define ACE_TRACE_SIZE 0x8000
 217
 218 /*
 219  * Host control register bits.
 220  */
 221
 222 #define IN_INT          0x01
 223 #define CLR_INT         0x02
 224 #define BYTE_SWAP       0x10
 225 #define WORD_SWAP       0x20
 226 #define MASK_INTS       0x40
 227
 228 /*
 229  * Local control register bits.
 230  */
 231
 232 #define EEPROM_DATA_IN          0x800000
 233 #define EEPROM_DATA_OUT         0x400000
 234 #define EEPROM_WRITE_ENABLE     0x200000
 235 #define EEPROM_CLK_OUT          0x100000
 236
 237 #define EEPROM_BASE             0xa0000000
 238
 239 #define EEPROM_WRITE_SELECT     0xa0
 240 #define EEPROM_READ_SELECT      0xa1
 241
 242 #define SRAM_BANK_512K          0x200
 243
 244
 245 /*
 246  * Misc Config bits
 247  */
 248
 249 #define SYNC_SRAM_TIMING        0x100000
 250
 251
 252 /*
 253  * CPU state bits.
 254  */
 255
 256 #define CPU_RESET               0x01
 257 #define CPU_TRACE               0x02
 258 #define CPU_PROM_FAILED         0x10
 259 #define CPU_HALT                0x00010000
 260 #define CPU_HALTED              0xffff0000
 261
 262
 263 /*
 264  * PCI State bits.
 265  */
 266
 267 #define DMA_READ_MAX_4          0x04
 268 #define DMA_READ_MAX_16         0x08
 269 #define DMA_READ_MAX_32         0x0c
 270 #define DMA_READ_MAX_64         0x10
 271 #define DMA_READ_MAX_128        0x14
 272 #define DMA_READ_MAX_256        0x18
 273 #define DMA_READ_MAX_1K         0x1c
 274 #define DMA_WRITE_MAX_4         0x20
 275 #define DMA_WRITE_MAX_16        0x40
 276 #define DMA_WRITE_MAX_32        0x60
 277 #define DMA_WRITE_MAX_64        0x80
 278 #define DMA_WRITE_MAX_128       0xa0
 279 #define DMA_WRITE_MAX_256       0xc0
 280 #define DMA_WRITE_MAX_1K        0xe0
 281 #define MEM_READ_MULTIPLE       0x00020000
 282 #define PCI_66MHZ               0x00080000
 283 #define DMA_WRITE_ALL_ALIGN     0x00800000
 284 #define READ_CMD_MEM            0x06000000
 285 #define WRITE_CMD_MEM           0x70000000
 286
 287
 288 /*
 289  * Mode status
 290  */
 291
 292 #define ACE_BYTE_SWAP_DATA      0x10
 293 #define ACE_WARN                0x08
 294 #define ACE_WORD_SWAP           0x04
 295 #define ACE_NO_JUMBO_FRAG       0x200
 296 #define ACE_FATAL               0x40000000
 297
 298
 299 /*
 300  * DMA config
 301  */
 302
 303 #define DMA_THRESH_8W           0x80
 304
 305
 306 /*
 307  * Tuning parameters
 308  */
 309
 310 #define TICKS_PER_SEC           1000000
 311
 312
 313 /*
 314  * Link bits
 315  */
 316
 317 #define LNK_PREF                0x00008000
 318 #define LNK_10MB                0x00010000
 319 #define LNK_100MB               0x00020000
 320 #define LNK_1000MB              0x00040000
 321 #define LNK_FULL_DUPLEX         0x00080000
 322 #define LNK_HALF_DUPLEX         0x00100000
 323 #define LNK_TX_FLOW_CTL_Y       0x00200000
 324 #define LNK_NEG_ADVANCED        0x00400000
 325 #define LNK_RX_FLOW_CTL_Y       0x00800000
 326 #define LNK_NIC                 0x01000000
 327 #define LNK_JAM                 0x02000000
 328 #define LNK_JUMBO               0x04000000
 329 #define LNK_ALTEON              0x08000000
 330 #define LNK_NEG_FCTL            0x10000000
 331 #define LNK_NEGOTIATE           0x20000000
 332 #define LNK_ENABLE              0x40000000
 333 #define LNK_UP                  0x80000000
 334
 335
 336 /*
 337  * Event definitions
 338  */
 339
 340 #define EVT_RING_ENTRIES        256
 341 #define EVT_RING_SIZE   (EVT_RING_ENTRIES * sizeof(struct event))
 342
 343 struct event {
 344 #ifdef __LITTLE_ENDIAN
 345         u32     idx:12;
 346         u32     code:12;
 347         u32     evt:8;
 348 #else
 349         u32     evt:8;
 350         u32     code:12;
 351         u32     idx:12;
 352 #endif
 353         u32     pad;
 354 };
 355
 356
 357 /*
 358  * Events
 359  */
 360
 361 #define E_FW_RUNNING            0x01
 362 #define E_STATS_UPDATED         0x04
 363
 364 #define E_STATS_UPDATE          0x04
 365
 366 #define E_LNK_STATE             0x06
 367 #define E_C_LINK_UP             0x01
 368 #define E_C_LINK_DOWN           0x02
 369 #define E_C_LINK_UP_FAST        0x03
 370
 371 #define E_ERROR                 0x07
 372 #define E_C_ERR_INVAL_CMD       0x01
 373 #define E_C_ERR_UNIMP_CMD       0x02
 374 #define E_C_ERR_BAD_CFG         0x03
 375
 376 #define E_MCAST_LIST            0x08
 377 #define E_C_MCAST_ADDR_ADD      0x01
 378 #define E_C_MCAST_ADDR_DEL      0x02
 379
 380 #define E_RESET_JUMBO_RNG       0x09
 381
 382
 383 /*
 384  * Commands
 385  */
 386
 387 #define CMD_RING_ENTRIES        64
 388
 389 struct cmd {
 390 #ifdef __LITTLE_ENDIAN
 391         u32     idx:12;
 392         u32     code:12;
 393         u32     evt:8;
 394 #else
 395         u32     evt:8;
 396         u32     code:12;
 397         u32     idx:12;
 398 #endif
 399 };
 400
 401
 402 #define C_HOST_STATE            0x01
 403 #define C_C_STACK_UP            0x01
 404 #define C_C_STACK_DOWN          0x02
 405
 406 #define C_FDR_FILTERING         0x02
 407 #define C_C_FDR_FILT_ENABLE     0x01
 408 #define C_C_FDR_FILT_DISABLE    0x02
 409
 410 #define C_SET_RX_PRD_IDX        0x03
 411 #define C_UPDATE_STATS          0x04
 412 #define C_RESET_JUMBO_RNG       0x05
 413 #define C_ADD_MULTICAST_ADDR    0x08
 414 #define C_DEL_MULTICAST_ADDR    0x09
 415
 416 #define C_SET_PROMISC_MODE      0x0a
 417 #define C_C_PROMISC_ENABLE      0x01
 418 #define C_C_PROMISC_DISABLE     0x02
 419
 420 #define C_LNK_NEGOTIATION       0x0b
 421 #define C_C_NEGOTIATE_BOTH      0x00
 422 #define C_C_NEGOTIATE_GIG       0x01
 423 #define C_C_NEGOTIATE_10_100    0x02
 424
 425 #define C_SET_MAC_ADDR          0x0c
 426 #define C_CLEAR_PROFILE         0x0d
 427
 428 #define C_SET_MULTICAST_MODE    0x0e
 429 #define C_C_MCAST_ENABLE        0x01
 430 #define C_C_MCAST_DISABLE       0x02
 431
 432 #define C_CLEAR_STATS           0x0f
 433 #define C_SET_RX_JUMBO_PRD_IDX  0x10
 434 #define C_REFRESH_STATS         0x11
 435
 436
 437 /*
 438  * Descriptor flags
 439  */
 440 #define BD_FLG_TCP_UDP_SUM      0x01
 441 #define BD_FLG_IP_SUM           0x02
 442 #define BD_FLG_END              0x04
 443 #define BD_FLG_JUMBO            0x10
 444 #define BD_FLG_MINI             0x1000
 445
 446
 447 /*
 448  * Ring Control block flags
 449  */
 450 #define RCB_FLG_TCP_UDP_SUM     0x01
 451 #define RCB_FLG_IP_SUM          0x02
 452 #define RCB_FLG_VLAN_ASSIST     0x10
 453 #define RCB_FLG_COAL_INT_ONLY   0x20
 454 #define RCB_FLG_IEEE_SNAP_SUM   0x80
 455 #define RCB_FLG_EXT_RX_BD       0x100
 456 #define RCB_FLG_RNG_DISABLE     0x200
 457
 458
 459 /*
 460  * TX ring
 461  */
 462 #define TX_RING_ENTRIES 128
 463 #define TX_RING_SIZE    (TX_RING_ENTRIES * sizeof(struct tx_desc))
 464 #define TX_RING_BASE    0x3800
 465
 466 struct tx_desc{
 467         aceaddr addr;
 468         u32     flagsize;
 469 #if 0
 470 /*
 471  * This is in PCI shared mem and must be accessed with readl/writel
 472  * real layout is:
 473  */
 474 #if __LITTLE_ENDIAN
 475         u16     flags;
 476         u16     size;
 477         u16     vlan;
 478         u16     reserved;
 479 #else
 480         u16     size;
 481         u16     flags;
 482         u16     reserved;
 483         u16     vlan;
 484 #endif
 485 #endif
 486         u32     vlanres;
 487 };
 488
 489
 490 #define RX_STD_RING_ENTRIES     512
 491 #define RX_STD_RING_SIZE        (RX_STD_RING_ENTRIES * sizeof(struct rx_desc))
 492
 493 #define RX_JUMBO_RING_ENTRIES   256
 494 #define RX_JUMBO_RING_SIZE      (RX_JUMBO_RING_ENTRIES *sizeof(struct rx_desc))
 495
 496 #define RX_MINI_RING_ENTRIES    1024
 497 #define RX_MINI_RING_SIZE       (RX_MINI_RING_ENTRIES *sizeof(struct rx_desc))
 498
 499 #define RX_RETURN_RING_ENTRIES  2048
 500 #define RX_RETURN_RING_SIZE     (RX_MAX_RETURN_RING_ENTRIES * \
 501                                  sizeof(struct rx_desc))
 502
 503 struct rx_desc{
 504         aceaddr addr;
 505 #ifdef __LITTLE_ENDIAN
 506         u16     size;
 507         u16     idx;
 508 #else
 509         u16     idx;
 510         u16     size;
 511 #endif
 512 #ifdef __LITTLE_ENDIAN
 513         u16     flags;
 514         u16     type;
 515 #else
 516         u16     type;
 517         u16     flags;
 518 #endif
 519 #ifdef __LITTLE_ENDIAN
 520         u16     tcp_udp_csum;
 521         u16     ip_csum;
 522 #else
 523         u16     ip_csum;
 524         u16     tcp_udp_csum;
 525 #endif
 526 #ifdef __LITTLE_ENDIAN
 527         u16     vlan;
 528         u16     err_flags;
 529 #else
 530         u16     err_flags;
 531         u16     vlan;
 532 #endif
 533         u32     reserved;
 534         u32     opague;
 535 };
 536
 537
 538 /*
 539  * This struct is shared with the NIC firmware.
 540  */
 541 struct ring_ctrl {
 542         aceaddr rngptr;
 543 #ifdef __LITTLE_ENDIAN
 544         u16     flags;
 545         u16     max_len;
 546 #else
 547         u16     max_len;
 548         u16     flags;
 549 #endif
 550         u32     pad;
 551 };
 552
 553
 554 struct ace_mac_stats {
 555         u32 excess_colls;
 556         u32 coll_1;
 557         u32 coll_2;
 558         u32 coll_3;
 559         u32 coll_4;
 560         u32 coll_5;
 561         u32 coll_6;
 562         u32 coll_7;
 563         u32 coll_8;
 564         u32 coll_9;
 565         u32 coll_10;
 566         u32 coll_11;
 567         u32 coll_12;
 568         u32 coll_13;
 569         u32 coll_14;
 570         u32 coll_15;
 571         u32 late_coll;
 572         u32 defers;
 573         u32 crc_err;
 574         u32 underrun;
 575         u32 crs_err;
 576         u32 pad[3];
 577         u32 drop_ula;
 578         u32 drop_mc;
 579         u32 drop_fc;
 580         u32 drop_space;
 581         u32 coll;
 582         u32 kept_bc;
 583         u32 kept_mc;
 584         u32 kept_uc;
 585 };
 586
 587
 588 struct ace_info {
 589         union {
 590                 u32 stats[256];
 591         } s;
 592         struct ring_ctrl        evt_ctrl;
 593         struct ring_ctrl        cmd_ctrl;
 594         struct ring_ctrl        tx_ctrl;
 595         struct ring_ctrl        rx_std_ctrl;
 596         struct ring_ctrl        rx_jumbo_ctrl;
 597         struct ring_ctrl        rx_mini_ctrl;
 598         struct ring_ctrl        rx_return_ctrl;
 599         aceaddr evt_prd_ptr;
 600         aceaddr rx_ret_prd_ptr;
 601         aceaddr tx_csm_ptr;
 602         aceaddr stats2_ptr;
 603 };
 604
 605
 606 /*
 607  * struct ace_skb holding the rings of skb's. This is an awful lot of
 608  * pointers, but I don't see any other smart mode to do this in an
 609  * efficient manner ;-(
 610  */
 611 struct ace_skb
 612 {
 613         struct sk_buff          *tx_skbuff[TX_RING_ENTRIES];
 614         struct sk_buff          *rx_std_skbuff[RX_STD_RING_ENTRIES];
 615         struct sk_buff          *rx_mini_skbuff[RX_MINI_RING_ENTRIES];
 616         struct sk_buff          *rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
 617 };
 618
 619
 620 /*
 621  * Struct private for the AceNIC.
 622  *
 623  * Elements are grouped so variables used by the tx handling goes
 624  * together, and will go into the same cache lines etc. in order to
 625  * avoid cache line contention between the rx and tx handling on SMP.
 626  *
 627  * Frequently accessed variables are put at the beginning of the
 628  * struct to help the compiler generate better/shorter code.
 629  */
 630 struct ace_private
 631 {
 632         struct ace_skb          *skb;
 633         struct ace_regs         *regs;          /* register base */
 634         int                     version, fw_running, fw_up, link;
 635         int                     promisc, mcast_all;
 636         /*
 637          * The send ring is located in the shared memory window
 638          */
 639         struct ace_info         *info;
 640         struct tx_desc          *tx_ring;
 641         u32                     tx_prd, tx_full, tx_ret_csm;
 642         struct timer_list       timer;
 643
 644         unsigned long           std_refill_busy
 645                                 __attribute__ ((aligned (L1_CACHE_BYTES)));
 646         unsigned long           mini_refill_busy, jumbo_refill_busy;
 647         atomic_t                cur_rx_bufs,
 648                                 cur_mini_bufs,
 649                                 cur_jumbo_bufs;
 650         u32                     rx_std_skbprd, rx_mini_skbprd, rx_jumbo_skbprd;
 651         u32                     cur_rx;
 652         struct tq_struct        immediate;
 653         int                     bh_pending, jumbo;
 654         struct rx_desc          rx_std_ring[RX_STD_RING_ENTRIES]
 655                                 __attribute__ ((aligned (L1_CACHE_BYTES)));
 656         struct rx_desc          rx_jumbo_ring[RX_JUMBO_RING_ENTRIES];
 657         struct rx_desc          rx_mini_ring[RX_MINI_RING_ENTRIES];
 658         struct rx_desc          rx_return_ring[RX_RETURN_RING_ENTRIES];
 659         struct event            evt_ring[EVT_RING_ENTRIES];
 660         volatile u32            evt_prd
 661                                 __attribute__ ((aligned (L1_CACHE_BYTES)));
 662         volatile u32            rx_ret_prd
 663                                 __attribute__ ((aligned (L1_CACHE_BYTES)));
 664         volatile u32            tx_csm
 665                                 __attribute__ ((aligned (L1_CACHE_BYTES)));
 666         unsigned char           *trace_buf;
 667         struct pci_dev          *pdev;
 668         struct net_device       *next;
 669         u16                     pci_command;
 670         u8                      pci_latency;
 671         char                    name[24];
 672         struct net_device_stats stats;
 673 };
 674
 675 /*
 676  * Prototypes
 677  */
 678 static int ace_init(struct net_device *dev, int board_idx);
 679 static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs);
 680 static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs);
 681 static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs);
 682 static int ace_flush_jumbo_rx_ring(struct net_device *dev);
 683 static void ace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 684 static int ace_load_firmware(struct net_device *dev);
 685 static int ace_open(struct net_device *dev);
 686 static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev);
 687 static int ace_close(struct net_device *dev);
 688 static void ace_timer(unsigned long data);
 689 static void ace_bh(struct net_device *dev);
 690 static void ace_dump_trace(struct ace_private *ap);
 691 static void ace_set_multicast_list(struct net_device *dev);
 692 static int ace_change_mtu(struct net_device *dev, int new_mtu);
 693 #ifdef SKB_RECYCLE
 694 extern int ace_recycle(struct sk_buff *skb);
 695 #endif
 696 static int ace_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 697 static int ace_set_mac_addr(struct net_device *dev, void *p);
 698 static struct net_device_stats *ace_get_stats(struct net_device *dev);
 699 static u8 read_eeprom_byte(struct ace_regs *regs, unsigned long offset);
 700
 701 #endif /* _ACENIC_H_ */