i386/linux/linux-2.3.21/drivers/pcmcia/ricoh.h

   1 /*
   2  * ricoh.h 1.8 1999/08/28 04:01:47
   3  *
   4  * The contents of this file are subject to the Mozilla Public License
   5  * Version 1.1 (the "License"); you may not use this file except in
   6  * compliance with the License. You may obtain a copy of the License
   7  * at http://www.mozilla.org/MPL/
   8  *
   9  * Software distributed under the License is distributed on an "AS IS"
  10  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11  * the License for the specific language governing rights and
  12  * limitations under the License.
  13  *
  14  * The initial developer of the original code is David A. Hinds
  15  * <dhinds@hyper.stanford.edu>.  Portions created by David A. Hinds
  16  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
  17  *
  18  * Alternatively, the contents of this file may be used under the
  19  * terms of the GNU Public License version 2 (the "GPL"), in which
  20  * case the provisions of the GPL are applicable instead of the
  21  * above.  If you wish to allow the use of your version of this file
  22  * only under the terms of the GPL and not to allow others to use
  23  * your version of this file under the MPL, indicate your decision by
  24  * deleting the provisions above and replace them with the notice and
  25  * other provisions required by the GPL.  If you do not delete the
  26  * provisions above, a recipient may use your version of this file
  27  * under either the MPL or the GPL.
  28  */
  29
  30 #ifndef _LINUX_RICOH_H
  31 #define _LINUX_RICOH_H
  32
  33 #define RF5C_MODE_CTL           0x1f    /* Mode control */
  34 #define RF5C_PWR_CTL            0x2f    /* Mixed voltage control */
  35 #define RF5C_CHIP_ID            0x3a    /* Chip identification */
  36 #define RF5C_MODE_CTL_3         0x3b    /* Mode control 3 */
  37
  38 /* I/O window address offset */
  39 #define RF5C_IO_OFF(w)          (0x36+((w)<<1))
  40
  41 /* Flags for RF5C_MODE_CTL */
  42 #define RF5C_MODE_ATA           0x01    /* ATA mode */
  43 #define RF5C_MODE_LED_ENA       0x02    /* IRQ 12 is LED */
  44 #define RF5C_MODE_CA21          0x04
  45 #define RF5C_MODE_CA22          0x08
  46 #define RF5C_MODE_CA23          0x10
  47 #define RF5C_MODE_CA24          0x20
  48 #define RF5C_MODE_CA25          0x40
  49 #define RF5C_MODE_3STATE_BIT7   0x80
  50
  51 /* Flags for RF5C_PWR_CTL */
  52 #define RF5C_PWR_VCC_3V         0x01
  53 #define RF5C_PWR_IREQ_HIGH      0x02
  54 #define RF5C_PWR_INPACK_ENA     0x04
  55 #define RF5C_PWR_5V_DET         0x08
  56 #define RF5C_PWR_TC_SEL         0x10    /* Terminal Count: irq 11 or 15 */
  57 #define RF5C_PWR_DREQ_LOW       0x20
  58 #define RF5C_PWR_DREQ_OFF       0x00    /* DREQ steering control */
  59 #define RF5C_PWR_DREQ_INPACK    0x40
  60 #define RF5C_PWR_DREQ_SPKR      0x80
  61 #define RF5C_PWR_DREQ_IOIS16    0xc0
  62
  63 /* Values for RF5C_CHIP_ID */
  64 #define RF5C_CHIP_RF5C296       0x32
  65 #define RF5C_CHIP_RF5C396       0xb2
  66
  67 /* Flags for RF5C_MODE_CTL_3 */
  68 #define RF5C_MCTL3_DISABLE      0x01    /* Disable PCMCIA interface */
  69 #define RF5C_MCTL3_DMA_ENA      0x02
  70
  71 /* Register definitions for Ricoh PCI-to-CardBus bridges */
  72
  73 #ifndef PCI_VENDOR_ID_RICOH
  74 #define PCI_VENDOR_ID_RICOH             0x1180
  75 #endif
  76 #ifndef PCI_DEVICE_ID_RICOH_RL5C465
  77 #define PCI_DEVICE_ID_RICOH_RL5C465     0x0465
  78 #endif
  79 #ifndef PCI_DEVICE_ID_RICOH_RL5C466
  80 #define PCI_DEVICE_ID_RICOH_RL5C466     0x0466
  81 #endif
  82 #ifndef PCI_DEVICE_ID_RICOH_RL5C475
  83 #define PCI_DEVICE_ID_RICOH_RL5C475     0x0475
  84 #endif
  85 #ifndef PCI_DEVICE_ID_RICOH_RL5C476
  86 #define PCI_DEVICE_ID_RICOH_RL5C476     0x0476
  87 #endif
  88 #ifndef PCI_DEVICE_ID_RICOH_RL5C478
  89 #define PCI_DEVICE_ID_RICOH_RL5C478     0x0478
  90 #endif
  91
  92 /* Extra bits in CB_BRIDGE_CONTROL */
  93 #define RL5C46X_BCR_3E0_ENA             0x0800
  94 #define RL5C46X_BCR_3E2_ENA             0x1000
  95
  96 /* Misc Control Register */
  97 #define RL5C4XX_MISC                    0x0082  /* 16 bit */
  98 #define  RL5C4XX_MISC_HW_SUSPEND_ENA    0x0002
  99 #define  RL5C4XX_MISC_VCCEN_POL         0x0100
 100 #define  RL5C4XX_MISC_VPPEN_POL         0x0200
 101 #define  RL5C46X_MISC_SUSPEND           0x0001
 102 #define  RL5C46X_MISC_PWR_SAVE_2        0x0004
 103 #define  RL5C46X_MISC_IFACE_BUSY        0x0008
 104 #define  RL5C46X_MISC_B_LOCK            0x0010
 105 #define  RL5C46X_MISC_A_LOCK            0x0020
 106 #define  RL5C46X_MISC_PCI_LOCK          0x0040
 107 #define  RL5C47X_MISC_IFACE_BUSY        0x0004
 108 #define  RL5C47X_MISC_PCI_INT_MASK      0x0018
 109 #define  RL5C47X_MISC_PCI_INT_DIS       0x0020
 110 #define  RL5C47X_MISC_SUBSYS_WR         0x0040
 111 #define  RL5C47X_MISC_SRIRQ_ENA         0x0080
 112 #define  RL5C47X_MISC_5V_DISABLE        0x0400
 113 #define  RL5C47X_MISC_LED_POL           0x0800
 114
 115 /* 16-bit Interface Control Register */
 116 #define RL5C4XX_16BIT_CTL               0x0084  /* 16 bit */
 117 #define  RL5C4XX_16CTL_IO_TIMING        0x0100
 118 #define  RL5C4XX_16CTL_MEM_TIMING       0x0200
 119 #define  RL5C46X_16CTL_LEVEL_1          0x0010
 120 #define  RL5C46X_16CTL_LEVEL_2          0x0020
 121
 122 /* 16-bit IO and memory timing registers */
 123 #define RL5C4XX_16BIT_IO_0              0x0088  /* 16 bit */
 124 #define RL5C4XX_16BIT_MEM_0             0x0088  /* 16 bit */
 125 #define  RL5C4XX_SETUP_MASK             0x0007
 126 #define  RL5C4XX_SETUP_SHIFT            0
 127 #define  RL5C4XX_CMD_MASK               0x01f0
 128 #define  RL5C4XX_CMD_SHIFT              4
 129 #define  RL5C4XX_HOLD_MASK              0x1c00
 130 #define  RL5C4XX_HOLD_SHIFT             10
 131
 132 #endif /* _LINUX_RICOH_H */