i386/linux/linux-2.3.21/drivers/pcmcia/ti113x.h

   1 /*
   2  * ti113x.h 1.15 1999/09/03 16:43:35
   3  *
   4  * The contents of this file are subject to the Mozilla Public License
   5  * Version 1.1 (the "License"); you may not use this file except in
   6  * compliance with the License. You may obtain a copy of the License
   7  * at http://www.mozilla.org/MPL/
   8  *
   9  * Software distributed under the License is distributed on an "AS IS"
  10  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11  * the License for the specific language governing rights and
  12  * limitations under the License.
  13  *
  14  * The initial developer of the original code is David A. Hinds
  15  * <dhinds@hyper.stanford.edu>.  Portions created by David A. Hinds
  16  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
  17  *
  18  * Alternatively, the contents of this file may be used under the
  19  * terms of the GNU Public License version 2 (the "GPL"), in which
  20  * case the provisions of the GPL are applicable instead of the
  21  * above.  If you wish to allow the use of your version of this file
  22  * only under the terms of the GPL and not to allow others to use
  23  * your version of this file under the MPL, indicate your decision by
  24  * deleting the provisions above and replace them with the notice and
  25  * other provisions required by the GPL.  If you do not delete the
  26  * provisions above, a recipient may use your version of this file
  27  * under either the MPL or the GPL.
  28  */
  29
  30 #ifndef _LINUX_TI113X_H
  31 #define _LINUX_TI113X_H
  32
  33 #ifndef PCI_VENDOR_ID_TI
  34 #define PCI_VENDOR_ID_TI                0x104c
  35 #endif
  36
  37 #ifndef PCI_DEVICE_ID_TI_1130
  38 #define PCI_DEVICE_ID_TI_1130           0xac12
  39 #endif
  40 #ifndef PCI_DEVICE_ID_TI_1131
  41 #define PCI_DEVICE_ID_TI_1131           0xac15
  42 #endif
  43 #ifndef PCI_DEVICE_ID_TI_1031
  44 #define PCI_DEVICE_ID_TI_1031           0xac13
  45 #endif
  46 #ifndef PCI_DEVICE_ID_TI_1250A
  47 #define PCI_DEVICE_ID_TI_1250A          0xac16
  48 #endif
  49 #ifndef PCI_DEVICE_ID_TI_1220
  50 #define PCI_DEVICE_ID_TI_1220           0xac17
  51 #endif
  52 #ifndef PCI_DEVICE_ID_TI_1221
  53 #define PCI_DEVICE_ID_TI_1221           0xac19
  54 #endif
  55 #ifndef PCI_DEVICE_ID_TI_1210
  56 #define PCI_DEVICE_ID_TI_1210           0xac1a
  57 #endif
  58 #ifndef PCI_DEVICE_ID_TI_1450
  59 #define PCI_DEVICE_ID_TI_1450           0xac1b
  60 #endif
  61 #ifndef PCI_DEVICE_ID_TI_1225
  62 #define PCI_DEVICE_ID_TI_1225           0xac1c
  63 #endif
  64 #ifndef PCI_DEVICE_ID_TI_1251A
  65 #define PCI_DEVICE_ID_TI_1251A          0xac1d
  66 #endif
  67 #ifndef PCI_DEVICE_ID_TI_1211
  68 #define PCI_DEVICE_ID_TI_1211           0xac1e
  69 #endif
  70 #ifndef PCI_DEVICE_ID_TI_1251B
  71 #define PCI_DEVICE_ID_TI_1251B          0xac1f
  72 #endif
  73 #ifndef PCI_DEVICE_ID_TI_1420
  74 #define PCI_DEVICE_ID_TI_1420           0xac51
  75 #endif
  76
  77 /* Register definitions for TI 113X PCI-to-CardBus bridges */
  78
  79 /* System Control Register */
  80 #define TI113X_SYSTEM_CONTROL           0x0080  /* 32 bit */
  81 #define  TI113X_SCR_SMIROUTE            0x04000000
  82 #define  TI113X_SCR_SMISTATUS           0x02000000
  83 #define  TI113X_SCR_SMIENB              0x01000000
  84 #define  TI113X_SCR_VCCPROT             0x00200000
  85 #define  TI113X_SCR_REDUCEZV            0x00100000
  86 #define  TI113X_SCR_CDREQEN             0x00080000
  87 #define  TI113X_SCR_CDMACHAN            0x00070000
  88 #define  TI113X_SCR_SOCACTIVE           0x00002000
  89 #define  TI113X_SCR_PWRSTREAM           0x00000800
  90 #define  TI113X_SCR_DELAYUP             0x00000400
  91 #define  TI113X_SCR_DELAYDOWN           0x00000200
  92 #define  TI113X_SCR_INTERROGATE         0x00000100
  93 #define  TI113X_SCR_CLKRUN_SEL          0x00000080
  94 #define  TI113X_SCR_PWRSAVINGS          0x00000040
  95 #define  TI113X_SCR_SUBSYSRW            0x00000020
  96 #define  TI113X_SCR_CB_DPAR             0x00000010
  97 #define  TI113X_SCR_CDMA_EN             0x00000008
  98 #define  TI113X_SCR_ASYNC_IRQ           0x00000004
  99 #define  TI113X_SCR_KEEPCLK             0x00000002
 100 #define  TI113X_SCR_CLKRUN_ENA          0x00000001
 101
 102 #define  TI122X_SCR_SER_STEP            0xc0000000
 103 #define  TI122X_SCR_INTRTIE             0x20000000
 104 #define  TI122X_SCR_CBRSVD              0x00400000
 105 #define  TI122X_SCR_MRBURSTDN           0x00008000
 106 #define  TI122X_SCR_MRBURSTUP           0x00004000
 107 #define  TI122X_SCR_RIMUX               0x00000001
 108
 109 /* Multimedia Control Register */
 110 #define TI1250_MULTIMEDIA_CTL           0x0084  /* 8 bit */
 111 #define  TI1250_MMC_ZVOUTEN             0x80
 112 #define  TI1250_MMC_PORTSEL             0x40
 113 #define  TI1250_MMC_ZVEN1               0x02
 114 #define  TI1250_MMC_ZVEN0               0x01
 115
 116 #define TI1250_GENERAL_STATUS           0x0085  /* 8 bit */
 117 #define TI1250_GPIO0_CONTROL            0x0088  /* 8 bit */
 118 #define TI1250_GPIO1_CONTROL            0x0089  /* 8 bit */
 119 #define TI1250_GPIO2_CONTROL            0x008a  /* 8 bit */
 120 #define TI1250_GPIO3_CONTROL            0x008b  /* 8 bit */
 121 #define TI122X_IRQMUX                   0x008c  /* 32 bit */
 122
 123 /* Retry Status Register */
 124 #define TI113X_RETRY_STATUS             0x0090  /* 8 bit */
 125 #define  TI113X_RSR_PCIRETRY            0x80
 126 #define  TI113X_RSR_CBRETRY             0x40
 127 #define  TI113X_RSR_TEXP_CBB            0x20
 128 #define  TI113X_RSR_MEXP_CBB            0x10
 129 #define  TI113X_RSR_TEXP_CBA            0x08
 130 #define  TI113X_RSR_MEXP_CBA            0x04
 131 #define  TI113X_RSR_TEXP_PCI            0x02
 132 #define  TI113X_RSR_MEXP_PCI            0x01
 133
 134 /* Card Control Register */
 135 #define TI113X_CARD_CONTROL             0x0091  /* 8 bit */
 136 #define  TI113X_CCR_RIENB               0x80
 137 #define  TI113X_CCR_ZVENABLE            0x40
 138 #define  TI113X_CCR_PCI_IRQ_ENA         0x20
 139 #define  TI113X_CCR_PCI_IREQ            0x10
 140 #define  TI113X_CCR_PCI_CSC             0x08
 141 #define  TI113X_CCR_SPKROUTEN           0x02
 142 #define  TI113X_CCR_IFG                 0x01
 143
 144 #define  TI1220_CCR_PORT_SEL            0x20
 145 #define  TI122X_CCR_AUD2MUX             0x04
 146
 147 /* Device Control Register */
 148 #define TI113X_DEVICE_CONTROL           0x0092  /* 8 bit */
 149 #define  TI113X_DCR_5V_FORCE            0x40
 150 #define  TI113X_DCR_3V_FORCE            0x20
 151 #define  TI113X_DCR_IMODE_MASK          0x06
 152 #define  TI113X_DCR_IMODE_ISA           0x02
 153 #define  TI113X_DCR_IMODE_SERIAL        0x04
 154
 155 #define  TI12XX_DCR_IMODE_PCI_ONLY      0x00
 156 #define  TI12XX_DCR_IMODE_ALL_SERIAL    0x06
 157
 158 /* Buffer Control Register */
 159 #define TI113X_BUFFER_CONTROL           0x0093  /* 8 bit */
 160 #define  TI113X_BCR_CB_READ_DEPTH       0x08
 161 #define  TI113X_BCR_CB_WRITE_DEPTH      0x04
 162 #define  TI113X_BCR_PCI_READ_DEPTH      0x02
 163 #define  TI113X_BCR_PCI_WRITE_DEPTH     0x01
 164
 165 /* Diagnostic Register */
 166 #define TI1250_DIAGNOSTIC               0x0093  /* 8 bit */
 167 #define  TI1250_DIAG_TRUE_VALUE         0x80
 168 #define  TI1250_DIAG_PCI_IREQ           0x40
 169 #define  TI1250_DIAG_PCI_CSC            0x20
 170 #define  TI1250_DIAG_ASYNC_CSC          0x01
 171
 172 /* DMA Registers */
 173 #define TI113X_DMA_0                    0x0094  /* 32 bit */
 174 #define TI113X_DMA_1                    0x0098  /* 32 bit */
 175
 176 /* ExCA IO offset registers */
 177 #define TI113X_IO_OFFSET(map)           (0x36+((map)<<1))
 178
 179 #endif /* _LINUX_TI113X_H */
 180