i386/linux/linux-2.3.21/include/asm-m68k/atarihw.h

   1 /*
   2 ** linux/atarihw.h -- This header defines some macros and pointers for
   3 **                    the various Atari custom hardware registers.
   4 **
   5 ** Copyright 1994 by Bj”rn Brauel
   6 **
   7 ** 5/1/94 Roman Hodek:
   8 **   Added definitions for TT specific chips.
   9 **
  10 ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
  11 **   Finally added definitions for the matrix/codec and the DSP56001 host
  12 **   interface.
  13 **
  14 ** This file is subject to the terms and conditions of the GNU General Public
  15 ** License.  See the file COPYING in the main directory of this archive
  16 ** for more details.
  17 **
  18 */
  19
  20 #ifndef _LINUX_ATARIHW_H_
  21 #define _LINUX_ATARIHW_H_
  22
  23 #include <linux/types.h>
  24 #include <asm/bootinfo.h>
  25
  26 extern u_long atari_mch_cookie;
  27 extern u_long atari_mch_type;
  28 extern u_long atari_switches;
  29 extern int atari_rtc_year_offset;
  30 extern int atari_dont_touch_floppy_select;
  31
  32 /* convenience macros for testing machine type */
  33 #define MACH_IS_ST      ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
  34 #define MACH_IS_STE     ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
  35                          (atari_mch_cookie & 0xffff) == 0)
  36 #define MACH_IS_MSTE    ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
  37                          (atari_mch_cookie & 0xffff) == 0x10)
  38 #define MACH_IS_TT      ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
  39 #define MACH_IS_FALCON  ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
  40 #define MACH_IS_MEDUSA  (atari_mch_type == ATARI_MACH_MEDUSA)
  41 #define MACH_IS_HADES   (atari_mch_type == ATARI_MACH_HADES)
  42 #define MACH_IS_AB40    (atari_mch_type == ATARI_MACH_AB40)
  43
  44 /* values for atari_switches */
  45 #define ATARI_SWITCH_IKBD       0x01
  46 #define ATARI_SWITCH_MIDI       0x02
  47 #define ATARI_SWITCH_SND6       0x04
  48 #define ATARI_SWITCH_SND7       0x08
  49 #define ATARI_SWITCH_OVSC_SHIFT 16
  50 #define ATARI_SWITCH_OVSC_IKBD  (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
  51 #define ATARI_SWITCH_OVSC_MIDI  (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
  52 #define ATARI_SWITCH_OVSC_SND6  (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
  53 #define ATARI_SWITCH_OVSC_SND7  (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
  54 #define ATARI_SWITCH_OVSC_MASK  0xffff0000
  55
  56 /*
  57  * Define several Hardware-Chips for indication so that for the ATARI we do
  58  * no longer decide whether it is a Falcon or other machine . It's just
  59  * important what hardware the machine uses
  60  */
  61
  62 /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
  63
  64 #define ATARIHW_DECLARE(name)   unsigned name : 1
  65 #define ATARIHW_SET(name)       (atari_hw_present.name = 1)
  66 #define ATARIHW_PRESENT(name)   (atari_hw_present.name)
  67
  68 struct atari_hw_present {
  69     /* video hardware */
  70     ATARIHW_DECLARE(STND_SHIFTER);      /* ST-Shifter - no base low ! */
  71     ATARIHW_DECLARE(EXTD_SHIFTER);      /* STe-Shifter - 24 bit address */
  72     ATARIHW_DECLARE(TT_SHIFTER);        /* TT-Shifter */
  73     ATARIHW_DECLARE(VIDEL_SHIFTER);     /* Falcon-Shifter */
  74     /* sound hardware */
  75     ATARIHW_DECLARE(YM_2149);           /* Yamaha YM 2149 */
  76     ATARIHW_DECLARE(PCM_8BIT);          /* PCM-Sound in STe-ATARI */
  77     ATARIHW_DECLARE(CODEC);             /* CODEC Sound (Falcon) */
  78     /* disk storage interfaces */
  79     ATARIHW_DECLARE(TT_SCSI);           /* Directly mapped NCR5380 */
  80     ATARIHW_DECLARE(ST_SCSI);           /* NCR5380 via ST-DMA (Falcon) */
  81     ATARIHW_DECLARE(ACSI);              /* Standard ACSI like in STs */
  82     ATARIHW_DECLARE(IDE);               /* IDE Interface */
  83     ATARIHW_DECLARE(FDCSPEED);          /* 8/16 MHz switch for FDC */
  84     /* other I/O hardware */
  85     ATARIHW_DECLARE(ST_MFP);            /* The ST-MFP (there should be no Atari
  86                                            without it... but who knows?) */
  87     ATARIHW_DECLARE(TT_MFP);            /* 2nd MFP */
  88     ATARIHW_DECLARE(SCC);               /* Serial Communications Contr. */
  89     ATARIHW_DECLARE(ST_ESCC);           /* SCC Z83230 in an ST */
  90     ATARIHW_DECLARE(ANALOG_JOY);        /* Paddle Interface for STe
  91                                            and Falcon */
  92     ATARIHW_DECLARE(MICROWIRE);         /* Microwire Interface */
  93     /* DMA */
  94     ATARIHW_DECLARE(STND_DMA);          /* 24 Bit limited ST-DMA */
  95     ATARIHW_DECLARE(EXTD_DMA);          /* 32 Bit ST-DMA */
  96     ATARIHW_DECLARE(SCSI_DMA);          /* DMA for the NCR5380 */
  97     ATARIHW_DECLARE(SCC_DMA);           /* DMA for the SCC */
  98     /* real time clocks */
  99     ATARIHW_DECLARE(TT_CLK);            /* TT compatible clock chip */
 100     ATARIHW_DECLARE(MSTE_CLK);          /* Mega ST(E) clock chip */
 101     /* supporting hardware */
 102     ATARIHW_DECLARE(SCU);               /* System Control Unit */
 103     ATARIHW_DECLARE(BLITTER);           /* Blitter */
 104     ATARIHW_DECLARE(VME);               /* VME Bus */
 105     ATARIHW_DECLARE(DSP56K);            /* DSP56k processor in Falcon */
 106 };
 107
 108 extern struct atari_hw_present atari_hw_present;
 109
 110
 111 /* Reading the MFP port register gives a machine independent delay, since the
 112  * MFP always has a 8 MHz clock. This avoids problems with the varying length
 113  * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
 114  */
 115 #define MFPDELAY() \
 116         __asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" );
 117
 118 /* Do cache push/invalidate for DMA read/write. This function obeys the
 119  * snooping on some machines (Medusa) and processors: The Medusa itself can
 120  * snoop, but only the '040 can source data from its cache to DMA writes i.e.,
 121  * reads from memory). Both '040 and '060 invalidate cache entries on snooped
 122  * DMA reads (i.e., writes to memory).
 123  */
 124
 125 #include <linux/mm.h>
 126 #include <asm/pgtable.h>
 127
 128 static inline void dma_cache_maintenance( unsigned long paddr,
 129                                           unsigned long len,
 130                                           int writeflag )
 131
 132 {
 133         if (writeflag) {
 134                 if (!MACH_IS_MEDUSA || CPU_IS_060)
 135                         cache_push( paddr, len );
 136         }
 137         else {
 138                 if (!MACH_IS_MEDUSA)
 139                         cache_clear( paddr, len );
 140         }
 141 }
 142
 143
 144 /*
 145 ** Shifter
 146  */
 147 #define ST_LOW  0
 148 #define ST_MID  1
 149 #define ST_HIGH 2
 150 #define TT_LOW  7
 151 #define TT_MID  4
 152 #define TT_HIGH 6
 153
 154 #define SHF_BAS (0xffff8200)
 155 struct SHIFTER
 156  {
 157         u_char pad1;
 158         u_char bas_hi;
 159         u_char pad2;
 160         u_char bas_md;
 161         u_char pad3;
 162         u_char volatile vcounthi;
 163         u_char pad4;
 164         u_char volatile vcountmid;
 165         u_char pad5;
 166         u_char volatile vcountlow;
 167         u_char volatile syncmode;
 168         u_char pad6;
 169         u_char pad7;
 170         u_char bas_lo;
 171  };
 172 # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
 173
 174 #define SHF_FBAS (0xffff820e)
 175 struct SHIFTER_F030
 176  {
 177   u_short off_next;
 178   u_short scn_width;
 179  };
 180 # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
 181
 182
 183 #define SHF_TBAS (0xffff8200)
 184 struct SHIFTER_TT {
 185         u_char  char_dummy0;
 186         u_char  bas_hi;                 /* video mem base addr, high and mid byte */
 187         u_char  char_dummy1;
 188         u_char  bas_md;
 189         u_char  char_dummy2;
 190         u_char  vcount_hi;              /* pointer to currently displayed byte */
 191         u_char  char_dummy3;
 192         u_char  vcount_md;
 193         u_char  char_dummy4;
 194         u_char  vcount_lo;
 195         u_short st_sync;                /* ST compatible sync mode register, unused */
 196         u_char  char_dummy5;
 197         u_char  bas_lo;                 /* video mem addr, low byte */
 198         u_char  char_dummy6[2+3*16];
 199         /* $ffff8240: */
 200         u_short color_reg[16];  /* 16 color registers */
 201         u_char  st_shiftmode;   /* ST compatible shift mode register, unused */
 202         u_char  char_dummy7;
 203         u_short tt_shiftmode;   /* TT shift mode register */
 204
 205
 206 };
 207 #define shifter_tt      ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
 208
 209 /* values for shifter_tt->tt_shiftmode */
 210 #define TT_SHIFTER_STLOW                0x0000
 211 #define TT_SHIFTER_STMID                0x0100
 212 #define TT_SHIFTER_STHIGH               0x0200
 213 #define TT_SHIFTER_TTLOW                0x0700
 214 #define TT_SHIFTER_TTMID                0x0400
 215 #define TT_SHIFTER_TTHIGH               0x0600
 216 #define TT_SHIFTER_MODEMASK     0x0700
 217 #define TT_SHIFTER_NUMMODE      0x0008
 218 #define TT_SHIFTER_PALETTE_MASK 0x000f
 219 #define TT_SHIFTER_GRAYMODE             0x1000
 220
 221 /* 256 TT palette registers */
 222 #define TT_PALETTE_BASE (0xffff8400)
 223 #define tt_palette      ((volatile u_short *)TT_PALETTE_BASE)
 224
 225 #define TT_PALETTE_RED_MASK             0x0f00
 226 #define TT_PALETTE_GREEN_MASK   0x00f0
 227 #define TT_PALETTE_BLUE_MASK    0x000f
 228
 229 /*
 230 ** Falcon030 VIDEL Video Controller
 231 ** for description see File 'linux\tools\atari\hardware.txt
 232  */
 233 #define f030_col ((u_long *)            0xffff9800)
 234 #define f030_xreg ((u_short*)           0xffff8282)
 235 #define f030_yreg ((u_short*)           0xffff82a2)
 236 #define f030_creg ((u_short*)           0xffff82c0)
 237 #define f030_sreg ((u_short*)           0xffff8260)
 238 #define f030_mreg ((u_short*)           0xffff820a)
 239 #define f030_linewidth ((u_short*)      0xffff820e)
 240 #define f030_hscroll ((u_char*)         0xffff8265)
 241
 242 #define VIDEL_BAS (0xffff8260)
 243 struct VIDEL {
 244         u_short st_shift;
 245         u_short pad1;
 246         u_char  xoffset_s;
 247         u_char  xoffset;
 248         u_short f_shift;
 249         u_char  pad2[0x1a];
 250         u_short hht;
 251         u_short hbb;
 252         u_short hbe;
 253         u_short hdb;
 254         u_short hde;
 255         u_short hss;
 256         u_char  pad3[0x14];
 257         u_short vft;
 258         u_short vbb;
 259         u_short vbe;
 260         u_short vdb;
 261         u_short vde;
 262         u_short vss;
 263         u_char  pad4[0x12];
 264         u_short control;
 265         u_short mode;
 266 };
 267 #define videl   ((*(volatile struct VIDEL *)VIDEL_BAS))
 268
 269 /*
 270 ** DMA/WD1772 Disk Controller
 271  */
 272
 273 #define FWD_BAS (0xffff8604)
 274 struct DMA_WD
 275  {
 276   u_short fdc_acces_seccount;
 277   u_short dma_mode_status;
 278   u_char dma_vhi;       /* Some extended ST-DMAs can handle 32 bit addresses */
 279   u_char dma_hi;
 280   u_char char_dummy2;
 281   u_char dma_md;
 282   u_char char_dummy3;
 283   u_char dma_lo;
 284   u_short fdc_speed;
 285  };
 286 # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
 287 /* alias */
 288 #define st_dma dma_wd
 289 /* The two highest bytes of an extended DMA as a short; this is a must
 290  * for the Medusa.
 291  */
 292 #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
 293
 294 /*
 295 ** YM2149 Sound Chip
 296 ** access in bytes
 297  */
 298
 299 #define YM_BAS (0xffff8800)
 300 struct SOUND_YM
 301  {
 302   u_char rd_data_reg_sel;
 303   u_char char_dummy1;
 304   u_char wd_data;
 305  };
 306 #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
 307
 308 /* TT SCSI DMA */
 309
 310 #define TT_SCSI_DMA_BAS (0xffff8700)
 311 struct TT_DMA {
 312         u_char  char_dummy0;
 313         u_char  dma_addr_hi;
 314         u_char  char_dummy1;
 315         u_char  dma_addr_hmd;
 316         u_char  char_dummy2;
 317         u_char  dma_addr_lmd;
 318         u_char  char_dummy3;
 319         u_char  dma_addr_lo;
 320         u_char  char_dummy4;
 321         u_char  dma_cnt_hi;
 322         u_char  char_dummy5;
 323         u_char  dma_cnt_hmd;
 324         u_char  char_dummy6;
 325         u_char  dma_cnt_lmd;
 326         u_char  char_dummy7;
 327         u_char  dma_cnt_lo;
 328         u_long  dma_restdata;
 329         u_short dma_ctrl;
 330 };
 331 #define tt_scsi_dma     ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
 332
 333 /* TT SCSI Controller 5380 */
 334
 335 #define TT_5380_BAS     (0xffff8781)
 336 struct TT_5380 {
 337         u_char  scsi_data;
 338         u_char  char_dummy1;
 339         u_char  scsi_icr;
 340         u_char  char_dummy2;
 341         u_char  scsi_mode;
 342         u_char  char_dummy3;
 343         u_char  scsi_tcr;
 344         u_char  char_dummy4;
 345         u_char  scsi_idstat;
 346         u_char  char_dummy5;
 347         u_char  scsi_dmastat;
 348         u_char  char_dummy6;
 349         u_char  scsi_targrcv;
 350         u_char  char_dummy7;
 351         u_char  scsi_inircv;
 352 };
 353 #define tt_scsi                 ((*(volatile struct TT_5380 *)TT_5380_BAS))
 354 #define tt_scsi_regp    ((volatile char *)TT_5380_BAS)
 355
 356
 357 /*
 358 ** Falcon DMA Sound Subsystem
 359  */
 360
 361 #define MATRIX_BASE (0xffff8930)
 362 struct MATRIX
 363 {
 364   u_short source;
 365   u_short destination;
 366   u_char external_frequency_divider;
 367   u_char internal_frequency_divider;
 368 };
 369 #define matrix (*(volatile struct MATRIX *)MATRIX_BASE)
 370
 371 #define CODEC_BASE (0xffff8936)
 372 struct CODEC
 373 {
 374   u_char tracks;
 375   u_char input_source;
 376 #define CODEC_SOURCE_ADC        1
 377 #define CODEC_SOURCE_MATRIX     2
 378   u_char adc_source;
 379 #define ADC_SOURCE_RIGHT_PSG    1
 380 #define ADC_SOURCE_LEFT_PSG     2
 381   u_char gain;
 382 #define CODEC_GAIN_RIGHT        0x0f
 383 #define CODEC_GAIN_LEFT         0xf0
 384   u_char attenuation;
 385 #define CODEC_ATTENUATION_RIGHT 0x0f
 386 #define CODEC_ATTENUATION_LEFT  0xf0
 387   u_char unused1;
 388   u_char status;
 389 #define CODEC_OVERFLOW_RIGHT    1
 390 #define CODEC_OVERFLOW_LEFT     2
 391   u_char unused2, unused3, unused4, unused5;
 392   u_char gpio_directions;
 393 #define GPIO_IN                 0
 394 #define GPIO_OUT                1
 395   u_char unused6;
 396   u_char gpio_data;
 397 };
 398 #define codec (*(volatile struct CODEC *)CODEC_BASE)
 399
 400 /*
 401 ** Falcon Blitter
 402 */
 403
 404 #define BLT_BAS (0xffff8a00)
 405
 406 struct BLITTER
 407  {
 408   u_short halftone[16];
 409   u_short src_x_inc;
 410   u_short src_y_inc;
 411   u_long src_address;
 412   u_short endmask1;
 413   u_short endmask2;
 414   u_short endmask3;
 415   u_short dst_x_inc;
 416   u_short dst_y_inc;
 417   u_long dst_address;
 418   u_short wd_per_line;
 419   u_short ln_per_bb;
 420   u_short hlf_op_reg;
 421   u_short log_op_reg;
 422   u_short lin_nm_reg;
 423   u_short skew_reg;
 424  };
 425 # define blitter ((*(volatile struct BLITTER *)BLT_BAS))
 426
 427
 428 /*
 429 ** SCC Z8530
 430  */
 431
 432 #define SCC_BAS (0xffff8c81)
 433 struct SCC
 434  {
 435   u_char cha_a_ctrl;
 436   u_char char_dummy1;
 437   u_char cha_a_data;
 438   u_char char_dummy2;
 439   u_char cha_b_ctrl;
 440   u_char char_dummy3;
 441   u_char cha_b_data;
 442  };
 443 # define scc ((*(volatile struct SCC*)SCC_BAS))
 444
 445 /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
 446 # define st_escc ((*(volatile struct SCC*)0xfffffa31))
 447 # define st_escc_dsr ((*(volatile char *)0xfffffa39))
 448
 449 /* TT SCC DMA Controller (same chip as SCSI DMA) */
 450
 451 #define TT_SCC_DMA_BAS  (0xffff8c00)
 452 #define tt_scc_dma      ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
 453
 454 /*
 455 ** VIDEL Palette Register
 456  */
 457
 458 #define FPL_BAS (0xffff9800)
 459 struct VIDEL_PALETTE
 460  {
 461   u_long reg[256];
 462  };
 463 # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
 464
 465
 466 /*
 467 ** Falcon DSP Host Interface
 468  */
 469
 470 #define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
 471 struct DSP56K_HOST_INTERFACE {
 472   u_char icr;
 473 #define DSP56K_ICR_RREQ 0x01
 474 #define DSP56K_ICR_TREQ 0x02
 475 #define DSP56K_ICR_HF0  0x08
 476 #define DSP56K_ICR_HF1  0x10
 477 #define DSP56K_ICR_HM0  0x20
 478 #define DSP56K_ICR_HM1  0x40
 479 #define DSP56K_ICR_INIT 0x80
 480
 481   u_char cvr;
 482 #define DSP56K_CVR_HV_MASK 0x1f
 483 #define DSP56K_CVR_HC   0x80
 484
 485   u_char isr;
 486 #define DSP56K_ISR_RXDF 0x01
 487 #define DSP56K_ISR_TXDE 0x02
 488 #define DSP56K_ISR_TRDY 0x04
 489 #define DSP56K_ISR_HF2  0x08
 490 #define DSP56K_ISR_HF3  0x10
 491 #define DSP56K_ISR_DMA  0x40
 492 #define DSP56K_ISR_HREQ 0x80
 493
 494   u_char ivr;
 495
 496   union {
 497     u_char b[4];
 498     u_short w[2];
 499     u_long l;
 500   } data;
 501 };
 502 #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
 503
 504 /*
 505 ** MFP 68901
 506  */
 507
 508 #define MFP_BAS (0xfffffa01)
 509 struct MFP
 510  {
 511   u_char par_dt_reg;
 512   u_char char_dummy1;
 513   u_char active_edge;
 514   u_char char_dummy2;
 515   u_char data_dir;
 516   u_char char_dummy3;
 517   u_char int_en_a;
 518   u_char char_dummy4;
 519   u_char int_en_b;
 520   u_char char_dummy5;
 521   u_char int_pn_a;
 522   u_char char_dummy6;
 523   u_char int_pn_b;
 524   u_char char_dummy7;
 525   u_char int_sv_a;
 526   u_char char_dummy8;
 527   u_char int_sv_b;
 528   u_char char_dummy9;
 529   u_char int_mk_a;
 530   u_char char_dummy10;
 531   u_char int_mk_b;
 532   u_char char_dummy11;
 533   u_char vec_adr;
 534   u_char char_dummy12;
 535   u_char tim_ct_a;
 536   u_char char_dummy13;
 537   u_char tim_ct_b;
 538   u_char char_dummy14;
 539   u_char tim_ct_cd;
 540   u_char char_dummy15;
 541   u_char tim_dt_a;
 542   u_char char_dummy16;
 543   u_char tim_dt_b;
 544   u_char char_dummy17;
 545   u_char tim_dt_c;
 546   u_char char_dummy18;
 547   u_char tim_dt_d;
 548   u_char char_dummy19;
 549   u_char sync_char;
 550   u_char char_dummy20;
 551   u_char usart_ctr;
 552   u_char char_dummy21;
 553   u_char rcv_stat;
 554   u_char char_dummy22;
 555   u_char trn_stat;
 556   u_char char_dummy23;
 557   u_char usart_dta;
 558  };
 559 # define mfp ((*(volatile struct MFP*)MFP_BAS))
 560
 561 /* TT's second MFP */
 562
 563 #define TT_MFP_BAS      (0xfffffa81)
 564 # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
 565
 566
 567 /* TT System Control Unit */
 568
 569 #define TT_SCU_BAS      (0xffff8e01)
 570 struct TT_SCU {
 571         u_char  sys_mask;
 572         u_char  char_dummy1;
 573         u_char  sys_stat;
 574         u_char  char_dummy2;
 575         u_char  softint;
 576         u_char  char_dummy3;
 577         u_char  vmeint;
 578         u_char  char_dummy4;
 579         u_char  gp_reg1;
 580         u_char  char_dummy5;
 581         u_char  gp_reg2;
 582         u_char  char_dummy6;
 583         u_char  vme_mask;
 584         u_char  char_dummy7;
 585         u_char  vme_stat;
 586 };
 587 #define tt_scu  ((*(volatile struct TT_SCU *)TT_SCU_BAS))
 588
 589 /* TT real time clock */
 590
 591 #define TT_RTC_BAS      (0xffff8961)
 592 struct TT_RTC {
 593         u_char  regsel;
 594         u_char  dummy;
 595         u_char  data;
 596 };
 597 #define tt_rtc  ((*(volatile struct TT_RTC *)TT_RTC_BAS))
 598
 599
 600 /*
 601 ** ACIA 6850
 602  */
 603 /* constants for the ACIA registers */
 604
 605 /* baudrate selection and reset (Baudrate = clock/factor) */
 606 #define ACIA_DIV1  0
 607 #define ACIA_DIV16 1
 608 #define ACIA_DIV64 2
 609 #define ACIA_RESET 3
 610
 611 /* character format */
 612 #define ACIA_D7E2S (0<<2)       /* 7 data, even parity, 2 stop */
 613 #define ACIA_D7O2S (1<<2)       /* 7 data, odd parity, 2 stop */
 614 #define ACIA_D7E1S (2<<2)       /* 7 data, even parity, 1 stop */
 615 #define ACIA_D7O1S (3<<2)       /* 7 data, odd parity, 1 stop */
 616 #define ACIA_D8N2S (4<<2)       /* 8 data, no parity, 2 stop */
 617 #define ACIA_D8N1S (5<<2)       /* 8 data, no parity, 1 stop */
 618 #define ACIA_D8E1S (6<<2)       /* 8 data, even parity, 1 stop */
 619 #define ACIA_D8O1S (7<<2)       /* 8 data, odd parity, 1 stop */
 620
 621 /* transmit control */
 622 #define ACIA_RLTID (0<<5)       /* RTS low, TxINT disabled */
 623 #define ACIA_RLTIE (1<<5)       /* RTS low, TxINT enabled */
 624 #define ACIA_RHTID (2<<5)       /* RTS high, TxINT disabled */
 625 #define ACIA_RLTIDSB (3<<5)     /* RTS low, TxINT disabled, send break */
 626
 627 /* receive control */
 628 #define ACIA_RID (0<<7)         /* RxINT disabled */
 629 #define ACIA_RIE (1<<7)         /* RxINT enabled */
 630
 631 /* status fields of the ACIA */
 632 #define ACIA_RDRF 1             /* Receive Data Register Full */
 633 #define ACIA_TDRE (1<<1)        /* Transmit Data Register Empty */
 634 #define ACIA_DCD  (1<<2)        /* Data Carrier Detect */
 635 #define ACIA_CTS  (1<<3)        /* Clear To Send */
 636 #define ACIA_FE   (1<<4)        /* Framing Error */
 637 #define ACIA_OVRN (1<<5)        /* Receiver Overrun */
 638 #define ACIA_PE   (1<<6)        /* Parity Error */
 639 #define ACIA_IRQ  (1<<7)        /* Interrupt Request */
 640
 641 #define ACIA_BAS (0xfffffc00)
 642 struct ACIA
 643  {
 644   u_char key_ctrl;
 645   u_char char_dummy1;
 646   u_char key_data;
 647   u_char char_dummy2;
 648   u_char mid_ctrl;
 649   u_char char_dummy3;
 650   u_char mid_data;
 651  };
 652 # define acia ((*(volatile struct ACIA*)ACIA_BAS))
 653
 654 #define TT_DMASND_BAS (0xffff8900)
 655 struct TT_DMASND {
 656         u_char  int_ctrl;       /* Falcon: Interrupt control */
 657         u_char  ctrl;
 658         u_char  pad2;
 659         u_char  bas_hi;
 660         u_char  pad3;
 661         u_char  bas_mid;
 662         u_char  pad4;
 663         u_char  bas_low;
 664         u_char  pad5;
 665         u_char  addr_hi;
 666         u_char  pad6;
 667         u_char  addr_mid;
 668         u_char  pad7;
 669         u_char  addr_low;
 670         u_char  pad8;
 671         u_char  end_hi;
 672         u_char  pad9;
 673         u_char  end_mid;
 674         u_char  pad10;
 675         u_char  end_low;
 676         u_char  pad11[12];
 677         u_char  track_select;   /* Falcon */
 678         u_char  mode;
 679         u_char  pad12[14];
 680         /* Falcon only: */
 681         u_short cbar_src;
 682         u_short cbar_dst;
 683         u_char  ext_div;
 684         u_char  int_div;
 685         u_char  rec_track_select;
 686         u_char  dac_src;
 687         u_char  adc_src;
 688         u_char  input_gain;
 689         u_short output_atten;
 690 };
 691 # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
 692
 693 #define DMASND_MFP_INT_REPLAY     0x01
 694 #define DMASND_MFP_INT_RECORD     0x02
 695 #define DMASND_TIMERA_INT_REPLAY  0x04
 696 #define DMASND_TIMERA_INT_RECORD  0x08
 697
 698 #define DMASND_CTRL_OFF           0x00
 699 #define DMASND_CTRL_ON            0x01
 700 #define DMASND_CTRL_REPEAT        0x02
 701 #define DMASND_CTRL_RECORD_ON     0x10
 702 #define DMASND_CTRL_RECORD_OFF    0x00
 703 #define DMASND_CTRL_RECORD_REPEAT 0x20
 704 #define DMASND_CTRL_SELECT_REPLAY 0x00
 705 #define DMASND_CTRL_SELECT_RECORD 0x80
 706 #define DMASND_MODE_MONO          0x80
 707 #define DMASND_MODE_STEREO        0x00
 708 #define DMASND_MODE_8BIT          0x00
 709 #define DMASND_MODE_16BIT         0x40  /* Falcon only */
 710 #define DMASND_MODE_6KHZ          0x00  /* Falcon: mute */
 711 #define DMASND_MODE_12KHZ         0x01
 712 #define DMASND_MODE_25KHZ         0x02
 713 #define DMASND_MODE_50KHZ         0x03
 714
 715
 716 #define DMASNDSetBase(bufstart)                                         \
 717     do {                                                                \
 718         tt_dmasnd.bas_hi  = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
 719         tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
 720         tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
 721     } while( 0 )
 722
 723 #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) +     \
 724                         (tt_dmasnd.addr_mid << 8) +     \
 725                         (tt_dmasnd.addr_low))
 726
 727 #define DMASNDSetEnd(bufend)                            \
 728     do {                                                \
 729         tt_dmasnd.end_hi  = (unsigned char)(((bufend) & 0xff0000) >> 16); \
 730         tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
 731         tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
 732     } while( 0 )
 733
 734
 735 #define TT_MICROWIRE_BAS        (0xffff8922)
 736 struct TT_MICROWIRE {
 737         u_short data;
 738         u_short mask;
 739 };
 740 # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
 741
 742 #define MW_LM1992_ADDR          0x0400
 743
 744 #define MW_LM1992_VOLUME(dB)    \
 745     (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
 746 #define MW_LM1992_BALLEFT(dB)   \
 747     (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
 748 #define MW_LM1992_BALRIGHT(dB)  \
 749     (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
 750 #define MW_LM1992_TREBLE(dB)    \
 751     (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
 752 #define MW_LM1992_BASS(dB)      \
 753     (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
 754
 755 #define MW_LM1992_PSG_LOW       0x000
 756 #define MW_LM1992_PSG_HIGH      0x001
 757 #define MW_LM1992_PSG_OFF       0x002
 758
 759 #define MSTE_RTC_BAS    (0xfffffc21)
 760
 761 struct MSTE_RTC {
 762         u_char sec_ones;
 763         u_char dummy1;
 764         u_char sec_tens;
 765         u_char dummy2;
 766         u_char min_ones;
 767         u_char dummy3;
 768         u_char min_tens;
 769         u_char dummy4;
 770         u_char hr_ones;
 771         u_char dummy5;
 772         u_char hr_tens;
 773         u_char dummy6;
 774         u_char weekday;
 775         u_char dummy7;
 776         u_char day_ones;
 777         u_char dummy8;
 778         u_char day_tens;
 779         u_char dummy9;
 780         u_char mon_ones;
 781         u_char dummy10;
 782         u_char mon_tens;
 783         u_char dummy11;
 784         u_char year_ones;
 785         u_char dummy12;
 786         u_char year_tens;
 787         u_char dummy13;
 788         u_char mode;
 789         u_char dummy14;
 790         u_char test;
 791         u_char dummy15;
 792         u_char reset;
 793 };
 794
 795 #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
 796
 797 #endif /* linux/atarihw.h */
 798