i386/linux/linux-2.3.21/include/asm-mips/ng1hw.h

   1 /* This is the hardware interface for newport graphics.  It's taken from
   2    IRIX.
   3
   4    Alex deVries <puffin@redhat.com>
   5
   6 */
   7
   8
   9 #ifndef __SYS_NG1HW_H__
  10 #define __SYS_NG1HW_H__
  11
  12 #ident "$Revision: 1.1 $"
  13
  14 #define BIT(n)  (0x1 << n)
  15
  16
  17 #ifndef REX_ASMCODE
  18
  19 typedef union {
  20     volatile float flt;
  21     volatile unsigned int word;
  22 } float_long;
  23
  24 typedef volatile unsigned int vol_ulong;
  25 typedef volatile unsigned int fixed16;
  26
  27 typedef union {
  28     vol_ulong   byword;
  29     struct {
  30         volatile unsigned short s0;
  31         volatile unsigned short s1;
  32     } byshort;
  33     struct {
  34         volatile unsigned char b0, b1, b2;
  35         volatile unsigned char b3;
  36     } bybyte;
  37 } DCB_reg;
  38
  39 #ifndef REXSIM
  40 typedef struct rex3regs {       /* THE CHIP */
  41     vol_ulong drawmode1;        /* extra mode bits for GL       0x0000 */
  42     vol_ulong drawmode0;        /* command register             0x0004 */
  43
  44     vol_ulong lsmode;           /* line stipple mode            0x0008 */
  45     vol_ulong lspattern;        /* 32 bit pixel lspattern       0x000c */
  46     vol_ulong lspatsave;        /* save register for lspattern  0x0010 */
  47     vol_ulong zpattern;         /* 32 bit pixel zpattern        0x0014 */
  48
  49     vol_ulong colorback;        /* background color             0x0018 */
  50     vol_ulong colorvram;        /* fast vram clear color        0x001c */
  51     vol_ulong alpharef;         /* afunction reference value    0x0020 */
  52
  53     vol_ulong pad0;             /* padding                      0x0024 */
  54
  55     vol_ulong smask0x;          /* screen mask 0, window rel,   0x0028 */
  56     vol_ulong smask0y;          /* exclusively for the GL       0x002c */
  57     vol_ulong _setup;           /* do line/span setup, no iter  0x0030 */
  58     vol_ulong _stepz;           /* Enable ZPATTERN for this pix 0x0034 */
  59     vol_ulong _lsrestore;       /* Restore lspattern,count      0x0038 */
  60     vol_ulong _lssave;          /* Backup lspattern,count       0x003c */
  61
  62     char _pad1[0x100-0x40];
  63
  64     float_long _xstart;         /* 16.4(7) current x            0x0100 */
  65     float_long _ystart;         /* 16.4(7) current y            0x0104 */
  66     float_long _xend;           /* 16.4(7)                      0x0108 */
  67     float_long _yend;           /* 16.4(7)                      0x010c */
  68     vol_ulong xsave;            /* 16   x save for blocks       0x0110 */
  69     vol_ulong xymove;           /* x,y copy dest offset         0x0114 */
  70     float_long bresd;           /* s19.8 bres d error term      0x0118 */
  71     float_long bress1;          /* s2.15 bres s coverage term   0x011c */
  72     vol_ulong bresoctinc1;      /* 3(4)17.3 octant+inc1 value   0x0120 */
  73     volatile int bresrndinc2;   /* 8(3)18.3 bres inc2 value     0x0124 */
  74     vol_ulong brese1;           /* 1.15 bres e1 (minor slope)   0x0128 */
  75     vol_ulong bress2;           /* s18.8 bres s2 coverage term  0x012c */
  76     vol_ulong aweight0;         /* antialiasing weights         0x0130 */
  77     vol_ulong aweight1;         /* antialiasing weights         0x0134 */
  78     float_long xstartf;         /* 12.4(7) GL version of _xstart0x0138 */
  79     float_long ystartf;         /* 12.4(7)                      0x013c */
  80     float_long xendf;           /* 12.4(7)                      0x0140 */
  81     float_long yendf;           /* 12.4(7)                      0x0144 */
  82     fixed16 xstarti;            /* 16 integer format for xstart 0x0148 */
  83     float_long xendf1;          /* 12.4(7) same as xend         0x014c */
  84     fixed16 xystarti;           /* 16,16                        0x0150 */
  85     fixed16 xyendi;             /* 16,16                        0x0154 */
  86     fixed16 xstartendi;         /* 16,16                        0x0158 */
  87     char _pad2[0x200-0x15c];
  88     float_long colorred;        /* o12.11 red (also foreground) 0x0200 */
  89     float_long coloralpha;      /* o8.11 alpha                  0x0204 */
  90     float_long colorgrn;        /* o8.11 green                  0x0208 */
  91     float_long colorblue;       /* o8.11 blue                   0x020c */
  92     float_long slopered;        /* s9.11                        0x0210 */
  93     float_long slopealpha;      /* s9.11                        0x0214 */
  94     float_long slopegrn;        /* s9.11                        0x0218 */
  95     float_long slopeblue;       /* s9.11                        0x021c */
  96     vol_ulong wrmask;           /* writemask                    0x0220 */
  97     vol_ulong colori;           /* packed bgr/ci                0x0224 */
  98     float_long colorx;          /* 12.11 red (no overflow)      0x0228 */
  99     float_long slopered1;       /* same as slopered             0x022c */
 100     vol_ulong hostrw0;          /* host PIO/DMA port (msw)      0x0230 */
 101     vol_ulong hostrw1;          /* host PIO/DMA port (lsw)      0x0234 */
 102     vol_ulong dcbmode;          /* display ctrl bus mode reg    0x0238 */
 103     volatile int pad3;                                          /* 0x023c */
 104     DCB_reg dcbdata0;           /* display ctrl bus port (msw)  0x0240 */
 105     vol_ulong dcbdata1;         /* display ctrl bus port (lsw)  0x0244 */
 106 } Rex3regs;
 107
 108
 109 typedef struct configregs {
 110     vol_ulong smask1x;          /* screenmask1 right,left edges 0x1300 */
 111     vol_ulong smask1y;          /* screenmask1 bottom,top edges 0x1304 */
 112     vol_ulong smask2x;          /* screenmask2 right,left edges 0x1308 */
 113     vol_ulong smask2y;          /* screenmask2 bottom,top edges 0x130c */
 114     vol_ulong smask3x;          /* screenmask3 right,left edges 0x1310 */
 115     vol_ulong smask3y;          /* screenmask3 bottom,top edges 0x1314 */
 116     vol_ulong smask4x;          /* screenmask4 right,left edges 0x1318 */
 117     vol_ulong smask4y;          /* screenmask4 bottom,top edges 0x131c */
 118     vol_ulong topscan;          /* y coord of top screen line   0x1320 */
 119     vol_ulong xywin;            /* window offset                0x1324 */
 120     vol_ulong clipmode;         /* cid,smask settings           0x1328 */
 121     vol_ulong pad0;             /*                              0x132c */
 122     vol_ulong config;           /* miscellaneous  config bits   0x1330 */
 123     vol_ulong pad1;             /*                              0x1334 */
 124     vol_ulong status;           /* chip busy, FIFO, int status  0x1338 */
 125                                 /* read clears interrupt status bits   */
 126     vol_ulong ustatus;          /* padding on rex rev a, 'read-only' 0x133c */
 127                                 /* copy of status on rex rev b.        */
 128     vol_ulong dcbreset;         /* resets DCB and flushes BFIFO 0x1340 */
 129 } Configregs;
 130
 131 typedef struct rex3chip {
 132                 /* page 0 */
 133         struct rex3regs set;            /* 0x0000 */
 134         char _pad0[0x7fc-sizeof(struct rex3regs)];
 135         volatile unsigned int dummy; /* 0x7fc */
 136         struct rex3regs go;             /* 0x0800 */
 137
 138         char _pad1[0x1300-0x800-sizeof(struct rex3regs)];
 139
 140                 /* page 1 */
 141         struct {
 142             struct configregs set;      /* 0x1300 */
 143             char _pad0[0x800-sizeof(struct configregs)];
 144             struct configregs go;       /* 0x1b00 */
 145         } p1;
 146 } rex3Chip, Rex3chip;
 147
 148
 149 #endif /* REX_ASMCODE */
 150 #endif /* REXSIM */
 151
 152 /* Since alot of flags went away, define here as null bits
 153    and leave the code as it is for now,
 154    marking where we have to change stuff.
 155
 156    NONE of these should be defined !   - billt
 157    */
 158
 159 #define LSCONTINUE 0
 160 #define SHADECONTINUE 0
 161 #define XYCONTINUE 0
 162 #define XMAJOR 0
 163 #define YMAJOR 0
 164 #define QUADMODE 0
 165 #define LRQPOLY 0
 166 /* RGBMODE, DITHER now live in DM1 */
 167 #define RGBMODECMD 0
 168 #define DITHER 0
 169 #define DITHERRANGE 0
 170 /* BLOCK is a function of ADDRMODE */
 171 #define BLOCK 0
 172 #define STOPONX 0
 173 #define STOPONY 0
 174 /* COLORCOMPARE is a combo of 3 bits (<, = , >) */
 175 #define COLORCOMP 0
 176 /* FRACTIONS are gone... */
 177 #define INITFRAC 0
 178 #define FRACTION1 0
 179
 180 /* -- some old AUX1 junk -- */
 181 #define DOUBLEBUF 0
 182 #define DBLDST0 0
 183 #define DBLDST1 0
 184 #define DBLSRC 0
 185 #define COLORAUX 0
 186
 187
 188 /* --- a couple of old cmds also only for conversion --- */
 189 #define REX_LDPIXEL 0x1
 190 #define REX_ANTIAUX 0
 191 #define REX_DRAW 0
 192 #define LOGICSRC 0
 193 /* --- Blech! locicops are in DM1 too! */
 194 #define REX_LO_ZERO REX_LO_ZERO
 195 #define REX_LO_AND DM1_LO_AND
 196 #define REX_LO_ANDR DM1_LO_ANDR
 197 #define REX_LO_SRC DM1_LO_SRC
 198 #define REX_LO_ANDI DM1_LO_ANDI
 199 #define REX_LO_DST DM1_LO_DST
 200 #define REX_LO_XOR DM1_LO_XOR
 201 #define REX_LO_OR DM1_LO_OR
 202 #define REX_LO_NOR DM1_LO_NOR
 203 #define REX_LO_XNOR DM1_LO_XNOR
 204 #define REX_LO_NDST DM1_LO_NDST
 205 #define REX_LO_ORR DM1_LO_ORR
 206 #define REX_LO_NSRC DM1_LO_NSRC
 207 #define REX_LO_ORI DM1_LO_ORI
 208 #define REX_LO_NAND DM1_LO_NAND
 209 #define REX_LO_ONE DM1_LO_ONE
 210
 211
 212 /*
 213  *  drawmode flags
 214  */
 215 #define DM0_OPCODE      0x3             /* opcode(1:0)  */
 216 #       define DM0_NOP          0x0
 217 #       define DM0_READ         0x1
 218 #       define DM0_DRAW         0x2
 219 #       define DM0_SCR2SCR      0x3
 220 #define DM0_ADRMODE_SHIFT       2       /* adrmode(2:0) */
 221 #       define DM0_ADRMODE      (0x7<<DM0_ADRMODE_SHIFT)
 222 #       define DM0_SPAN         (0x0<<DM0_ADRMODE_SHIFT)
 223 #       define DM0_BLOCK        (0x1<<DM0_ADRMODE_SHIFT)
 224 #       define DM0_ILINE        (0x2<<DM0_ADRMODE_SHIFT)
 225 #       define DM0_FLINE        (0x3<<DM0_ADRMODE_SHIFT)
 226 #       define DM0_ALINE        (0x4<<DM0_ADRMODE_SHIFT)
 227 #ifdef OLDJUNK
 228
 229 /* XXX These definitions are obsolete */
 230
 231 #       define DM0_AELINE       (0x5<<DM0_ADRMODE_SHIFT)
 232 #       define DM0_ACWEDGE      (0x6<<DM0_ADRMODE_SHIFT)
 233 #       define DM0_ACCWEDGE     (0x7<<DM0_ADRMODE_SHIFT)
 234
 235 #else
 236
 237 /* XXX These are according to 11/2/92 spec */
 238
 239 #       define DM0_TLINE        (0x5<<DM0_ADRMODE_SHIFT)
 240 #       define DM0_BLINE        (0x6<<DM0_ADRMODE_SHIFT)
 241
 242 #endif /* OLDJUNK */
 243
 244 #define DM0_DOSETUP     BIT(5)
 245 #define DM0_COLORHOST   BIT(6)
 246 #define DM0_ALPHAHOST   BIT(7)
 247 #define DM0_STOPONX     BIT(8)
 248 #define DM0_STOPONY     BIT(9)
 249 #define DM0_STOPONXY    (DM0_STOPONX | DM0_STOPONY)
 250 #define DM0_SKIPFIRST   BIT(10)
 251 #define DM0_SKIPLAST    BIT(11)
 252 #define DM0_ENZPATTERN  BIT(12)
 253 #define DM0_ENLSPATTERN BIT(13)
 254 #define DM0_LSADVLAST   BIT(14)
 255 #define DM0_LENGTH32    BIT(15)
 256 #define DM0_ZOPAQUE     BIT(16)
 257 #define DM0_LSOPAQUE    BIT(17)
 258 #define DM0_SHADE       BIT(18)
 259 #define DM0_LRONLY      BIT(19)
 260
 261 #ifdef OLDJUNK
 262
 263 /* XXX These definitions are obsolete */
 264
 265 #define DM0_CICLAMP     BIT(20)
 266 #define DM0_ENDPTFILTER BIT(21)
 267
 268 #else
 269
 270 /* XXX These are according to 11/2/92 spec */
 271
 272 #define DM0_XYOFFSET    BIT(20)
 273 #define DM0_CICLAMP     BIT(21)
 274 #define DM0_ENDPTFILTER BIT(22)
 275
 276 #endif  /* OLDJUNK */
 277 /* New Feature in REX REV B */
 278 #define DM0_YSTRIDE     BIT(23)
 279
 280 #define DM1_PLANES_SHIFT        0
 281 #define DM1_PLANES      0x7             /* planes(2:0)  */
 282 #       define DM1_NOPLANES     0x0
 283 #       define DM1_RGBPLANES    0x1
 284 #       define DM1_RGBAPLANES   0x2
 285 #       define DM1_OLAYPLANES   0x4
 286 #       define DM1_PUPPLANES    0x5
 287 #       define DM1_CIDPLANES    0x6
 288 #define DM1_DRAWDEPTH_SHIFT     3       /* drawdepth(1:0)       */
 289 #define DM1_DRAWDEPTH_MASK      (3 << DM1_DRAWDEPTH_SHIFT)
 290 #       define DM1_DRAWDEPTH    (0x3 << DM1_DRAWDEPTH_SHIFT)
 291 #       define DM1_DRAWDEPTH4   (0x0 << DM1_DRAWDEPTH_SHIFT)
 292 #       define DM1_DRAWDEPTH8   (0x1 << DM1_DRAWDEPTH_SHIFT)
 293 #       define DM1_DRAWDEPTH12  (0x2 << DM1_DRAWDEPTH_SHIFT)
 294 #       define DM1_DRAWDEPTH24  (0x3 << DM1_DRAWDEPTH_SHIFT)
 295 #define DM1_DBLSRC              BIT(5)
 296 #define DM1_YFLIP               BIT(6)
 297 #define DM1_RWPACKED            BIT(7)
 298 #define DM1_HOSTDEPTH_SHIFT     8       /* hostdepth(1:0)       */
 299 #define DM1_HOSTDEPTH_MASK      (3 << DM1_HOSTDEPTH_SHIFT)
 300 #       define DM1_HOSTDEPTH    (0x3 << DM1_HOSTDEPTH_SHIFT)
 301 #       define DM1_HOSTDEPTH4   (0x0 << DM1_HOSTDEPTH_SHIFT)
 302 #       define DM1_HOSTDEPTH8   (0x1 << DM1_HOSTDEPTH_SHIFT)
 303 #       define DM1_HOSTDEPTH12  (0x2 << DM1_HOSTDEPTH_SHIFT)
 304 #       define DM1_HOSTDEPTH32  (0x3 << DM1_HOSTDEPTH_SHIFT)
 305 #define DM1_RWDOUBLE            BIT(10)
 306 #define DM1_SWAPENDIAN          BIT(11)
 307 #define DM1_COLORCOMPARE_SHIFT  12      /* compare (2:0)        */
 308 #define DM1_COLORCOMPARE_MASK  (7 << DM1_COLORCOMPARE_SHIFT)
 309 #       define DM1_COLORCOMPARE (0x7 << DM1_COLORCOMPARE_SHIFT)
 310 #       define DM1_COLORCOMPLT  BIT(12)
 311 #       define DM1_COLORCOMPEQ  BIT(13)
 312 #       define DM1_COLORCOMPGT  BIT(14)
 313 #define DM1_RGBMODE             BIT(15)
 314 #define DM1_ENDITHER            BIT(16)
 315 #define DM1_FASTCLEAR           BIT(17)
 316 #define DM1_ENBLEND             BIT(18)
 317 #define DM1_SF_SHIFT            19      /* sfactor(2:0) */
 318 #define DM1_SF_MASK             (7 << DM1_SF_SHIFT)
 319 #       define DM1_SF           (0x7 << DM1_SF_SHIFT)
 320 #       define DM1_SF_ZERO      (0x0 << DM1_SF_SHIFT)
 321 #       define DM1_SF_ONE       (0x1 << DM1_SF_SHIFT)
 322 #       define DM1_SF_DC        (0x2 << DM1_SF_SHIFT)
 323 #       define DM1_SF_MDC       (0x3 << DM1_SF_SHIFT)
 324 #       define DM1_SF_SA        (0x4 << DM1_SF_SHIFT)
 325 #       define DM1_SF_MSA       (0x5 << DM1_SF_SHIFT)
 326 #define DM1_DF_SHIFT            22      /* dfactor(2:0) */
 327 #define DM1_DF_MASK     (7 << DM1_DF_SHIFT)
 328 #       define DM1_DF           (0x7 << DM1_DF_SHIFT)
 329 #       define DM1_DF_ZERO      (0x0 << DM1_DF_SHIFT)
 330 #       define DM1_DF_ONE       (0x1 << DM1_DF_SHIFT)
 331 #       define DM1_DF_SC        (0x2 << DM1_DF_SHIFT)
 332 #       define DM1_DF_MSC       (0x3 << DM1_DF_SHIFT)
 333 #       define DM1_DF_SA        (0x4 << DM1_DF_SHIFT)
 334 #       define DM1_DF_MSA       (0x5 << DM1_DF_SHIFT)
 335 #define DM1_ENBACKBLEND         BIT(25)
 336 #define DM1_ENPREFETCH          BIT(26)
 337 #define DM1_BLENDALPHA          BIT(27)
 338 #define DM1_LO_SHIFT            28      /* logicop(3:0) */
 339 #       define DM1_LO           (0xF << DM1_LO_SHIFT)
 340 #       define DM1_LO_MASK      DM1_LO
 341 #       define DM1_LO_ZERO      (0x0 << DM1_LO_SHIFT)
 342 #       define DM1_LO_AND       (0x1 << DM1_LO_SHIFT)
 343 #       define DM1_LO_ANDR      (0x2 << DM1_LO_SHIFT)
 344 #       define DM1_LO_SRC       (0x3 << DM1_LO_SHIFT)
 345 #       define DM1_LO_ANDI      (0x4 << DM1_LO_SHIFT)
 346 #       define DM1_LO_DST       (0x5 << DM1_LO_SHIFT)
 347 #       define DM1_LO_XOR       (0x6 << DM1_LO_SHIFT)
 348 #       define DM1_LO_OR        (0x7 << DM1_LO_SHIFT)
 349 #       define DM1_LO_NOR       (0x8 << DM1_LO_SHIFT)
 350 #       define DM1_LO_XNOR      (0x9 << DM1_LO_SHIFT)
 351 #       define DM1_LO_NDST      (0xa << DM1_LO_SHIFT)
 352 #       define DM1_LO_ORR       (0xb << DM1_LO_SHIFT)
 353 #       define DM1_LO_NSRC      (0xc << DM1_LO_SHIFT)
 354 #       define DM1_LO_ORI       (0xd << DM1_LO_SHIFT)
 355 #       define DM1_LO_NAND      (0xe << DM1_LO_SHIFT)
 356 #       define DM1_LO_ONE       (0xf << DM1_LO_SHIFT)
 357
 358
 359
 360 /*
 361  * Clipmode register bits
 362  */
 363
 364 #define SMASK0  BIT(0)
 365 #define SMASK1  BIT(1)
 366 #define SMASK2  BIT(2)
 367 #define SMASK3  BIT(3)
 368 #define SMASK4  BIT(4)
 369 #define ALL_SMASKS      31
 370
 371 #define CM_CIDMATCH_SHIFT       9
 372 #define CM_CIDMATCH_MASK        (0xf << CM_CIDMATCH_SHIFT)
 373
 374
 375 /*
 376  * Status register bits
 377  */
 378
 379 #define REX3VERSION_MASK 7
 380 #define GFXBUSY         BIT(3)
 381 #define BACKBUSY        BIT(4)
 382 #define VRINT           BIT(5)
 383 #define VIDEOINT        BIT(6)
 384 #define GFIFO_LEVEL_SHIFT       7
 385 #define GFIFO_LEVEL_MASK        (0x3f << GFIFO_LEVEL_SHIFT)
 386 #define BFIFO_LEVEL_SHIFT       13
 387 #define BFIFO_LEVEL_MASK        (0x1f << BFIFO_LEVEL_SHIFT)
 388 #define BFIFO_INT        BIT(18)
 389 #define GFIFO_INT        BIT(19)
 390
 391
 392 /*
 393  * Config register bits
 394  */
 395
 396 #define GIO32MODE       BIT(0)
 397 #define BUSWIDTH        BIT(1)
 398 #define EXTREGXCVR      BIT(2)
 399 #define BFIFODEPTH_SHIFT        3
 400 #define BFIFODEPTH_MASK         (0xf << BFIFODEPTH_SHIFT)
 401 #define BFIFOABOVEINT   BIT(7)
 402 #define GFIFODEPTH_SHIFT        8
 403 #define GFIFODEPTH_MASK         (0x1f << GFIFODEPTH_SHIFT)
 404 #define GFIFOABOVEINT   BIT(13)
 405 #define TIMEOUT_SHIFT   14
 406 #define TIMEOUT_MASK    (7 << TIMEOUT_SHIFT)
 407 #define VREFRESH_SHIFT  17
 408 #define VREFRESH_MASK   (0x7 << VREFRESH_SHIFT)
 409 #define FB_TYPE         BIT(20)
 410
 411 /*
 412  * Display Control Bus (DCB) macros
 413  */
 414
 415 #define DCB_DATAWIDTH_MASK  (0x3)
 416 #define DCB_ENDATAPACK      BIT(2)
 417 #define DCB_ENCRSINC        BIT(3)
 418 #define DCB_CRS_SHIFT    4
 419 #define DCB_CRS_MASK     (0x7 << DCB_CRS_SHIFT)
 420 #define DCB_ADDR_SHIFT   7
 421 #define DCB_ADDR_MASK    (0xf << DCB_ADDR_SHIFT)
 422 #define DCB_ENSYNCACK       BIT(11)
 423 #define DCB_ENASYNCACK      BIT(12)
 424 #define DCB_CSWIDTH_SHIFT   13
 425 #define DCB_CSWIDTH_MASK    (0x1f << CSWIDTH_SHIFT)
 426 #define DCB_CSHOLD_SHIFT    18
 427 #define DCB_CSHOLD_MASK     (0x1f << CSHOLD_SHIFT)
 428 #define DCB_CSSETUP_SHIFT   23
 429 #define DCB_CSSETUP_MASK    (0x1f << CSSETUP_SHIFT)
 430 #define DCB_SWAPENDIAN      BIT(28)
 431
 432
 433 /*
 434  * Some values for DCBMODE fields
 435  */
 436 #define DCB_DATAWIDTH_4         0x0
 437 #define DCB_DATAWIDTH_1         0x1
 438 #define DCB_DATAWIDTH_2         0x2
 439 #define DCB_DATAWIDTH_3         0x3
 440
 441
 442 /*
 443  * DCB_ADDR values to select the various dcb slave devices
 444  */
 445 #define DCB_VC2          (0 << DCB_ADDR_SHIFT)
 446 #define DCB_CMAP_ALL     (1 << DCB_ADDR_SHIFT)
 447 #define DCB_CMAP0        (2 << DCB_ADDR_SHIFT)
 448 #define DCB_CMAP1        (3 << DCB_ADDR_SHIFT)
 449 #define DCB_XMAP_ALL     (4 << DCB_ADDR_SHIFT)
 450 #define DCB_XMAP0        (5 << DCB_ADDR_SHIFT)
 451 #define DCB_XMAP1        (6 << DCB_ADDR_SHIFT)
 452 #define DCB_BT445        (7 << DCB_ADDR_SHIFT)
 453 #define DCB_VCC1         (8 << DCB_ADDR_SHIFT)
 454 #define DCB_VAB1         (9 << DCB_ADDR_SHIFT)
 455 #define DCB_LG3_BDVERS0      (10 << DCB_ADDR_SHIFT)
 456 #define DCB_LG3_ICS1562      (11 << DCB_ADDR_SHIFT)
 457 #define DCB_RESERVED     (15 << DCB_ADDR_SHIFT)
 458
 459 /*
 460  * New DCB Addresses which are used in (new) Indigo2 Video and Galileo 1.5
 461  * since these boards have to work with Mardi Gras also. Yet, these
 462  * are not necessarily the MGRAS address, these translate to the Mardi Gras
 463  * addresses when the lower 2 bits are swapped (which will happen on
 464  * the Newport to new video board flex cable).
 465  */
 466 #define DCB_VAB1_NEW     (9 << DCB_ADDR_SHIFT)
 467 /*
 468  * While the Presenter is currently using address 12 and
 469  * conflicting with the CC1, it has been changed for Mardi Gras
 470  * To use the new video boards with Newport (an unreleased product)
 471  * the presenter probe must be disabled by changing the presenter
 472  * DCB address in gfx/kern/sys/pcd.h (and possibly
 473  * lotus/stand/arcs/lib/libsk/graphics/NEWPORT/pcd.h), so
 474  * it is probed at address 11.  This will of course not work with
 475  * the presenter card but it will allow you to test new video
 476  * boards will Newport
 477  */
 478
 479 #define DCB_VCC1_NEW     (12 << DCB_ADDR_SHIFT)
 480 /*#define DCB_VCC1_NEW     (8 << DCB_ADDR_SHIFT)*/
 481
 482 /*
 483  * Addresses being used for Galileo 1.5.
 484  */
 485 #define DCB_VCC1_GAL     (8 << DCB_ADDR_SHIFT) /* was 12 and will return */
 486 #define DCB_VAB1_GAL     (9 << DCB_ADDR_SHIFT)
 487 #define DCB_TMI_CSC      (13 << DCB_ADDR_SHIFT)
 488 #define DCB_GAL          (14 << DCB_ADDR_SHIFT)
 489
 490 /*
 491  * LG3 - (Newport for Fullhouse) board defines
 492  */
 493 /* Version 0 register */
 494 #define LG3_VC2_UNRESET BIT(0)
 495 #define LG3_GFX_UNRESET BIT(1)
 496 #define LG3_PLL_UNRESET BIT(2)
 497 #define LG3_DLHD_MASTER BIT(3)
 498
 499 #define LG3_BDVERS_PROTOCOL ((2 << DCB_CSWIDTH_SHIFT) | (1 << DCB_CSHOLD_SHIFT) | (1 << DCB_CSSETUP_SHIFT))
 500
 501 #define lg3BdVersGet(rex3, data)                                        \
 502         rex3->set.dcbmode = DCB_LG3_BDVERS0 | \
 503                 LG3_BDVERS_PROTOCOL | DCB_DATAWIDTH_1 ;                 \
 504         data = rex3->set.dcbdata0.bybyte.b3
 505
 506 #define lg3BdVersSet(rex3, data)                                        \
 507         rex3->set.dcbmode = DCB_LG3_BDVERS0 | \
 508                 LG3_BDVERS_PROTOCOL | DCB_DATAWIDTH_1 ;         \
 509         rex3->set.dcbdata0.bybyte.b3 = (data)
 510
 511 #define Ics1562Set(rex3, data)                                  \
 512         rex3->set.dcbmode = DCB_LG3_ICS1562 | LG3_BDVERS_PROTOCOL | DCB_DATAWIDTH_1 ; \
 513         rex3->set.dcbdata0.bybyte.b3 = (data)
 514
 515 #define LG3_BD_001      0x7
 516 #define LG3_BD_002      0x0
 517 /*
 518  * Lsmode register bits
 519  */
 520 #define LSRCOUNT_SHIFT  0
 521 #define LSRCOUNT_MASK   (0xff << LSRCOUNT_SHIFT)
 522 #define LSREPEAT_SHIFT  8
 523 #define LSREPEAT_MASK   (0xff << LSREPEAT_SHIFT)
 524 #define LSRCNTSAVE_SHIFT        16
 525 #define LSRCNTSAVE_MASK (0xff << LSRCNTSAVE_SHIFT)
 526 #define LSLENGTH_SHIFT  24
 527 #define LSLENGTH_MASK   (0xf << LSLENGTH_SHIFT)
 528
 529 #if     defined ( _KERNEL ) && defined ( REX3_RUNTIME_REV_CHECK )
 530
 531 extern void _newport_poll_status (register struct rex3chip *, register int);
 532
 533 #define REX3WAIT(rex3)  _newport_poll_status (rex3, GFXBUSY)
 534 #define BFIFOWAIT(rex3)  _newport_poll_status (rex3, BACKBUSY)
 535
 536 #else
 537
 538 /* XXX  When we drop support for rex rev b,
 539  * change status to ustatus in the macros below.
 540  */
 541 #define REX3WAIT(rex3)  while ((rex3)->p1.set.status & GFXBUSY)
 542 #define BFIFOWAIT(rex3)  while ((rex3)->p1.set.status & BACKBUSY)
 543
 544 #endif
 545
 546 /*
 547  * Legal GIO bus addresses for Newport graphics boards.
 548  */
 549 #define REX3_GIO_ADDR_0         0x1f0f0000
 550 #define REX3_GIO_ADDR_1         0x1f4f0000
 551 #define REX3_GIO_ADDR_2         0x1f8f0000
 552 #define REX3_GIO_ADDR_3         0x1fcf0000
 553
 554 #define NG1_XSIZE       1280    /* screen size in x */
 555 #define NG1_YSIZE       1024    /* screen size in y */
 556
 557 /*
 558  * XXX Correct values TBD.  Depends on video timing
 559  */
 560 #define CURSOR_XOFF 29
 561 #define CURSOR_YOFF 31
 562
 563 #ifdef _STANDALONE
 564 struct rex3chip;
 565 struct ng1_info;
 566 void Ng1RegisterInit(struct rex3chip *, struct ng1_info *);
 567 extern int ng1checkboard(void);
 568 extern void vc2LoadSRAM(struct rex3chip *, unsigned short *,
 569                 unsigned int , unsigned int);
 570 #endif
 571
 572 #endif /* __SYS_NG1HW_H__ */