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* added 0.99 linux version
[mascara-docs.git] / i386 / linux / linux-2.3.21 / include / asm-sparc / system.h
blobb489cac95a666a7165f09efbbb43fb8659620efd
1 /* $Id: system.h,v 1.75 1999/09/01 08:06:08 davem Exp $ */
2 #include <linux/config.h>
3
4 #ifndef __SPARC_SYSTEM_H
5 #define __SPARC_SYSTEM_H
6
7 #include <linux/kernel.h>
8
9 #include <asm/segment.h>
10
11 #ifdef __KERNEL__
12 #include <asm/page.h>
13 #include <asm/oplib.h>
14 #include <asm/psr.h>
15 #include <asm/ptrace.h>
16 #include <asm/btfixup.h>
17
18 #define EMPTY_PGT (&empty_bad_page)
19 #define EMPTY_PGE (&empty_bad_page_table)
20 #endif /* __KERNEL__ */
21
22 #ifndef __ASSEMBLY__
23
24 /*
25 * Sparc (general) CPU types
26 */
27 enum sparc_cpu {
28 sun4 = 0x00,
29 sun4c = 0x01,
30 sun4m = 0x02,
31 sun4d = 0x03,
32 sun4e = 0x04,
33 sun4u = 0x05, /* V8 ploos ploos */
34 sun_unknown = 0x06,
35 ap1000 = 0x07, /* almost a sun4m */
36 };
37
38 /* Really, userland should not be looking at any of this... */
39 #ifdef __KERNEL__
40
41 extern enum sparc_cpu sparc_cpu_model;
42
43 #ifndef CONFIG_SUN4
44 #define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
45 #define ARCH_SUN4 0
46 #else
47 #define ARCH_SUN4C_SUN4 1
48 #define ARCH_SUN4 1
49 #endif
50
51 #define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
52
53 extern unsigned long empty_bad_page;
54 extern unsigned long empty_bad_page_table;
55 extern unsigned long empty_zero_page;
56
57 extern struct linux_romvec *romvec;
58 #define halt() romvec->pv_halt()
59
60 /* When a context switch happens we must flush all user windows so that
61 * the windows of the current process are flushed onto its stack. This
62 * way the windows are all clean for the next process and the stack
63 * frames are up to date.
64 */
65 extern void flush_user_windows(void);
66 extern void kill_user_windows(void);
67 extern void synchronize_user_stack(void);
68 extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
69 void *fpqueue, unsigned long *fpqdepth);
70
71 #ifdef __SMP__
72 #define SWITCH_ENTER \
73 if(prev->flags & PF_USEDFPU) { \
74 put_psr(get_psr() | PSR_EF); \
75 fpsave(&prev->tss.float_regs[0], &prev->tss.fsr, \
76 &prev->tss.fpqueue[0], &prev->tss.fpqdepth); \
77 prev->flags &= ~PF_USEDFPU; \
78 prev->tss.kregs->psr &= ~PSR_EF; \
79 }
80
81 #define SWITCH_DO_LAZY_FPU
82 #else
83 #define SWITCH_ENTER
84 #define SWITCH_DO_LAZY_FPU if(last_task_used_math != next) next->tss.kregs->psr&=~PSR_EF;
85 #endif
86
87 /* Much care has gone into this code, do not touch it.
88 *
89 * We need to loadup regs l0/l1 for the newly forked child
90 * case because the trap return path relies on those registers
91 * holding certain values, gcc is told that they are clobbered.
92 * Gcc needs registers for 3 values in and 1 value out, so we
93 * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
94 */
95 #define switch_to(prev, next, last) do { \
96 __label__ here; \
97 register unsigned long task_pc asm("o7"); \
98 extern struct task_struct *current_set[NR_CPUS]; \
99 SWITCH_ENTER \
100 SWITCH_DO_LAZY_FPU \
101 __asm__ __volatile__( \
102 ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
103 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
104 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
105 "save %sp, -0x40, %sp\n\t" \
106 "restore; restore; restore; restore; restore; restore; restore"); \
107 if(!(next->tss.flags & SPARC_FLAG_KTHREAD) && \
108 !(next->flags & PF_EXITING)) \
109 switch_to_context(next); \
110 next->mm->cpu_vm_mask |= (1 << smp_processor_id()); \
111 task_pc = ((unsigned long) &&here) - 0x8; \
112 __asm__ __volatile__( \
113 "mov %%g6, %%g3\n\t" \
114 "rd %%psr, %%g4\n\t" \
115 "std %%sp, [%%g6 + %4]\n\t" \
116 "rd %%wim, %%g5\n\t" \
117 "wr %%g4, 0x20, %%psr\n\t" \
118 "nop\n\t" \
119 "std %%g4, [%%g6 + %3]\n\t" \
120 "ldd [%2 + %3], %%g4\n\t" \
121 "mov %2, %%g6\n\t" \
122 ".globl patchme_store_new_current\n" \
123 "patchme_store_new_current:\n\t" \
124 "st %2, [%1]\n\t" \
125 "wr %%g4, 0x20, %%psr\n\t" \
126 "nop\n\t" \
127 "nop\n\t" \
128 "ldd [%%g6 + %4], %%sp\n\t" \
129 "wr %%g5, 0x0, %%wim\n\t" \
130 "ldd [%%sp + 0x00], %%l0\n\t" \
131 "ldd [%%sp + 0x38], %%i6\n\t" \
132 "wr %%g4, 0x0, %%psr\n\t" \
133 "nop\n\t" \
134 "nop\n\t" \
135 "jmpl %%o7 + 0x8, %%g0\n\t" \
136 " mov %%g3, %0\n\t" \
137 : "=&r" (last) \
138 : "r" (&(current_set[hard_smp_processor_id()])), "r" (next), \
139 "i" ((const unsigned long)(&((struct task_struct *)0)->tss.kpsr)), \
140 "i" ((const unsigned long)(&((struct task_struct *)0)->tss.ksp)), \
141 "r" (task_pc) \
142 : "g1", "g2", "g3", "g4", "g5", "g7", "l0", "l1", \
143 "l4", "l5", "l6", "l7", "i0", "i1", "i2", "i3", "i4", "i5", "o0", "o1", "o2", \
144 "o3"); \
145 here: } while(0)
146
147 /* Changing the IRQ level on the Sparc. We now avoid writing the psr
148 * whenever possible.
149 */
150 extern __inline__ void setipl(unsigned long __orig_psr)
151 {
152 __asm__ __volatile__("
153 wr %0, 0x0, %%psr
154 nop; nop; nop
155 " : /* no outputs */
156 : "r" (__orig_psr)
157 : "memory", "cc");
158 }
159
160 extern __inline__ void __cli(void)
161 {
162 unsigned long tmp;
163
164 __asm__ __volatile__("
165 rd %%psr, %0
166 nop; nop; nop; /* Sun4m + Cypress + SMP bug */
167 or %0, %1, %0
168 wr %0, 0x0, %%psr
169 nop; nop; nop
170 " : "=r" (tmp)
171 : "i" (PSR_PIL)
172 : "memory");
173 }
174
175 extern __inline__ void __sti(void)
176 {
177 unsigned long tmp;
178
179 __asm__ __volatile__("
180 rd %%psr, %0
181 nop; nop; nop; /* Sun4m + Cypress + SMP bug */
182 andn %0, %1, %0
183 wr %0, 0x0, %%psr
184 nop; nop; nop
185 " : "=r" (tmp)
186 : "i" (PSR_PIL)
187 : "memory");
188 }
189
190 extern __inline__ unsigned long getipl(void)
191 {
192 unsigned long retval;
193
194 __asm__ __volatile__("rd %%psr, %0" : "=r" (retval));
195 return retval;
196 }
197
198 extern __inline__ unsigned long swap_pil(unsigned long __new_psr)
199 {
200 unsigned long retval;
201
202 __asm__ __volatile__("
203 rd %%psr, %0
204 nop; nop; nop; /* Sun4m + Cypress + SMP bug */
205 and %0, %2, %%g1
206 and %1, %2, %%g2
207 xorcc %%g1, %%g2, %%g0
208 be 1f
209 nop
210 wr %0, %2, %%psr
211 nop; nop; nop;
212 1:
213 " : "=r" (retval)
214 : "r" (__new_psr), "i" (PSR_PIL)
215 : "g1", "g2", "memory", "cc");
216
217 return retval;
218 }
219
220 extern __inline__ unsigned long read_psr_and_cli(void)
221 {
222 unsigned long retval;
223
224 __asm__ __volatile__("
225 rd %%psr, %0
226 nop; nop; nop; /* Sun4m + Cypress + SMP bug */
227 or %0, %1, %%g1
228 wr %%g1, 0x0, %%psr
229 nop; nop; nop
230 " : "=r" (retval)
231 : "i" (PSR_PIL)
232 : "g1", "memory");
233
234 return retval;
235 }
236
237 #define __save_flags(flags) ((flags) = getipl())
238 #define __save_and_cli(flags) ((flags) = read_psr_and_cli())
239 #define __restore_flags(flags) setipl((flags))
240
241 #ifdef __SMP__
242
243 /* This goes away after lockups have been found... */
244 #ifndef DEBUG_IRQLOCK
245 #define DEBUG_IRQLOCK
246 #endif
247
248 extern unsigned char global_irq_holder;
249
250 #define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
251
252 #ifdef DEBUG_IRQLOCK
253 extern void __global_cli(void);
254 extern void __global_sti(void);
255 extern unsigned long __global_save_flags(void);
256 extern void __global_restore_flags(unsigned long flags);
257 #define cli() __global_cli()
258 #define sti() __global_sti()
259 #define save_flags(flags) ((flags)=__global_save_flags())
260 #define restore_flags(flags) __global_restore_flags(flags)
261 #else
262
263 #error For combined sun4[md] smp, we need to get rid of the rdtbr.
264
265 /* Visit arch/sparc/lib/irqlock.S for all the fun details... */
266 #define cli() __asm__ __volatile__("mov %%o7, %%g4\n\t" \
267 "call ___f_global_cli\n\t" \
268 " rd %%tbr, %%g7" : : \
269 : "g1", "g2", "g3", "g4", "g5", "g7", \
270 "memory", "cc")
271
272 #define sti() \
273 do { register unsigned long bits asm("g7"); \
274 bits = 0; \
275 __asm__ __volatile__("mov %%o7, %%g4\n\t" \
276 "call ___f_global_sti\n\t" \
277 " rd %%tbr, %%g2" \
278 : /* no outputs */ \
279 : "r" (bits) \
280 : "g1", "g2", "g3", "g4", "g5", \
281 "memory", "cc"); \
282 } while(0)
283
284 #define restore_flags(flags) \
285 do { register unsigned long bits asm("g7"); \
286 bits = flags; \
287 __asm__ __volatile__("mov %%o7, %%g4\n\t" \
288 "call ___f_global_restore_flags\n\t" \
289 " andcc %%g7, 0x1, %%g0" \
290 : "=&r" (bits) \
291 : "0" (bits) \
292 : "g1", "g2", "g3", "g4", "g5", \
293 "memory", "cc"); \
294 } while(0)
295
296 #endif /* DEBUG_IRQLOCK */
297
298 #else
299
300 #define cli() __cli()
301 #define sti() __sti()
302 #define save_flags(x) __save_flags(x)
303 #define restore_flags(x) __restore_flags(x)
304 #define save_and_cli(x) __save_and_cli(x)
305
306 #endif
307
308 /* XXX Change this if we ever use a PSO mode kernel. */
309 #define mb() __asm__ __volatile__ ("" : : : "memory")
310 #define rmb() mb()
311 #define wmb() mb()
312 #define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
313 #define set_rmb(__var, __value) set_mb(__var, __value)
314 #define set_wmb(__var, __value) set_mb(__var, __value)
315
316 #define nop() __asm__ __volatile__ ("nop");
317
318 /* This has special calling conventions */
319 #ifndef __SMP__
320 BTFIXUPDEF_CALL(void, ___xchg32, void)
321 #endif
322
323 extern __inline__ unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
324 {
325 #ifdef __SMP__
326 __asm__ __volatile__("swap [%2], %0"
327 : "=&r" (val)
328 : "0" (val), "r" (m));
329 return val;
330 #else
331 register unsigned long *ptr asm("g1");
332 register unsigned long ret asm("g2");
333
334 ptr = (unsigned long *) m;
335 ret = val;
336
337 /* Note: this is magic and the nop there is
338 really needed. */
339 __asm__ __volatile__("
340 mov %%o7, %%g4
341 call ___f____xchg32
342 nop
343 " : "=&r" (ret)
344 : "0" (ret), "r" (ptr)
345 : "g3", "g4", "g7", "memory", "cc");
346
347 return ret;
348 #endif
349 }
350
351 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
352 #define tas(ptr) (xchg((ptr),1))
353
354 extern void __xchg_called_with_bad_pointer(void);
355
356 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
357 {
358 switch (size) {
359 case 4:
360 return xchg_u32(ptr, x);
361 };
362 __xchg_called_with_bad_pointer();
363 return x;
364 }
365
366 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
367
368 #endif /* __KERNEL__ */
369
370 #endif /* __ASSEMBLY__ */
371
372 #endif /* !(__SPARC_SYSTEM_H) */