i386/linux/linux-2.3.21/include/asm-sparc64/firehose.h

   1 /* $Id: firehose.h,v 1.4 1998/12/02 10:16:47 davem Exp $
   2  * firehose.h: Defines for the Fire Hose Controller (FHC) found
   3  *             on Sunfire/Starfire/Wildfire systems.
   4  *
   5  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #ifndef _SPARC64_FIREHOSE_H
   9 #define _SPARC64_FIREHOSE_H
  10
  11 #include <linux/types.h>
  12
  13 /* Fire Hose Controller Internal Registers */
  14 struct fhc_internal_regs {
  15 /*0x0000*/      u32     fhc_id;         /* FHC ID Register                      */
  16                 u32     _unused1[3];
  17 /*0x0010*/      u32     fhc_rcs;        /* FHC Reset Control/Status Register    */
  18                 u32     _unused2[3];
  19 /*0x0020*/      u32     fhc_control;    /* FHC Control Register                 */
  20                 u32     _unused3[3];
  21 /*0x0030*/      u32     fhc_bsr;        /* FHC Board Status Register            */
  22                 u32     _unused4[3];
  23 /*0x0040*/      u32     fhc_ecc;        /* FHC ECC Control Register (16 bits)   */
  24                 u32     _unused5[43];
  25 /*0x00f0*/      u32     fhc_jtag_ctrl;  /* FHC JTAG Control Register            */
  26                 u32     _unused6[3];
  27 /*0x0100*/      u32     fhc_jtag_cmd;   /* FHC JTAG Command Register            */
  28 };
  29
  30 /* Part of same space of regs, but mapped separately in PROM reg property
  31  * for the FHC, thus we have the following few structs...
  32  */
  33 struct fhc_ign_reg {
  34 /*0x2000*/      u32     fhc_ign;                /* FHC Interrupt Group Number   */
  35 };
  36
  37 struct fhc_fanfail_regs {
  38 /*0x4000*/      u32     fhc_ff_imap;            /* FHC FanFail Interrupt Map    */
  39                 u32     _pad[3];
  40 /*0x4010*/      u32     fhc_ff_iclr;            /* FHC FanFail Interrupt Clear  */
  41 };
  42
  43 struct fhc_system_regs {
  44 /*0x6000*/      u32     fhc_sys_imap;           /* FHC System Interrupt Map     */
  45                 u32     _pad[3];
  46 /*0x6010*/      u32     fhc_sys_iclr;           /* FHC System Interrupt Clear   */
  47 };
  48
  49 struct fhc_uart_regs {
  50 /*0x8000*/      u32     fhc_uart_imap;          /* FHC UART Interrupt Map       */
  51                 u32     _pad[3];
  52 /*0x8010*/      u32     fhc_uart_iclr;          /* FHC UART Interrupt Clear     */
  53 };
  54
  55 struct fhc_tod_regs {
  56 /*0xa000*/      u32     fhc_tod_imap;           /* FHC TOD Interrupt Map        */
  57                 u32     _pad1[3];
  58 /*0xa010*/      u32     fhc_tod_iclr;           /* FHC TOD Interrupt Clear      */
  59 };
  60
  61 /* All of the above. */
  62 struct fhc_regs {
  63         struct fhc_internal_regs        *pregs;
  64         struct fhc_ign_reg              *ireg;
  65         struct fhc_fanfail_regs         *ffregs;
  66         struct fhc_system_regs          *sregs;
  67         struct fhc_uart_regs            *uregs;
  68         struct fhc_tod_regs             *tregs;
  69 };
  70
  71 /* FHC ID Register */
  72 #define FHC_ID_VERS             0xf0000000 /* Version of this FHC               */
  73 #define FHC_ID_PARTID           0x0ffff000 /* Part ID code (0x0f9f == FHC)      */
  74 #define FHC_ID_MANUF            0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
  75 #define FHC_ID_RESV             0x00000001 /* Read as one                       */
  76
  77 /* FHC Control Register */
  78 #define FHC_CONTROL_ICS         0x00100000 /* Ignore Centerplane Signals        */
  79 #define FHC_CONTROL_FRST        0x00080000 /* Fatal Error Reset Enable          */
  80 #define FHC_CONTROL_LFAT        0x00040000 /* AC/DC signalled a local error     */
  81 #define FHC_CONTROL_SLINE       0x00010000 /* Firmware Synchronization Line     */
  82 #define FHC_CONTROL_DCD         0x00008000 /* DC-->DC Converter Disable         */
  83 #define FHC_CONTROL_POFF        0x00004000 /* AC/DC Controller PLL Disable      */
  84 #define FHC_CONTROL_FOFF        0x00002000 /* FHC Controller PLL Disable        */
  85 #define FHC_CONTROL_AOFF        0x00001000 /* CPU A SRAM/SBD Low Power Mode     */
  86 #define FHC_CONTROL_BOFF        0x00000800 /* CPU B SRAM/SBD Low Power Mode     */
  87 #define FHC_CONTROL_PSOFF       0x00000400 /* Turns off this FHC's power supply */
  88 #define FHC_CONTROL_IXIST       0x00000200 /* 0=FHC tells clock board it exists */
  89 #define FHC_CONTROL_XMSTR       0x00000100 /* 1=Causes this FHC to be XIR master*/
  90 #define FHC_CONTROL_LLED        0x00000040 /* 0=Left LED ON                     */
  91 #define FHC_CONTROL_MLED        0x00000020 /* 1=Middle LED ON                   */
  92 #define FHC_CONTROL_RLED        0x00000010 /* 1=Right LED                       */
  93 #define FHC_CONTROL_BPINS       0x00000003 /* Spare Bidirectional Pins          */
  94
  95 /* FHC Reset Control/Status Register */
  96 #define FHC_RCS_POR             0x80000000 /* Last reset was a power cycle      */
  97 #define FHC_RCS_SPOR            0x40000000 /* Last reset was sw power on reset  */
  98 #define FHC_RCS_SXIR            0x20000000 /* Last reset was sw XIR reset       */
  99 #define FHC_RCS_BPOR            0x10000000 /* Last reset was due to POR button  */
 100 #define FHC_RCS_BXIR            0x08000000 /* Last reset was due to XIR button  */
 101 #define FHC_RCS_WEVENT          0x04000000 /* CPU reset was due to wakeup event */
 102 #define FHC_RCS_CFATAL          0x02000000 /* Centerplane Fatal Error signalled */
 103 #define FHC_RCS_FENAB           0x01000000 /* Fatal errors elicit system reset  */
 104
 105 /* FHC Board Status Register */
 106 #define FHC_BSR_DA64            0x00040000 /* Port A: 0=128bit 1=64bit data path */
 107 #define FHC_BSR_DB64            0x00020000 /* Port B: 0=128bit 1=64bit data path */
 108 #define FHC_BSR_BID             0x0001e000 /* Board ID                           */
 109 #define FHC_BSR_SA              0x00001c00 /* Port A UPA Speed (from the pins)   */
 110 #define FHC_BSR_SB              0x00000380 /* Port B UPA Speed (from the pins)   */
 111 #define FHC_BSR_NDIAG           0x00000040 /* Not in Diag Mode                   */
 112 #define FHC_BSR_NTBED           0x00000020 /* Not in TestBED Mode                */
 113 #define FHC_BSR_NIA             0x0000001c /* Jumper, bit 18 in PROM space       */
 114 #define FHC_BSR_SI              0x00000001 /* Spare input pin value              */
 115
 116 /* FHC JTAG Control Register */
 117 #define FHC_JTAG_CTRL_MENAB     0x80000000 /* Indicates this is JTAG Master      */
 118 #define FHC_JTAG_CTRL_MNONE     0x40000000 /* Indicates no JTAG Master present   */
 119
 120 /* FHC then has an Interrupt Group Number register, essentially this is a 32-bit
 121  * register with the low 5 bits specifying the IGN of this FHC for interrupt
 122  * generation purposes, it is a product of the BoardID/Pins seen by the FHC
 123  * at power on time.  I suspect the firmware really sets this value though
 124  * during POST.  On board FHC devices generate fixed INO interrupt packet
 125  * values, of course these are concatenated with the IGN before it reaches the
 126  * CPU:
 127  *
 128  *      IRQ Source              INO Value
 129  *      ----------------------------------------
 130  *      "System" Interrupt      0x38
 131  *      Zilogs                  0x39
 132  *      Mostek                  0x3a
 133  *      Fan Failure             0x3b
 134  *      Spare 1                 0x3c
 135  *      Spare 2                 0x3d
 136  *
 137  * Consult the sysio.h header for the layout of the Interrupt Mapping and
 138  * Interrupt Clear register bits as they are the same. -DaveM
 139  */
 140
 141 #endif /* !(_SPARC64_FIREHOSE_H) */