src/gallium/drivers/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31 #include "tgsi/tgsi_info.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_screen.h"
  35 #include "brw_wm.h"
  36 #include "brw_state.h"
  37 #include "brw_debug.h"
  38 #include "brw_pipe_rast.h"
  39
  40
  41 /** Return number of src args for given instruction */
  42 GLuint brw_wm_nr_args( GLuint opcode )
  43 {
  44    switch (opcode) {
  45    case WM_FRONTFACING:
  46    case WM_PIXELXY:
  47       return 0;
  48    case WM_CINTERP:
  49    case WM_WPOSXY:
  50    case WM_DELTAXY:
  51       return 1;
  52    case WM_LINTERP:
  53    case WM_PIXELW:
  54       return 2;
  55    case WM_FB_WRITE:
  56    case WM_PINTERP:
  57       return 3;
  58    case TGSI_OPCODE_TEX:
  59    case TGSI_OPCODE_TXP:
  60    case TGSI_OPCODE_TXB:
  61    case TGSI_OPCODE_TXD:
  62       /* sampler arg is held as a field in the instruction, not in an
  63        * actual register:
  64        */
  65       return tgsi_get_opcode_info(opcode)->num_src - 1;
  66
  67    default:
  68       assert(opcode < MAX_OPCODE);
  69       return tgsi_get_opcode_info(opcode)->num_src;
  70    }
  71 }
  72
  73
  74 GLuint brw_wm_is_scalar_result( GLuint opcode )
  75 {
  76    switch (opcode) {
  77    case TGSI_OPCODE_COS:
  78    case TGSI_OPCODE_EX2:
  79    case TGSI_OPCODE_LG2:
  80    case TGSI_OPCODE_POW:
  81    case TGSI_OPCODE_RCP:
  82    case TGSI_OPCODE_RSQ:
  83    case TGSI_OPCODE_SIN:
  84    case TGSI_OPCODE_DP3:
  85    case TGSI_OPCODE_DP4:
  86    case TGSI_OPCODE_DPH:
  87    case TGSI_OPCODE_DST:
  88       return 1;
  89
  90    default:
  91       return 0;
  92    }
  93 }
  94
  95
  96 /**
  97  * Do GPU code generation for shaders without flow control.  Shaders
  98  * without flow control instructions can more readily be analysed for
  99  * SSA-style optimizations.
 100  */
 101 static void
 102 brw_wm_linear_shader_emit(struct brw_context *brw, struct brw_wm_compile *c)
 103 {
 104    /* Augment fragment program.  Add instructions for pre- and
 105     * post-fragment-program tasks such as interpolation and fogging.
 106     */
 107    brw_wm_pass_fp(c);
 108
 109    /* Translate to intermediate representation.  Build register usage
 110     * chains.
 111     */
 112    brw_wm_pass0(c);
 113
 114    /* Dead code removal.
 115     */
 116    brw_wm_pass1(c);
 117
 118    /* Register allocation.
 119     * Divide by two because we operate on 16 pixels at a time and require
 120     * two GRF entries for each logical shader register.
 121     */
 122    c->grf_limit = BRW_WM_MAX_GRF / 2;
 123
 124    brw_wm_pass2(c);
 125
 126    /* how many general-purpose registers are used */
 127    c->prog_data.total_grf = c->max_wm_grf;
 128
 129    /* Scratch space is used for register spilling */
 130    if (c->last_scratch) {
 131       c->prog_data.total_scratch = c->last_scratch + 0x40;
 132    }
 133    else {
 134       c->prog_data.total_scratch = 0;
 135    }
 136
 137    /* Emit GEN4 code.
 138     */
 139    brw_wm_emit(c);
 140 }
 141
 142
 143 /**
 144  * All Mesa program -> GPU code generation goes through this function.
 145  * Depending on the instructions used (i.e. flow control instructions)
 146  * we'll use one of two code generators.
 147  */
 148 static enum pipe_error do_wm_prog( struct brw_context *brw,
 149                                    struct brw_fragment_shader *fp,
 150                                    struct brw_wm_prog_key *key,
 151                                    struct brw_winsys_buffer **bo_out)
 152 {
 153    enum pipe_error ret;
 154    struct brw_wm_compile *c;
 155    const GLuint *program;
 156    GLuint program_size;
 157
 158    if (brw->wm.compile_data == NULL) {
 159       brw->wm.compile_data = MALLOC(sizeof(*brw->wm.compile_data));
 160       if (!brw->wm.compile_data)
 161          return PIPE_ERROR_OUT_OF_MEMORY;
 162    }
 163
 164    c = brw->wm.compile_data;
 165    memset(c, 0, sizeof *c);
 166
 167    c->key = *key;
 168    c->fp = fp;
 169    c->env_param = NULL; /*brw->intel.ctx.FragmentProgram.Parameters;*/
 170
 171    brw_init_compile(brw, &c->func);
 172
 173    /*
 174     * Shader which use GLSL features such as flow control are handled
 175     * differently from "simple" shaders.
 176     */
 177    if (fp->has_flow_control) {
 178       c->dispatch_width = 8;
 179       /* XXX: GLSL support
 180        */
 181       exit(1);
 182       /* brw_wm_branching_shader_emit(brw, c); */
 183    }
 184    else {
 185       c->dispatch_width = 16;
 186       brw_wm_linear_shader_emit(brw, c);
 187    }
 188
 189    if (BRW_DEBUG & DEBUG_WM)
 190       debug_printf("\n");
 191
 192    /* get the program
 193     */
 194    ret = brw_get_program(&c->func, &program, &program_size);
 195    if (ret)
 196       return ret;
 197
 198    ret = brw_upload_cache( &brw->cache, BRW_WM_PROG,
 199                            &c->key, sizeof(c->key),
 200                            NULL, 0,
 201                            program, program_size,
 202                            &c->prog_data,
 203                            &brw->wm.prog_data,
 204                            bo_out );
 205    if (ret)
 206       return ret;
 207
 208    return PIPE_OK;
 209 }
 210
 211
 212
 213 static void brw_wm_populate_key( struct brw_context *brw,
 214                                  struct brw_wm_prog_key *key )
 215 {
 216    unsigned lookup, line_aa;
 217    unsigned i;
 218
 219    memset(key, 0, sizeof(*key));
 220
 221    /* PIPE_NEW_FRAGMENT_SHADER
 222     * PIPE_NEW_DEPTH_STENCIL_ALPHA
 223     */
 224    lookup = (brw->curr.zstencil->iz_lookup |
 225              brw->curr.fragment_shader->iz_lookup);
 226
 227
 228    /* PIPE_NEW_RAST
 229     * BRW_NEW_REDUCED_PRIMITIVE
 230     */
 231    switch (brw->reduced_primitive) {
 232    case PIPE_PRIM_POINTS:
 233       line_aa = AA_NEVER;
 234       break;
 235    case PIPE_PRIM_LINES:
 236       line_aa = (brw->curr.rast->templ.line_smooth ?
 237                  AA_ALWAYS : AA_NEVER);
 238       break;
 239    default:
 240       line_aa = brw->curr.rast->unfilled_aa_line;
 241       break;
 242    }
 243
 244    brw_wm_lookup_iz(line_aa,
 245                     lookup,
 246                     brw->curr.fragment_shader->uses_depth,
 247                     key);
 248
 249    /* PIPE_NEW_RAST */
 250    key->flat_shade = brw->curr.rast->templ.flatshade;
 251
 252
 253    /* PIPE_NEW_BOUND_TEXTURES */
 254    for (i = 0; i < brw->curr.num_fragment_sampler_views; i++) {
 255       const struct brw_texture *tex = brw_texture(brw->curr.fragment_sampler_views[i]->texture);
 256
 257       if (tex->base.format == PIPE_FORMAT_UYVY)
 258          key->yuvtex_mask |= 1 << i;
 259
 260       if (tex->base.format == PIPE_FORMAT_YUYV)
 261          key->yuvtex_swap_mask |= 1 << i;
 262
 263       /* XXX: shadow texture
 264        */
 265       /* key->shadowtex_mask |= 1<<i; */
 266    }
 267
 268    /* CACHE_NEW_VS_PROG */
 269    key->vp_nr_outputs = brw->vs.prog_data->nr_outputs;
 270
 271    key->nr_cbufs = brw->curr.fb.nr_cbufs;
 272
 273    key->nr_inputs = brw->curr.fragment_shader->info.num_inputs;
 274
 275    /* The unique fragment program ID */
 276    key->program_string_id = brw->curr.fragment_shader->id;
 277 }
 278
 279
 280 static enum pipe_error brw_prepare_wm_prog(struct brw_context *brw)
 281 {
 282    struct brw_wm_prog_key key;
 283    struct brw_fragment_shader *fs = brw->curr.fragment_shader;
 284    enum pipe_error ret;
 285
 286    brw_wm_populate_key(brw, &key);
 287
 288    /* Make an early check for the key.
 289     */
 290    if (brw_search_cache(&brw->cache, BRW_WM_PROG,
 291                         &key, sizeof(key),
 292                         NULL, 0,
 293                         &brw->wm.prog_data,
 294                         &brw->wm.prog_bo))
 295       return PIPE_OK;
 296
 297    ret = do_wm_prog(brw, fs, &key, &brw->wm.prog_bo);
 298    if (ret)
 299       return ret;
 300
 301    return PIPE_OK;
 302 }
 303
 304
 305 const struct brw_tracked_state brw_wm_prog = {
 306    .dirty = {
 307       .mesa  = (PIPE_NEW_FRAGMENT_SHADER |
 308                 PIPE_NEW_DEPTH_STENCIL_ALPHA |
 309                 PIPE_NEW_RAST |
 310                 PIPE_NEW_NR_CBUFS |
 311                 PIPE_NEW_BOUND_TEXTURES),
 312       .brw   = (BRW_NEW_WM_INPUT_DIMENSIONS |
 313                 BRW_NEW_REDUCED_PRIMITIVE),
 314       .cache = CACHE_NEW_VS_PROG,
 315    },
 316    .prepare = brw_prepare_wm_prog
 317 };
 318