gallium: add target-helpers/wrap_screen.c to C_SOURCES
[mesa/mesa-lb.git] / src / gallium / drivers / i965 / brw_wm_state.c
blobee970ac75bcd0a53a019e6aa2e7b8e5a880d8281
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "util/u_math.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "brw_wm.h"
38 #include "brw_debug.h"
39 #include "brw_pipe_rast.h"
41 /***********************************************************************
42 * WM unit - fragment programs and rasterization
45 struct brw_wm_unit_key {
46 unsigned int total_grf, total_scratch;
47 unsigned int urb_entry_read_length;
48 unsigned int curb_entry_read_length;
49 unsigned int dispatch_grf_start_reg;
51 unsigned int curbe_offset;
52 unsigned int urb_size;
54 unsigned int max_threads;
56 unsigned int nr_surfaces, sampler_count;
57 GLboolean uses_depth, computes_depth, uses_kill, has_flow_control;
58 GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
59 GLfloat offset_units, offset_factor;
62 static void
63 wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
65 const struct brw_fragment_shader *fp = brw->curr.fragment_shader;
67 memset(key, 0, sizeof(*key));
69 if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
70 key->max_threads = 1;
71 else {
72 /* WM maximum threads is number of EUs times number of threads per EU. */
73 if (BRW_IS_IGDNG(brw))
74 key->max_threads = 12 * 6;
75 else if (BRW_IS_G4X(brw))
76 key->max_threads = 10 * 5;
77 else
78 key->max_threads = 8 * 4;
81 /* CACHE_NEW_WM_PROG */
82 key->total_grf = brw->wm.prog_data->total_grf;
83 key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
84 key->curb_entry_read_length = brw->wm.prog_data->curb_read_length;
85 key->dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
86 key->total_scratch = align(brw->wm.prog_data->total_scratch, 1024);
88 /* BRW_NEW_URB_FENCE */
89 key->urb_size = brw->urb.vsize;
91 /* BRW_NEW_CURBE_OFFSETS */
92 key->curbe_offset = brw->curbe.wm_start;
94 /* BRW_NEW_NR_SURFACEs */
95 key->nr_surfaces = brw->wm.nr_surfaces;
97 /* CACHE_NEW_SAMPLER */
98 key->sampler_count = brw->wm.sampler_count;
100 /* PIPE_NEW_RAST */
101 key->polygon_stipple = brw->curr.rast->templ.poly_stipple_enable;
103 /* PIPE_NEW_FRAGMENT_PROGRAM */
104 key->uses_depth = fp->uses_depth;
105 key->computes_depth = fp->info.writes_z;
107 /* PIPE_NEW_DEPTH_BUFFER
109 * Override for NULL depthbuffer case, required by the Pixel Shader Computed
110 * Depth field.
112 if (brw->curr.fb.zsbuf == NULL)
113 key->computes_depth = 0;
115 /* PIPE_NEW_DEPTH_STENCIL_ALPHA */
116 key->uses_kill = (fp->info.uses_kill ||
117 brw->curr.zstencil->cc3.alpha_test);
119 key->has_flow_control = fp->has_flow_control;
121 /* temporary sanity check assertion */
122 assert(fp->has_flow_control == 0);
124 /* PIPE_NEW_QUERY */
125 key->stats_wm = (brw->query.stats_wm != 0);
127 /* PIPE_NEW_RAST */
128 key->line_stipple = brw->curr.rast->templ.line_stipple_enable;
131 key->offset_enable = (brw->curr.rast->templ.offset_cw ||
132 brw->curr.rast->templ.offset_ccw);
134 key->offset_units = brw->curr.rast->templ.offset_units;
135 key->offset_factor = brw->curr.rast->templ.offset_scale;
139 * Setup wm hardware state. See page 225 of Volume 2
141 static enum pipe_error
142 wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
143 struct brw_winsys_reloc *reloc,
144 unsigned nr_reloc,
145 struct brw_winsys_buffer **bo_out)
147 struct brw_wm_unit_state wm;
148 enum pipe_error ret;
150 memset(&wm, 0, sizeof(wm));
152 wm.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
153 wm.thread0.kernel_start_pointer = 0; /* reloc */
154 wm.thread1.depth_coef_urb_read_offset = 1;
155 wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
157 if (BRW_IS_IGDNG(brw))
158 wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
159 else
160 wm.thread1.binding_table_entry_count = key->nr_surfaces;
162 if (key->total_scratch != 0) {
163 wm.thread2.scratch_space_base_pointer = 0; /* reloc */
164 wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1;
165 } else {
166 wm.thread2.scratch_space_base_pointer = 0;
167 wm.thread2.per_thread_scratch_space = 0;
170 wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg;
171 wm.thread3.urb_entry_read_length = key->urb_entry_read_length;
172 wm.thread3.urb_entry_read_offset = 0;
173 wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
174 wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
176 if (BRW_IS_IGDNG(brw))
177 wm.wm4.sampler_count = 0; /* hardware requirement */
178 else
179 wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
181 /* reloc */
182 wm.wm4.sampler_state_pointer = 0;
184 wm.wm5.program_uses_depth = key->uses_depth;
185 wm.wm5.program_computes_depth = key->computes_depth;
186 wm.wm5.program_uses_killpixel = key->uses_kill;
188 if (key->has_flow_control)
189 wm.wm5.enable_8_pix = 1;
190 else
191 wm.wm5.enable_16_pix = 1;
193 wm.wm5.max_threads = key->max_threads - 1;
194 wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */
195 wm.wm5.legacy_line_rast = 0;
196 wm.wm5.legacy_global_depth_bias = 0;
197 wm.wm5.early_depth_test = 1; /* never need to disable */
198 wm.wm5.line_aa_region_width = 0;
199 wm.wm5.line_endcap_aa_region_width = 1;
201 wm.wm5.polygon_stipple = key->polygon_stipple;
203 if (key->offset_enable) {
204 wm.wm5.depth_offset = 1;
205 /* Something wierd going on with legacy_global_depth_bias,
206 * offset_constant, scaling and MRD. This value passes glean
207 * but gives some odd results elsewere (eg. the
208 * quad-offset-units test).
210 wm.global_depth_offset_constant = key->offset_units * 2;
212 /* This is the only value that passes glean:
214 wm.global_depth_offset_scale = key->offset_factor;
217 wm.wm5.line_stipple = key->line_stipple;
219 if ((BRW_DEBUG & DEBUG_STATS) || key->stats_wm)
220 wm.wm4.stats_enable = 1;
222 ret = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
223 key, sizeof(*key),
224 reloc, nr_reloc,
225 &wm, sizeof(wm),
226 NULL, NULL,
227 bo_out);
228 if (ret)
229 return ret;
231 return PIPE_OK;
235 static enum pipe_error upload_wm_unit( struct brw_context *brw )
237 struct brw_wm_unit_key key;
238 struct brw_winsys_reloc reloc[3];
239 unsigned nr_reloc = 0;
240 enum pipe_error ret;
241 unsigned grf_reg_count;
242 unsigned per_thread_scratch_space;
243 unsigned stats_enable;
244 unsigned sampler_count;
246 wm_unit_populate_key(brw, &key);
249 /* Allocate the necessary scratch space if we haven't already. Don't
250 * bother reducing the allocation later, since we use scratch so
251 * rarely.
253 assert(key.total_scratch <= 12 * 1024);
254 if (key.total_scratch) {
255 GLuint total = key.total_scratch * key.max_threads;
257 /* Do we need a new buffer:
259 if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size)
260 bo_reference(&brw->wm.scratch_bo, NULL);
262 if (brw->wm.scratch_bo == NULL) {
263 ret = brw->sws->bo_alloc(brw->sws,
264 BRW_BUFFER_TYPE_SHADER_SCRATCH,
265 total,
266 4096,
267 &brw->wm.scratch_bo);
268 if (ret)
269 return ret;
274 /* XXX: temporary:
276 grf_reg_count = (align(key.total_grf, 16) / 16 - 1);
277 per_thread_scratch_space = key.total_scratch / 1024 - 1;
278 stats_enable = (BRW_DEBUG & DEBUG_STATS) || key.stats_wm;
279 sampler_count = BRW_IS_IGDNG(brw) ? 0 :(key.sampler_count + 1) / 4;
281 /* Emit WM program relocation */
282 make_reloc(&reloc[nr_reloc++],
283 BRW_USAGE_STATE,
284 grf_reg_count << 1,
285 offsetof(struct brw_wm_unit_state, thread0),
286 brw->wm.prog_bo);
288 /* Emit scratch space relocation */
289 if (key.total_scratch != 0) {
290 make_reloc(&reloc[nr_reloc++],
291 BRW_USAGE_SCRATCH,
292 per_thread_scratch_space,
293 offsetof(struct brw_wm_unit_state, thread2),
294 brw->wm.scratch_bo);
297 /* Emit sampler state relocation */
298 if (key.sampler_count != 0) {
299 make_reloc(&reloc[nr_reloc++],
300 BRW_USAGE_STATE,
301 stats_enable | (sampler_count << 2),
302 offsetof(struct brw_wm_unit_state, wm4),
303 brw->wm.sampler_bo);
307 if (brw_search_cache(&brw->cache, BRW_WM_UNIT,
308 &key, sizeof(key),
309 reloc, nr_reloc,
310 NULL,
311 &brw->wm.state_bo))
312 return PIPE_OK;
314 ret = wm_unit_create_from_key(brw, &key,
315 reloc, nr_reloc,
316 &brw->wm.state_bo);
317 if (ret)
318 return ret;
320 return PIPE_OK;
323 const struct brw_tracked_state brw_wm_unit = {
324 .dirty = {
325 .mesa = (PIPE_NEW_FRAGMENT_SHADER |
326 PIPE_NEW_DEPTH_BUFFER |
327 PIPE_NEW_RAST |
328 PIPE_NEW_DEPTH_STENCIL_ALPHA |
329 PIPE_NEW_QUERY),
331 .brw = (BRW_NEW_CURBE_OFFSETS |
332 BRW_NEW_NR_WM_SURFACES),
334 .cache = (CACHE_NEW_WM_PROG |
335 CACHE_NEW_SAMPLER)
337 .prepare = upload_wm_unit,