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gallium: add target-helpers/wrap_screen.c to C_SOURCES
[mesa/mesa-lb.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
blob2d243be16a35ff1ce245f0b0917292b2af308c4b
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_dump.h"
9 #include "tgsi/tgsi_util.h"
10
11 #include "nvfx_context.h"
12 #include "nvfx_state.h"
13
14 /* TODO (at least...):
15 * 1. Indexed consts + ARL
16 * 3. NV_vp11, NV_vp2, NV_vp3 features
17 * - extra arith opcodes
18 * - branching
19 * - texture sampling
20 * - indexed attribs
21 * - indexed results
22 * 4. bugs
23 */
24
25 #include "nv30_vertprog.h"
26 #include "nv40_vertprog.h"
27
28 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
29
30 struct nvfx_vpc {
31 struct nvfx_vertex_program *vp;
32
33 struct nvfx_vertex_program_exec *vpi;
34
35 unsigned r_temps;
36 unsigned r_temps_discard;
37 struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
38 struct nvfx_sreg *r_address;
39 struct nvfx_sreg *r_temp;
40
41 struct nvfx_sreg *imm;
42 unsigned nr_imm;
43
44 unsigned hpos_idx;
45 };
46
47 static struct nvfx_sreg
48 temp(struct nvfx_vpc *vpc)
49 {
50 int idx = ffs(~vpc->r_temps) - 1;
51
52 if (idx < 0) {
53 NOUVEAU_ERR("out of temps!!\n");
54 assert(0);
55 return nvfx_sr(NVFXSR_TEMP, 0);
56 }
57
58 vpc->r_temps |= (1 << idx);
59 vpc->r_temps_discard |= (1 << idx);
60 return nvfx_sr(NVFXSR_TEMP, idx);
61 }
62
63 static INLINE void
64 release_temps(struct nvfx_vpc *vpc)
65 {
66 vpc->r_temps &= ~vpc->r_temps_discard;
67 vpc->r_temps_discard = 0;
68 }
69
70 static struct nvfx_sreg
71 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
72 {
73 struct nvfx_vertex_program *vp = vpc->vp;
74 struct nvfx_vertex_program_data *vpd;
75 int idx;
76
77 if (pipe >= 0) {
78 for (idx = 0; idx < vp->nr_consts; idx++) {
79 if (vp->consts[idx].index == pipe)
80 return nvfx_sr(NVFXSR_CONST, idx);
81 }
82 }
83
84 idx = vp->nr_consts++;
85 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
86 vpd = &vp->consts[idx];
87
88 vpd->index = pipe;
89 vpd->value[0] = x;
90 vpd->value[1] = y;
91 vpd->value[2] = z;
92 vpd->value[3] = w;
93 return nvfx_sr(NVFXSR_CONST, idx);
94 }
95
96 #define arith(cc,s,o,d,m,s0,s1,s2) \
97 nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
98
99 static void
100 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
101 {
102 struct nvfx_vertex_program *vp = vpc->vp;
103 uint32_t sr = 0;
104
105 switch (src.type) {
106 case NVFXSR_TEMP:
107 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
108 sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
109 break;
110 case NVFXSR_INPUT:
111 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
112 NVFX_VP(SRC_REG_TYPE_SHIFT));
113 vp->ir |= (1 << src.index);
114 hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
115 break;
116 case NVFXSR_CONST:
117 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
118 NVFX_VP(SRC_REG_TYPE_SHIFT));
119 assert(vpc->vpi->const_index == -1 ||
120 vpc->vpi->const_index == src.index);
121 vpc->vpi->const_index = src.index;
122 break;
123 case NVFXSR_NONE:
124 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
125 NVFX_VP(SRC_REG_TYPE_SHIFT));
126 break;
127 default:
128 assert(0);
129 }
130
131 if (src.negate)
132 sr |= NVFX_VP(SRC_NEGATE);
133
134 if (src.abs)
135 hw[0] |= (1 << (21 + pos));
136
137 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
138 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
139 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
140 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
141
142 switch (pos) {
143 case 0:
144 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
145 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
146 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
147 NVFX_VP(INST_SRC0L_SHIFT);
148 break;
149 case 1:
150 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
151 break;
152 case 2:
153 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
154 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
155 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
156 NVFX_VP(INST_SRC2L_SHIFT);
157 break;
158 default:
159 assert(0);
160 }
161 }
162
163 static void
164 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
165 {
166 struct nvfx_vertex_program *vp = vpc->vp;
167
168 switch (dst.type) {
169 case NVFXSR_TEMP:
170 if(!nvfx->is_nv4x)
171 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
172 else {
173 hw[3] |= NV40_VP_INST_DEST_MASK;
174 if (slot == 0) {
175 hw[0] |= (dst.index <<
176 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
177 } else {
178 hw[3] |= (dst.index <<
179 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
180 }
181 }
182 break;
183 case NVFXSR_OUTPUT:
184 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
185 switch (dst.index) {
186 case NVFX_VP_INST_DEST_CLIP(0):
187 vp->or |= (1 << 6);
188 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
189 dst.index = NVFX_VP(INST_DEST_FOGC);
190 break;
191 case NVFX_VP_INST_DEST_CLIP(1):
192 vp->or |= (1 << 7);
193 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
194 dst.index = NVFX_VP(INST_DEST_FOGC);
195 break;
196 case NVFX_VP_INST_DEST_CLIP(2):
197 vp->or |= (1 << 8);
198 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
199 dst.index = NVFX_VP(INST_DEST_FOGC);
200 break;
201 case NVFX_VP_INST_DEST_CLIP(3):
202 vp->or |= (1 << 9);
203 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
204 dst.index = NVFX_VP(INST_DEST_PSZ);
205 break;
206 case NVFX_VP_INST_DEST_CLIP(4):
207 vp->or |= (1 << 10);
208 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
209 dst.index = NVFX_VP(INST_DEST_PSZ);
210 break;
211 case NVFX_VP_INST_DEST_CLIP(5):
212 vp->or |= (1 << 11);
213 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
214 dst.index = NVFX_VP(INST_DEST_PSZ);
215 break;
216 default:
217 if(!nvfx->is_nv4x) {
218 switch (dst.index) {
219 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
220 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
221 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
222 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
223 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
224 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
225 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
226 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
227 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
228 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
229 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
230 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
231 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
232 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
233 }
234 } else {
235 switch (dst.index) {
236 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
237 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
238 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
239 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
240 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
241 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
242 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
243 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
244 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
245 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
246 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
247 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
248 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
249 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
250 }
251 }
252 break;
253 }
254
255 if(!nvfx->is_nv4x) {
256 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
257 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
258
259 /*XXX: no way this is entirely correct, someone needs to
260 * figure out what exactly it is.
261 */
262 hw[3] |= 0x800;
263 } else {
264 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
265 if (slot == 0) {
266 hw[0] |= NV40_VP_INST_VEC_RESULT;
267 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
268 } else {
269 hw[3] |= NV40_VP_INST_SCA_RESULT;
270 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
271 }
272 }
273 break;
274 default:
275 assert(0);
276 }
277 }
278
279 static void
280 nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
281 struct nvfx_sreg dst, int mask,
282 struct nvfx_sreg s0, struct nvfx_sreg s1,
283 struct nvfx_sreg s2)
284 {
285 struct nvfx_vertex_program *vp = vpc->vp;
286 uint32_t *hw;
287
288 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
289 vpc->vpi = &vp->insns[vp->nr_insns - 1];
290 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
291 vpc->vpi->const_index = -1;
292
293 hw = vpc->vpi->data;
294
295 hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
296 hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
297 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
298 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
299 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
300
301 if(!nvfx->is_nv4x) {
302 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
303 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
304 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
305
306 if (dst.type == NVFXSR_OUTPUT) {
307 if (slot)
308 hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
309 else
310 hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
311 } else {
312 if (slot)
313 hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
314 else
315 hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
316 }
317 } else {
318 if (slot == 0) {
319 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
320 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
321 hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
322 } else {
323 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
324 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
325 hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
326 }
327 }
328
329 emit_dst(nvfx, vpc, hw, slot, dst);
330 emit_src(nvfx, vpc, hw, 0, s0);
331 emit_src(nvfx, vpc, hw, 1, s1);
332 emit_src(nvfx, vpc, hw, 2, s2);
333 }
334
335 static INLINE struct nvfx_sreg
336 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
337 struct nvfx_sreg src;
338
339 switch (fsrc->Register.File) {
340 case TGSI_FILE_INPUT:
341 src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
342 break;
343 case TGSI_FILE_CONSTANT:
344 src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
345 break;
346 case TGSI_FILE_IMMEDIATE:
347 src = vpc->imm[fsrc->Register.Index];
348 break;
349 case TGSI_FILE_TEMPORARY:
350 src = vpc->r_temp[fsrc->Register.Index];
351 break;
352 default:
353 NOUVEAU_ERR("bad src file\n");
354 break;
355 }
356
357 src.abs = fsrc->Register.Absolute;
358 src.negate = fsrc->Register.Negate;
359 src.swz[0] = fsrc->Register.SwizzleX;
360 src.swz[1] = fsrc->Register.SwizzleY;
361 src.swz[2] = fsrc->Register.SwizzleZ;
362 src.swz[3] = fsrc->Register.SwizzleW;
363 return src;
364 }
365
366 static INLINE struct nvfx_sreg
367 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
368 struct nvfx_sreg dst;
369
370 switch (fdst->Register.File) {
371 case TGSI_FILE_OUTPUT:
372 dst = vpc->r_result[fdst->Register.Index];
373 break;
374 case TGSI_FILE_TEMPORARY:
375 dst = vpc->r_temp[fdst->Register.Index];
376 break;
377 case TGSI_FILE_ADDRESS:
378 dst = vpc->r_address[fdst->Register.Index];
379 break;
380 default:
381 NOUVEAU_ERR("bad dst file\n");
382 break;
383 }
384
385 return dst;
386 }
387
388 static INLINE int
389 tgsi_mask(uint tgsi)
390 {
391 int mask = 0;
392
393 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
394 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
395 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
396 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
397 return mask;
398 }
399
400 static boolean
401 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
402 const struct tgsi_full_instruction *finst)
403 {
404 struct nvfx_sreg src[3], dst, tmp;
405 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
406 int mask;
407 int ai = -1, ci = -1, ii = -1;
408 int i;
409
410 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
411 return TRUE;
412
413 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
414 const struct tgsi_full_src_register *fsrc;
415
416 fsrc = &finst->Src[i];
417 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
418 src[i] = tgsi_src(vpc, fsrc);
419 }
420 }
421
422 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
423 const struct tgsi_full_src_register *fsrc;
424
425 fsrc = &finst->Src[i];
426
427 switch (fsrc->Register.File) {
428 case TGSI_FILE_INPUT:
429 if (ai == -1 || ai == fsrc->Register.Index) {
430 ai = fsrc->Register.Index;
431 src[i] = tgsi_src(vpc, fsrc);
432 } else {
433 src[i] = temp(vpc);
434 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
435 tgsi_src(vpc, fsrc), none, none);
436 }
437 break;
438 case TGSI_FILE_CONSTANT:
439 if ((ci == -1 && ii == -1) ||
440 ci == fsrc->Register.Index) {
441 ci = fsrc->Register.Index;
442 src[i] = tgsi_src(vpc, fsrc);
443 } else {
444 src[i] = temp(vpc);
445 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
446 tgsi_src(vpc, fsrc), none, none);
447 }
448 break;
449 case TGSI_FILE_IMMEDIATE:
450 if ((ci == -1 && ii == -1) ||
451 ii == fsrc->Register.Index) {
452 ii = fsrc->Register.Index;
453 src[i] = tgsi_src(vpc, fsrc);
454 } else {
455 src[i] = temp(vpc);
456 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
457 tgsi_src(vpc, fsrc), none, none);
458 }
459 break;
460 case TGSI_FILE_TEMPORARY:
461 /* handled above */
462 break;
463 default:
464 NOUVEAU_ERR("bad src file\n");
465 return FALSE;
466 }
467 }
468
469 dst = tgsi_dst(vpc, &finst->Dst[0]);
470 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
471
472 switch (finst->Instruction.Opcode) {
473 case TGSI_OPCODE_ABS:
474 arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
475 break;
476 case TGSI_OPCODE_ADD:
477 arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
478 break;
479 case TGSI_OPCODE_ARL:
480 arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
481 break;
482 case TGSI_OPCODE_DP3:
483 arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
484 break;
485 case TGSI_OPCODE_DP4:
486 arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
487 break;
488 case TGSI_OPCODE_DPH:
489 arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
490 break;
491 case TGSI_OPCODE_DST:
492 arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
493 break;
494 case TGSI_OPCODE_EX2:
495 arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
496 break;
497 case TGSI_OPCODE_EXP:
498 arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
499 break;
500 case TGSI_OPCODE_FLR:
501 arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
502 break;
503 case TGSI_OPCODE_FRC:
504 arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
505 break;
506 case TGSI_OPCODE_LG2:
507 arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
508 break;
509 case TGSI_OPCODE_LIT:
510 arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
511 break;
512 case TGSI_OPCODE_LOG:
513 arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
514 break;
515 case TGSI_OPCODE_MAD:
516 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
517 break;
518 case TGSI_OPCODE_MAX:
519 arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
520 break;
521 case TGSI_OPCODE_MIN:
522 arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
523 break;
524 case TGSI_OPCODE_MOV:
525 arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
526 break;
527 case TGSI_OPCODE_MUL:
528 arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
529 break;
530 case TGSI_OPCODE_POW:
531 tmp = temp(vpc);
532 arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
533 swz(src[0], X, X, X, X));
534 arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
535 swz(src[1], X, X, X, X), none);
536 arith(vpc, SCA, EX2, dst, mask, none, none,
537 swz(tmp, X, X, X, X));
538 break;
539 case TGSI_OPCODE_RCP:
540 arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
541 break;
542 case TGSI_OPCODE_RET:
543 break;
544 case TGSI_OPCODE_RSQ:
545 arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
546 break;
547 case TGSI_OPCODE_SGE:
548 arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
549 break;
550 case TGSI_OPCODE_SGT:
551 arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
552 break;
553 case TGSI_OPCODE_SLT:
554 arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
555 break;
556 case TGSI_OPCODE_SUB:
557 arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
558 break;
559 case TGSI_OPCODE_XPD:
560 tmp = temp(vpc);
561 arith(vpc, VEC, MUL, tmp, mask,
562 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
563 arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
564 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
565 neg(tmp));
566 break;
567 default:
568 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
569 return FALSE;
570 }
571
572 release_temps(vpc);
573 return TRUE;
574 }
575
576 static boolean
577 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
578 const struct tgsi_full_declaration *fdec)
579 {
580 unsigned idx = fdec->Range.First;
581 int hw;
582
583 switch (fdec->Semantic.Name) {
584 case TGSI_SEMANTIC_POSITION:
585 hw = NVFX_VP(INST_DEST_POS);
586 vpc->hpos_idx = idx;
587 break;
588 case TGSI_SEMANTIC_COLOR:
589 if (fdec->Semantic.Index == 0) {
590 hw = NVFX_VP(INST_DEST_COL0);
591 } else
592 if (fdec->Semantic.Index == 1) {
593 hw = NVFX_VP(INST_DEST_COL1);
594 } else {
595 NOUVEAU_ERR("bad colour semantic index\n");
596 return FALSE;
597 }
598 break;
599 case TGSI_SEMANTIC_BCOLOR:
600 if (fdec->Semantic.Index == 0) {
601 hw = NVFX_VP(INST_DEST_BFC0);
602 } else
603 if (fdec->Semantic.Index == 1) {
604 hw = NVFX_VP(INST_DEST_BFC1);
605 } else {
606 NOUVEAU_ERR("bad bcolour semantic index\n");
607 return FALSE;
608 }
609 break;
610 case TGSI_SEMANTIC_FOG:
611 hw = NVFX_VP(INST_DEST_FOGC);
612 break;
613 case TGSI_SEMANTIC_PSIZE:
614 hw = NVFX_VP(INST_DEST_PSZ);
615 break;
616 case TGSI_SEMANTIC_GENERIC:
617 if (fdec->Semantic.Index <= 7) {
618 hw = NVFX_VP(INST_DEST_TC(fdec->Semantic.Index));
619 } else {
620 NOUVEAU_ERR("bad generic semantic index\n");
621 return FALSE;
622 }
623 break;
624 case TGSI_SEMANTIC_EDGEFLAG:
625 /* not really an error just a fallback */
626 NOUVEAU_ERR("cannot handle edgeflag output\n");
627 return FALSE;
628 default:
629 NOUVEAU_ERR("bad output semantic\n");
630 return FALSE;
631 }
632
633 vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
634 return TRUE;
635 }
636
637 static boolean
638 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
639 {
640 struct tgsi_parse_context p;
641 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
642
643 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
644 while (!tgsi_parse_end_of_tokens(&p)) {
645 const union tgsi_full_token *tok = &p.FullToken;
646
647 tgsi_parse_token(&p);
648 switch(tok->Token.Type) {
649 case TGSI_TOKEN_TYPE_IMMEDIATE:
650 nr_imm++;
651 break;
652 case TGSI_TOKEN_TYPE_DECLARATION:
653 {
654 const struct tgsi_full_declaration *fdec;
655
656 fdec = &p.FullToken.FullDeclaration;
657 switch (fdec->Declaration.File) {
658 case TGSI_FILE_TEMPORARY:
659 if (fdec->Range.Last > high_temp) {
660 high_temp =
661 fdec->Range.Last;
662 }
663 break;
664 #if 0 /* this would be nice.. except gallium doesn't track it */
665 case TGSI_FILE_ADDRESS:
666 if (fdec->Range.Last > high_addr) {
667 high_addr =
668 fdec->Range.Last;
669 }
670 break;
671 #endif
672 case TGSI_FILE_OUTPUT:
673 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
674 return FALSE;
675 break;
676 default:
677 break;
678 }
679 }
680 break;
681 #if 1 /* yay, parse instructions looking for address regs instead */
682 case TGSI_TOKEN_TYPE_INSTRUCTION:
683 {
684 const struct tgsi_full_instruction *finst;
685 const struct tgsi_full_dst_register *fdst;
686
687 finst = &p.FullToken.FullInstruction;
688 fdst = &finst->Dst[0];
689
690 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
691 if (fdst->Register.Index > high_addr)
692 high_addr = fdst->Register.Index;
693 }
694
695 }
696 break;
697 #endif
698 default:
699 break;
700 }
701 }
702 tgsi_parse_free(&p);
703
704 if (nr_imm) {
705 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
706 assert(vpc->imm);
707 }
708
709 if (++high_temp) {
710 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
711 for (i = 0; i < high_temp; i++)
712 vpc->r_temp[i] = temp(vpc);
713 }
714
715 if (++high_addr) {
716 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
717 for (i = 0; i < high_addr; i++)
718 vpc->r_address[i] = temp(vpc);
719 }
720
721 vpc->r_temps_discard = 0;
722 return TRUE;
723 }
724
725 static void
726 nvfx_vertprog_translate(struct nvfx_context *nvfx,
727 struct nvfx_vertex_program *vp)
728 {
729 struct tgsi_parse_context parse;
730 struct nvfx_vpc *vpc = NULL;
731 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
732 int i;
733
734 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
735 if (!vpc)
736 return;
737 vpc->vp = vp;
738
739 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
740 FREE(vpc);
741 return;
742 }
743
744 /* Redirect post-transform vertex position to a temp if user clip
745 * planes are enabled. We need to append code to the vtxprog
746 * to handle clip planes later.
747 */
748 if (vp->ucp.nr) {
749 vpc->r_result[vpc->hpos_idx] = temp(vpc);
750 vpc->r_temps_discard = 0;
751 }
752
753 tgsi_parse_init(&parse, vp->pipe.tokens);
754
755 while (!tgsi_parse_end_of_tokens(&parse)) {
756 tgsi_parse_token(&parse);
757
758 switch (parse.FullToken.Token.Type) {
759 case TGSI_TOKEN_TYPE_IMMEDIATE:
760 {
761 const struct tgsi_full_immediate *imm;
762
763 imm = &parse.FullToken.FullImmediate;
764 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
765 assert(imm->Immediate.NrTokens == 4 + 1);
766 vpc->imm[vpc->nr_imm++] =
767 constant(vpc, -1,
768 imm->u[0].Float,
769 imm->u[1].Float,
770 imm->u[2].Float,
771 imm->u[3].Float);
772 }
773 break;
774 case TGSI_TOKEN_TYPE_INSTRUCTION:
775 {
776 const struct tgsi_full_instruction *finst;
777 finst = &parse.FullToken.FullInstruction;
778 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
779 goto out_err;
780 }
781 break;
782 default:
783 break;
784 }
785 }
786
787 /* Write out HPOS if it was redirected to a temp earlier */
788 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
789 struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
790 NVFX_VP(INST_DEST_POS));
791 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
792
793 arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
794 }
795
796 /* Insert code to handle user clip planes */
797 for (i = 0; i < vp->ucp.nr; i++) {
798 struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
799 NVFX_VP_INST_DEST_CLIP(i));
800 struct nvfx_sreg ceqn = constant(vpc, -1,
801 nvfx->clip.ucp[i][0],
802 nvfx->clip.ucp[i][1],
803 nvfx->clip.ucp[i][2],
804 nvfx->clip.ucp[i][3]);
805 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
806 unsigned mask;
807
808 switch (i) {
809 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
810 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
811 case 2: case 5: mask = NVFX_VP_MASK_W; break;
812 default:
813 NOUVEAU_ERR("invalid clip dist #%d\n", i);
814 goto out_err;
815 }
816
817 arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
818 }
819
820 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
821 vp->translated = TRUE;
822 out_err:
823 tgsi_parse_free(&parse);
824 if (vpc->r_temp)
825 FREE(vpc->r_temp);
826 if (vpc->r_address)
827 FREE(vpc->r_address);
828 if (vpc->imm)
829 FREE(vpc->imm);
830 FREE(vpc);
831 }
832
833 static boolean
834 nvfx_vertprog_validate(struct nvfx_context *nvfx)
835 {
836 struct pipe_screen *pscreen = nvfx->pipe.screen;
837 struct nvfx_screen *screen = nvfx->screen;
838 struct nouveau_channel *chan = screen->base.channel;
839 struct nouveau_grobj *eng3d = screen->eng3d;
840 struct nvfx_vertex_program *vp;
841 struct pipe_buffer *constbuf;
842 boolean upload_code = FALSE, upload_data = FALSE;
843 int i;
844
845 if (nvfx->render_mode == HW) {
846 vp = nvfx->vertprog;
847 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
848
849 if ((nvfx->dirty & NVFX_NEW_UCP) ||
850 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
851 nvfx_vertprog_destroy(nvfx, vp);
852 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
853 }
854 } else {
855 vp = nvfx->swtnl.vertprog;
856 constbuf = NULL;
857 }
858
859 /* Translate TGSI shader into hw bytecode */
860 if (vp->translated)
861 goto check_gpu_resources;
862
863 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
864 nvfx_vertprog_translate(nvfx, vp);
865 if (!vp->translated) {
866 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
867 return FALSE;
868 }
869
870 check_gpu_resources:
871 /* Allocate hw vtxprog exec slots */
872 if (!vp->exec) {
873 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
874 struct nouveau_stateobj *so;
875 uint vplen = vp->nr_insns;
876
877 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
878 while (heap->next && heap->size < vplen) {
879 struct nvfx_vertex_program *evict;
880
881 evict = heap->next->priv;
882 nouveau_resource_free(&evict->exec);
883 }
884
885 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
886 assert(0);
887 }
888
889 so = so_new(3, 4, 0);
890 so_method(so, eng3d, NV34TCL_VP_START_FROM_ID, 1);
891 so_data (so, vp->exec->start);
892 if(nvfx->is_nv4x) {
893 so_method(so, eng3d, NV40TCL_VP_ATTRIB_EN, 2);
894 so_data (so, vp->ir);
895 so_data (so, vp->or);
896 }
897 so_method(so, eng3d, NV34TCL_VP_CLIP_PLANES_ENABLE, 1);
898 so_data (so, vp->clip_ctrl);
899 so_ref(so, &vp->so);
900 so_ref(NULL, &so);
901
902 upload_code = TRUE;
903 }
904
905 /* Allocate hw vtxprog const slots */
906 if (vp->nr_consts && !vp->data) {
907 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
908
909 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
910 while (heap->next && heap->size < vp->nr_consts) {
911 struct nvfx_vertex_program *evict;
912
913 evict = heap->next->priv;
914 nouveau_resource_free(&evict->data);
915 }
916
917 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
918 assert(0);
919 }
920
921 /*XXX: handle this some day */
922 assert(vp->data->start >= vp->data_start_min);
923
924 upload_data = TRUE;
925 if (vp->data_start != vp->data->start)
926 upload_code = TRUE;
927 }
928
929 /* If exec or data segments moved we need to patch the program to
930 * fixup offsets and register IDs.
931 */
932 if (vp->exec_start != vp->exec->start) {
933 for (i = 0; i < vp->nr_insns; i++) {
934 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
935
936 if (vpi->has_branch_offset) {
937 assert(0);
938 }
939 }
940
941 vp->exec_start = vp->exec->start;
942 }
943
944 if (vp->nr_consts && vp->data_start != vp->data->start) {
945 for (i = 0; i < vp->nr_insns; i++) {
946 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
947
948 if (vpi->const_index >= 0) {
949 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
950 vpi->data[1] |=
951 (vpi->const_index + vp->data->start) <<
952 NVFX_VP(INST_CONST_SRC_SHIFT);
953
954 }
955 }
956
957 vp->data_start = vp->data->start;
958 }
959
960 /* Update + Upload constant values */
961 if (vp->nr_consts) {
962 float *map = NULL;
963
964 if (constbuf) {
965 map = pipe_buffer_map(pscreen, constbuf,
966 PIPE_BUFFER_USAGE_CPU_READ);
967 }
968
969 for (i = 0; i < vp->nr_consts; i++) {
970 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
971
972 if (vpd->index >= 0) {
973 if (!upload_data &&
974 !memcmp(vpd->value, &map[vpd->index * 4],
975 4 * sizeof(float)))
976 continue;
977 memcpy(vpd->value, &map[vpd->index * 4],
978 4 * sizeof(float));
979 }
980
981 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
982 OUT_RING (chan, i + vp->data->start);
983 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
984 }
985
986 if (constbuf)
987 pipe_buffer_unmap(pscreen, constbuf);
988 }
989
990 /* Upload vtxprog */
991 if (upload_code) {
992 #if 0
993 for (i = 0; i < vp->nr_insns; i++) {
994 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
995 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
996 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
997 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
998 }
999 #endif
1000 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1001 OUT_RING (chan, vp->exec->start);
1002 for (i = 0; i < vp->nr_insns; i++) {
1003 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1004 OUT_RINGp (chan, vp->insns[i].data, 4);
1005 }
1006 }
1007
1008 if (vp->so != nvfx->state.hw[NVFX_STATE_VERTPROG]) {
1009 so_ref(vp->so, &nvfx->state.hw[NVFX_STATE_VERTPROG]);
1010 return TRUE;
1011 }
1012
1013 return FALSE;
1014 }
1015
1016 void
1017 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1018 {
1019 vp->translated = FALSE;
1020
1021 if (vp->nr_insns) {
1022 FREE(vp->insns);
1023 vp->insns = NULL;
1024 vp->nr_insns = 0;
1025 }
1026
1027 if (vp->nr_consts) {
1028 FREE(vp->consts);
1029 vp->consts = NULL;
1030 vp->nr_consts = 0;
1031 }
1032
1033 nouveau_resource_free(&vp->exec);
1034 vp->exec_start = 0;
1035 nouveau_resource_free(&vp->data);
1036 vp->data_start = 0;
1037 vp->data_start_min = 0;
1038
1039 vp->ir = vp->or = vp->clip_ctrl = 0;
1040 so_ref(NULL, &vp->so);
1041 }
1042
1043 struct nvfx_state_entry nvfx_state_vertprog = {
1044 .validate = nvfx_vertprog_validate,
1045 .dirty = {
1046 .pipe = NVFX_NEW_VERTPROG | NVFX_NEW_UCP,
1047 .hw = NVFX_STATE_VERTPROG,
1048 }
1049 };
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