?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
r600g: fix color format, indentation, defines
[mesa/nouveau-pmpeg.git] / src / gallium / drivers / r600 / r600_state.c
blobdeb9bf3395a50b57fd544203f66e48bbef792b5e
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void *r600_create_blend_state(struct pipe_context *ctx,
38 const struct pipe_blend_state *state)
39 {
40 struct r600_context *rctx = r600_context(ctx);
41
42 return r600_context_state(rctx, pipe_blend_type, state);
43 }
44
45 static void *r600_create_dsa_state(struct pipe_context *ctx,
46 const struct pipe_depth_stencil_alpha_state *state)
47 {
48 struct r600_context *rctx = r600_context(ctx);
49
50 return r600_context_state(rctx, pipe_dsa_type, state);
51 }
52
53 static void *r600_create_rs_state(struct pipe_context *ctx,
54 const struct pipe_rasterizer_state *state)
55 {
56 struct r600_context *rctx = r600_context(ctx);
57
58 return r600_context_state(rctx, pipe_rasterizer_type, state);
59 }
60
61 static void *r600_create_sampler_state(struct pipe_context *ctx,
62 const struct pipe_sampler_state *state)
63 {
64 struct r600_context *rctx = r600_context(ctx);
65
66 return r600_context_state(rctx, pipe_sampler_type, state);
67 }
68
69 static void r600_sampler_view_destroy(struct pipe_context *ctx,
70 struct pipe_sampler_view *state)
71 {
72 struct r600_context_state *rstate = (struct r600_context_state *)state;
73
74 r600_context_state_decref(rstate);
75 }
76
77 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
78 struct pipe_resource *texture,
79 const struct pipe_sampler_view *state)
80 {
81 struct r600_context *rctx = r600_context(ctx);
82 struct r600_context_state *rstate;
83
84 rstate = r600_context_state(rctx, pipe_sampler_type, state);
85 pipe_reference(NULL, &texture->reference);
86 rstate->state.sampler_view.texture = texture;
87 rstate->state.sampler_view.reference.count = 1;
88 rstate->state.sampler_view.context = ctx;
89 return &rstate->state.sampler_view;
90 }
91
92 static void *r600_create_shader_state(struct pipe_context *ctx,
93 const struct pipe_shader_state *state)
94 {
95 struct r600_context *rctx = r600_context(ctx);
96
97 return r600_context_state(rctx, pipe_shader_type, state);
98 }
99
100 static void *r600_create_vertex_elements(struct pipe_context *ctx,
101 unsigned count,
102 const struct pipe_vertex_element *elements)
103 {
104 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
105
106 assert(count < 32);
107 v->count = count;
108 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
109 v->refcount = 1;
110 return v;
111 }
112
113 static void r600_bind_state(struct pipe_context *ctx, void *state)
114 {
115 struct r600_context *rctx = r600_context(ctx);
116 struct r600_context_state *rstate = (struct r600_context_state *)state;
117
118 if (state == NULL)
119 return;
120 switch (rstate->type) {
121 case pipe_rasterizer_type:
122 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
123 rctx->rasterizer = r600_context_state_incref(rstate);
124 break;
125 case pipe_poly_stipple_type:
126 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
127 rctx->poly_stipple = r600_context_state_incref(rstate);
128 break;
129 case pipe_scissor_type:
130 rctx->scissor = r600_context_state_decref(rctx->scissor);
131 rctx->scissor = r600_context_state_incref(rstate);
132 break;
133 case pipe_clip_type:
134 rctx->clip = r600_context_state_decref(rctx->clip);
135 rctx->clip = r600_context_state_incref(rstate);
136 break;
137 case pipe_depth_type:
138 rctx->depth = r600_context_state_decref(rctx->depth);
139 rctx->depth = r600_context_state_incref(rstate);
140 break;
141 case pipe_stencil_type:
142 rctx->stencil = r600_context_state_decref(rctx->stencil);
143 rctx->stencil = r600_context_state_incref(rstate);
144 break;
145 case pipe_alpha_type:
146 rctx->alpha = r600_context_state_decref(rctx->alpha);
147 rctx->alpha = r600_context_state_incref(rstate);
148 break;
149 case pipe_dsa_type:
150 rctx->dsa = r600_context_state_decref(rctx->dsa);
151 rctx->dsa = r600_context_state_incref(rstate);
152 break;
153 case pipe_blend_type:
154 rctx->blend = r600_context_state_decref(rctx->blend);
155 rctx->blend = r600_context_state_incref(rstate);
156 break;
157 case pipe_framebuffer_type:
158 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
159 rctx->framebuffer = r600_context_state_incref(rstate);
160 break;
161 case pipe_stencil_ref_type:
162 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
163 rctx->stencil_ref = r600_context_state_incref(rstate);
164 break;
165 case pipe_viewport_type:
166 rctx->viewport = r600_context_state_decref(rctx->viewport);
167 rctx->viewport = r600_context_state_incref(rstate);
168 break;
169 case pipe_shader_type:
170 case pipe_sampler_type:
171 case pipe_sampler_view_type:
172 default:
173 R600_ERR("invalid type %d\n", rstate->type);
174 return;
175 }
176 }
177
178 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
179 {
180 struct r600_context *rctx = r600_context(ctx);
181 struct r600_context_state *rstate = (struct r600_context_state *)state;
182
183 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
184 rctx->ps_shader = r600_context_state_incref(rstate);
185 }
186
187 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
188 {
189 struct r600_context *rctx = r600_context(ctx);
190 struct r600_context_state *rstate = (struct r600_context_state *)state;
191
192 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
193 rctx->vs_shader = r600_context_state_incref(rstate);
194 }
195
196 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
197 {
198 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
199
200 if (v == NULL)
201 return;
202 if (--v->refcount)
203 return;
204 free(v);
205 }
206
207 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
208 {
209 struct r600_context *rctx = r600_context(ctx);
210 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
211
212 r600_delete_vertex_element(ctx, rctx->vertex_elements);
213 rctx->vertex_elements = v;
214 if (v) {
215 v->refcount++;
216 }
217 }
218
219 static void r600_bind_ps_sampler(struct pipe_context *ctx,
220 unsigned count, void **states)
221 {
222 struct r600_context *rctx = r600_context(ctx);
223 struct r600_context_state *rstate;
224 unsigned i;
225
226 for (i = 0; i < rctx->ps_nsampler; i++) {
227 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
228 }
229 for (i = 0; i < count; i++) {
230 rstate = (struct r600_context_state *)states[i];
231 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
232 }
233 rctx->ps_nsampler = count;
234 }
235
236 static void r600_bind_vs_sampler(struct pipe_context *ctx,
237 unsigned count, void **states)
238 {
239 struct r600_context *rctx = r600_context(ctx);
240 struct r600_context_state *rstate;
241 unsigned i;
242
243 for (i = 0; i < rctx->vs_nsampler; i++) {
244 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
245 }
246 for (i = 0; i < count; i++) {
247 rstate = (struct r600_context_state *)states[i];
248 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
249 }
250 rctx->vs_nsampler = count;
251 }
252
253 static void r600_delete_state(struct pipe_context *ctx, void *state)
254 {
255 struct r600_context_state *rstate = (struct r600_context_state *)state;
256
257 r600_context_state_decref(rstate);
258 }
259
260 static void r600_set_blend_color(struct pipe_context *ctx,
261 const struct pipe_blend_color *color)
262 {
263 struct r600_context *rctx = r600_context(ctx);
264
265 rctx->blend_color = *color;
266 }
267
268 static void r600_set_clip_state(struct pipe_context *ctx,
269 const struct pipe_clip_state *state)
270 {
271 }
272
273 static void r600_set_constant_buffer(struct pipe_context *ctx,
274 uint shader, uint index,
275 struct pipe_resource *buffer)
276 {
277 struct r600_screen *rscreen = r600_screen(ctx->screen);
278 struct r600_context *rctx = r600_context(ctx);
279 unsigned nconstant = 0, i, type, id;
280 struct radeon_state *rstate;
281 struct pipe_transfer *transfer;
282 u32 *ptr;
283
284 switch (shader) {
285 case PIPE_SHADER_VERTEX:
286 id = R600_VS_CONSTANT;
287 type = R600_VS_CONSTANT_TYPE;
288 break;
289 case PIPE_SHADER_FRAGMENT:
290 id = R600_PS_CONSTANT;
291 type = R600_PS_CONSTANT_TYPE;
292 break;
293 default:
294 R600_ERR("unsupported %d\n", shader);
295 return;
296 }
297 if (buffer && buffer->width0 > 0) {
298 nconstant = buffer->width0 / 16;
299 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
300 if (ptr == NULL)
301 return;
302 for (i = 0; i < nconstant; i++) {
303 rstate = radeon_state(rscreen->rw, type, id + i);
304 if (rstate == NULL)
305 return;
306 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
307 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
308 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
309 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
310 if (radeon_state_pm4(rstate))
311 return;
312 if (radeon_draw_set_new(rctx->draw, rstate))
313 return;
314 }
315 pipe_buffer_unmap(ctx, buffer, transfer);
316 }
317 }
318
319 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
320 unsigned count,
321 struct pipe_sampler_view **views)
322 {
323 struct r600_context *rctx = r600_context(ctx);
324 struct r600_context_state *rstate;
325 unsigned i;
326
327 for (i = 0; i < rctx->ps_nsampler_view; i++) {
328 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
329 }
330 for (i = 0; i < count; i++) {
331 rstate = (struct r600_context_state *)views[i];
332 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
333 }
334 rctx->ps_nsampler_view = count;
335 }
336
337 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
338 unsigned count,
339 struct pipe_sampler_view **views)
340 {
341 struct r600_context *rctx = r600_context(ctx);
342 struct r600_context_state *rstate;
343 unsigned i;
344
345 for (i = 0; i < rctx->vs_nsampler_view; i++) {
346 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
347 }
348 for (i = 0; i < count; i++) {
349 rstate = (struct r600_context_state *)views[i];
350 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
351 }
352 rctx->vs_nsampler_view = count;
353 }
354
355 static void r600_set_framebuffer_state(struct pipe_context *ctx,
356 const struct pipe_framebuffer_state *state)
357 {
358 struct r600_context *rctx = r600_context(ctx);
359 struct r600_context_state *rstate;
360
361 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
362 r600_bind_state(ctx, rstate);
363 }
364
365 static void r600_set_polygon_stipple(struct pipe_context *ctx,
366 const struct pipe_poly_stipple *state)
367 {
368 }
369
370 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
371 {
372 }
373
374 static void r600_set_scissor_state(struct pipe_context *ctx,
375 const struct pipe_scissor_state *state)
376 {
377 struct r600_context *rctx = r600_context(ctx);
378 struct r600_context_state *rstate;
379
380 rstate = r600_context_state(rctx, pipe_scissor_type, state);
381 r600_bind_state(ctx, rstate);
382 }
383
384 static void r600_set_stencil_ref(struct pipe_context *ctx,
385 const struct pipe_stencil_ref *state)
386 {
387 struct r600_context *rctx = r600_context(ctx);
388 struct r600_context_state *rstate;
389
390 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
391 r600_bind_state(ctx, rstate);
392 }
393
394 static void r600_set_vertex_buffers(struct pipe_context *ctx,
395 unsigned count,
396 const struct pipe_vertex_buffer *buffers)
397 {
398 struct r600_context *rctx = r600_context(ctx);
399 unsigned i;
400
401 for (i = 0; i < rctx->nvertex_buffer; i++) {
402 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
403 }
404 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
405 for (i = 0; i < count; i++) {
406 rctx->vertex_buffer[i].buffer = NULL;
407 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
408 }
409 rctx->nvertex_buffer = count;
410 }
411
412 static void r600_set_index_buffer(struct pipe_context *ctx,
413 const struct pipe_index_buffer *ib)
414 {
415 struct r600_context *rctx = r600_context(ctx);
416
417 if (ib) {
418 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
419 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
420 } else {
421 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
422 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
423 }
424
425 /* TODO make this more like a state */
426 }
427
428 static void r600_set_viewport_state(struct pipe_context *ctx,
429 const struct pipe_viewport_state *state)
430 {
431 struct r600_context *rctx = r600_context(ctx);
432 struct r600_context_state *rstate;
433
434 rstate = r600_context_state(rctx, pipe_viewport_type, state);
435 r600_bind_state(ctx, rstate);
436 }
437
438 void r600_init_state_functions(struct r600_context *rctx)
439 {
440 rctx->context.create_blend_state = r600_create_blend_state;
441 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
442 rctx->context.create_fs_state = r600_create_shader_state;
443 rctx->context.create_rasterizer_state = r600_create_rs_state;
444 rctx->context.create_sampler_state = r600_create_sampler_state;
445 rctx->context.create_sampler_view = r600_create_sampler_view;
446 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
447 rctx->context.create_vs_state = r600_create_shader_state;
448 rctx->context.bind_blend_state = r600_bind_state;
449 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
450 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
451 rctx->context.bind_fs_state = r600_bind_ps_shader;
452 rctx->context.bind_rasterizer_state = r600_bind_state;
453 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
454 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
455 rctx->context.bind_vs_state = r600_bind_vs_shader;
456 rctx->context.delete_blend_state = r600_delete_state;
457 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
458 rctx->context.delete_fs_state = r600_delete_state;
459 rctx->context.delete_rasterizer_state = r600_delete_state;
460 rctx->context.delete_sampler_state = r600_delete_state;
461 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
462 rctx->context.delete_vs_state = r600_delete_state;
463 rctx->context.set_blend_color = r600_set_blend_color;
464 rctx->context.set_clip_state = r600_set_clip_state;
465 rctx->context.set_constant_buffer = r600_set_constant_buffer;
466 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
467 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
468 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
469 rctx->context.set_sample_mask = r600_set_sample_mask;
470 rctx->context.set_scissor_state = r600_set_scissor_state;
471 rctx->context.set_stencil_ref = r600_set_stencil_ref;
472 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
473 rctx->context.set_index_buffer = r600_set_index_buffer;
474 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
475 rctx->context.set_viewport_state = r600_set_viewport_state;
476 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
477 }
478
479 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
480 {
481 if (rstate == NULL)
482 return NULL;
483 rstate->refcount++;
484 return rstate;
485 }
486
487 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
488 {
489 unsigned i;
490
491 if (rstate == NULL)
492 return NULL;
493 if (--rstate->refcount)
494 return NULL;
495 switch (rstate->type) {
496 case pipe_sampler_view_type:
497 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
498 break;
499 case pipe_framebuffer_type:
500 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
501 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
502 }
503 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
504 break;
505 case pipe_viewport_type:
506 case pipe_depth_type:
507 case pipe_rasterizer_type:
508 case pipe_poly_stipple_type:
509 case pipe_scissor_type:
510 case pipe_clip_type:
511 case pipe_stencil_type:
512 case pipe_alpha_type:
513 case pipe_dsa_type:
514 case pipe_blend_type:
515 case pipe_stencil_ref_type:
516 case pipe_shader_type:
517 case pipe_sampler_type:
518 break;
519 default:
520 R600_ERR("invalid type %d\n", rstate->type);
521 return NULL;
522 }
523 radeon_state_decref(rstate->rstate);
524 FREE(rstate);
525 return NULL;
526 }
527
528 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
529 {
530 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
531 const union pipe_states *states = state;
532 unsigned i;
533 int r;
534
535 if (rstate == NULL)
536 return NULL;
537 rstate->type = type;
538 rstate->refcount = 1;
539
540 switch (rstate->type) {
541 case pipe_sampler_view_type:
542 rstate->state.sampler_view = (*states).sampler_view;
543 rstate->state.sampler_view.texture = NULL;
544 break;
545 case pipe_framebuffer_type:
546 rstate->state.framebuffer = (*states).framebuffer;
547 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
548 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
549 (*states).framebuffer.cbufs[i]);
550 }
551 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
552 (*states).framebuffer.zsbuf);
553 break;
554 case pipe_viewport_type:
555 rstate->state.viewport = (*states).viewport;
556 break;
557 case pipe_depth_type:
558 rstate->state.depth = (*states).depth;
559 break;
560 case pipe_rasterizer_type:
561 rstate->state.rasterizer = (*states).rasterizer;
562 break;
563 case pipe_poly_stipple_type:
564 rstate->state.poly_stipple = (*states).poly_stipple;
565 break;
566 case pipe_scissor_type:
567 rstate->state.scissor = (*states).scissor;
568 break;
569 case pipe_clip_type:
570 rstate->state.clip = (*states).clip;
571 break;
572 case pipe_stencil_type:
573 rstate->state.stencil = (*states).stencil;
574 break;
575 case pipe_alpha_type:
576 rstate->state.alpha = (*states).alpha;
577 break;
578 case pipe_dsa_type:
579 rstate->state.dsa = (*states).dsa;
580 break;
581 case pipe_blend_type:
582 rstate->state.blend = (*states).blend;
583 break;
584 case pipe_stencil_ref_type:
585 rstate->state.stencil_ref = (*states).stencil_ref;
586 break;
587 case pipe_shader_type:
588 rstate->state.shader = (*states).shader;
589 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
590 if (r) {
591 r600_context_state_decref(rstate);
592 return NULL;
593 }
594 break;
595 case pipe_sampler_type:
596 rstate->state.sampler = (*states).sampler;
597 break;
598 default:
599 R600_ERR("invalid type %d\n", rstate->type);
600 FREE(rstate);
601 return NULL;
602 }
603 return rstate;
604 }
605
606 static struct radeon_state *r600_blend(struct r600_context *rctx)
607 {
608 struct r600_screen *rscreen = rctx->screen;
609 struct radeon_state *rstate;
610 const struct pipe_blend_state *state = &rctx->blend->state.blend;
611 int i;
612
613 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
614 if (rstate == NULL)
615 return NULL;
616 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
617 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
618 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
619 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
620 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
621 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
622 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
623 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
624 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
625 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
626 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
627 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
628 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
629
630 for (i = 0; i < 8; i++) {
631 unsigned eqRGB = state->rt[i].rgb_func;
632 unsigned srcRGB = state->rt[i].rgb_src_factor;
633 unsigned dstRGB = state->rt[i].rgb_dst_factor;
634
635 unsigned eqA = state->rt[i].alpha_func;
636 unsigned srcA = state->rt[i].alpha_src_factor;
637 unsigned dstA = state->rt[i].alpha_dst_factor;
638 uint32_t bc = 0;
639
640 if (!state->rt[i].blend_enable)
641 continue;
642
643 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
644 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
645 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
646
647 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
648 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
649 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
650 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
651 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
652 }
653
654 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
655 if (i == 0)
656 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
657 }
658
659 if (radeon_state_pm4(rstate)) {
660 radeon_state_decref(rstate);
661 return NULL;
662 }
663 return rstate;
664 }
665
666 static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
667 {
668 struct r600_screen *rscreen = rctx->screen;
669 struct r600_resource_texture *rtex;
670 struct r600_resource *rbuffer;
671 struct radeon_state *rstate;
672 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
673 unsigned level = state->cbufs[cb]->level;
674 unsigned pitch, slice;
675 unsigned color_info;
676 unsigned format, swap, ntype;
677 const struct util_format_description *desc;
678 int id = R600_CB0 + cb;
679
680 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, id);
681 if (rstate == NULL)
682 return NULL;
683 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
684 rbuffer = &rtex->resource;
685 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
686 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
687 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
688 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
689 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
690 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
691 rstate->nbo = 3;
692 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
693 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
694
695 ntype = 0;
696 desc = util_format_description(rtex->resource.base.b.format);
697 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
698 ntype = V_0280A0_NUMBER_SRGB;
699
700 format = r600_translate_colorformat(rtex->resource.base.b.format);
701 swap = r600_translate_colorswap(rtex->resource.base.b.format);
702
703 color_info = S_0280A0_FORMAT(format) |
704 S_0280A0_COMP_SWAP(swap) |
705 S_0280A0_BLEND_CLAMP(1) |
706 S_0280A0_SOURCE_FORMAT(1) |
707 S_0280A0_NUMBER_TYPE(ntype);
708
709 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
710 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
711 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
712 S_028060_SLICE_TILE_MAX(slice);
713 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
714 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
715 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
716 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
717 if (radeon_state_pm4(rstate)) {
718 radeon_state_decref(rstate);
719 return NULL;
720 }
721 return rstate;
722 }
723
724 static struct radeon_state *r600_db(struct r600_context *rctx)
725 {
726 struct r600_screen *rscreen = rctx->screen;
727 struct r600_resource_texture *rtex;
728 struct r600_resource *rbuffer;
729 struct radeon_state *rstate;
730 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
731 unsigned level = state->cbufs[0]->level;
732 unsigned pitch, slice, format;
733
734 if (state->zsbuf == NULL)
735 return NULL;
736
737 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
738 if (rstate == NULL)
739 return NULL;
740
741 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
742 rbuffer = &rtex->resource;
743 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
744 rstate->nbo = 1;
745 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
746 level = state->zsbuf->level;
747 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
748 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
749 format = r600_translate_dbformat(state->zsbuf->texture->format);
750 rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
751 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
752 S_028010_FORMAT(format);
753 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
754 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
755 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
756 S_028000_SLICE_TILE_MAX(slice);
757 if (radeon_state_pm4(rstate)) {
758 radeon_state_decref(rstate);
759 return NULL;
760 }
761 return rstate;
762 }
763
764 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
765 {
766 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
767 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
768 struct r600_screen *rscreen = rctx->screen;
769 struct radeon_state *rstate;
770 float offset_units = 0, offset_scale = 0;
771 char depth = 0;
772 unsigned offset_db_fmt_cntl = 0;
773
774 if (fb->zsbuf) {
775 offset_units = state->offset_units;
776 offset_scale = state->offset_scale * 12.0f;
777 switch (fb->zsbuf->texture->format) {
778 case PIPE_FORMAT_Z24X8_UNORM:
779 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
780 depth = -24;
781 offset_units *= 2.0f;
782 break;
783 case PIPE_FORMAT_Z32_FLOAT:
784 depth = -23;
785 offset_units *= 1.0f;
786 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
787 break;
788 case PIPE_FORMAT_Z16_UNORM:
789 depth = -16;
790 offset_units *= 4.0f;
791 break;
792 default:
793 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
794 return NULL;
795 }
796 }
797 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
798
799 rctx->flat_shade = state->flatshade;
800 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
801 if (rstate == NULL)
802 return NULL;
803 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
804 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
805 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
806 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
807 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
808 S_028814_FACE(!state->front_ccw) |
809 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
810 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
811 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
812 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
813 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
814 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
815 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
816 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
817 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
818 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
819 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
820 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
821 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
822 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
823 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
824 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
825 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
826 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
827 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
828 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
829 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
830 if (radeon_state_pm4(rstate)) {
831 radeon_state_decref(rstate);
832 return NULL;
833 }
834 return rstate;
835 }
836
837 static struct radeon_state *r600_scissor(struct r600_context *rctx)
838 {
839 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
840 struct r600_screen *rscreen = rctx->screen;
841 struct radeon_state *rstate;
842 u32 tl, br;
843
844 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
845 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
846 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
847 if (rstate == NULL)
848 return NULL;
849 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
850 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
851 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
852 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
853 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
854 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
855 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
856 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
857 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
858 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
859 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
860 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
861 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
862 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
863 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
864 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
865 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
866 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
867 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
868 if (radeon_state_pm4(rstate)) {
869 radeon_state_decref(rstate);
870 return NULL;
871 }
872 return rstate;
873 }
874
875 static struct radeon_state *r600_viewport(struct r600_context *rctx)
876 {
877 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
878 struct r600_screen *rscreen = rctx->screen;
879 struct radeon_state *rstate;
880
881 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
882 if (rstate == NULL)
883 return NULL;
884 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
885 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
886 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
887 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
888 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
889 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
890 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
891 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
892 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
893 if (radeon_state_pm4(rstate)) {
894 radeon_state_decref(rstate);
895 return NULL;
896 }
897 return rstate;
898 }
899
900 static struct radeon_state *r600_dsa(struct r600_context *rctx)
901 {
902 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
903 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
904 struct r600_screen *rscreen = rctx->screen;
905 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
906 unsigned stencil_ref_mask, stencil_ref_mask_bf;
907 struct r600_shader *rshader = &rctx->ps_shader->shader;
908 struct radeon_state *rstate;
909 int i;
910
911 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
912 if (rstate == NULL)
913 return NULL;
914
915 db_shader_control = 0x210;
916 for (i = 0; i < rshader->noutput; i++) {
917 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
918 db_shader_control |= 1;
919 }
920 stencil_ref_mask = 0;
921 stencil_ref_mask_bf = 0;
922 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
923 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
924 S_028800_ZFUNC(state->depth.func);
925 /* set stencil enable */
926
927 if (state->stencil[0].enabled) {
928 db_depth_control |= S_028800_STENCIL_ENABLE(1);
929 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
930 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
931 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
932 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
933
934 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
935 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
936 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
937 if (state->stencil[1].enabled) {
938 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
939 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
940 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
941 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
942 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
943 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
944 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
945 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
946 }
947 }
948
949 alpha_test_control = 0;
950 alpha_ref = 0;
951 if (state->alpha.enabled) {
952 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
953 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
954 alpha_ref = fui(state->alpha.ref_value);
955 }
956
957 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
958 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
959 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
960 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
961 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
962 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
963 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
964 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
965 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
966 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
967 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
968 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
969 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
970 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
971 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
972 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
973 if (radeon_state_pm4(rstate)) {
974 radeon_state_decref(rstate);
975 return NULL;
976 }
977 return rstate;
978 }
979
980 static inline unsigned r600_tex_wrap(unsigned wrap)
981 {
982 switch (wrap) {
983 default:
984 case PIPE_TEX_WRAP_REPEAT:
985 return V_03C000_SQ_TEX_WRAP;
986 case PIPE_TEX_WRAP_CLAMP:
987 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
988 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
989 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
990 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
991 return V_03C000_SQ_TEX_CLAMP_BORDER;
992 case PIPE_TEX_WRAP_MIRROR_REPEAT:
993 return V_03C000_SQ_TEX_MIRROR;
994 case PIPE_TEX_WRAP_MIRROR_CLAMP:
995 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
996 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
997 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
998 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
999 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1000 }
1001 }
1002
1003 static inline unsigned r600_tex_filter(unsigned filter)
1004 {
1005 switch (filter) {
1006 default:
1007 case PIPE_TEX_FILTER_NEAREST:
1008 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1009 case PIPE_TEX_FILTER_LINEAR:
1010 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1011 }
1012 }
1013
1014 static inline unsigned r600_tex_mipfilter(unsigned filter)
1015 {
1016 switch (filter) {
1017 case PIPE_TEX_MIPFILTER_NEAREST:
1018 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1019 case PIPE_TEX_MIPFILTER_LINEAR:
1020 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1021 default:
1022 case PIPE_TEX_MIPFILTER_NONE:
1023 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1024 }
1025 }
1026
1027 static inline unsigned r600_tex_compare(unsigned compare)
1028 {
1029 switch (compare) {
1030 default:
1031 case PIPE_FUNC_NEVER:
1032 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1033 case PIPE_FUNC_LESS:
1034 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1035 case PIPE_FUNC_EQUAL:
1036 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1037 case PIPE_FUNC_LEQUAL:
1038 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1039 case PIPE_FUNC_GREATER:
1040 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1041 case PIPE_FUNC_NOTEQUAL:
1042 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1043 case PIPE_FUNC_GEQUAL:
1044 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1045 case PIPE_FUNC_ALWAYS:
1046 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1047 }
1048 }
1049
1050 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1051 {
1052 return value * (1 << frac_bits);
1053 }
1054
1055 static struct radeon_state *r600_sampler(struct r600_context *rctx,
1056 const struct pipe_sampler_state *state,
1057 unsigned id)
1058 {
1059 struct r600_screen *rscreen = rctx->screen;
1060 struct radeon_state *rstate;
1061
1062 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
1063 if (rstate == NULL)
1064 return NULL;
1065 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1066 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1067 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1068 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1069 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1070 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1071 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1072 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1073 /* FIXME LOD it depends on texture base level ... */
1074 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1075 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1076 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1077 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1078 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1079 if (radeon_state_pm4(rstate)) {
1080 radeon_state_decref(rstate);
1081 return NULL;
1082 }
1083 return rstate;
1084 }
1085
1086 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1087 {
1088 switch (swizzle) {
1089 case PIPE_SWIZZLE_RED:
1090 return V_038010_SQ_SEL_X;
1091 case PIPE_SWIZZLE_GREEN:
1092 return V_038010_SQ_SEL_Y;
1093 case PIPE_SWIZZLE_BLUE:
1094 return V_038010_SQ_SEL_Z;
1095 case PIPE_SWIZZLE_ALPHA:
1096 return V_038010_SQ_SEL_W;
1097 case PIPE_SWIZZLE_ZERO:
1098 return V_038010_SQ_SEL_0;
1099 default:
1100 case PIPE_SWIZZLE_ONE:
1101 return V_038010_SQ_SEL_1;
1102 }
1103 }
1104
1105 static inline unsigned r600_format_type(unsigned format_type)
1106 {
1107 switch (format_type) {
1108 default:
1109 case UTIL_FORMAT_TYPE_UNSIGNED:
1110 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1111 case UTIL_FORMAT_TYPE_SIGNED:
1112 return V_038010_SQ_FORMAT_COMP_SIGNED;
1113 case UTIL_FORMAT_TYPE_FIXED:
1114 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1115 }
1116 }
1117
1118 static inline unsigned r600_tex_dim(unsigned dim)
1119 {
1120 switch (dim) {
1121 default:
1122 case PIPE_TEXTURE_1D:
1123 return V_038000_SQ_TEX_DIM_1D;
1124 case PIPE_TEXTURE_2D:
1125 return V_038000_SQ_TEX_DIM_2D;
1126 case PIPE_TEXTURE_3D:
1127 return V_038000_SQ_TEX_DIM_3D;
1128 case PIPE_TEXTURE_CUBE:
1129 return V_038000_SQ_TEX_DIM_CUBEMAP;
1130 }
1131 }
1132
1133 static struct radeon_state *r600_resource(struct r600_context *rctx,
1134 const struct pipe_sampler_view *view,
1135 unsigned id)
1136 {
1137 struct r600_screen *rscreen = rctx->screen;
1138 const struct util_format_description *desc;
1139 struct r600_resource_texture *tmp;
1140 struct r600_resource *rbuffer;
1141 struct radeon_state *rstate;
1142 unsigned format;
1143
1144 format = r600_translate_colorformat(view->texture->format);
1145 if (format == ~0)
1146 return NULL;
1147 desc = util_format_description(view->texture->format);
1148 if (desc == NULL) {
1149 R600_ERR("unknow format %d\n", view->texture->format);
1150 return NULL;
1151 }
1152 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
1153 if (rstate == NULL) {
1154 return NULL;
1155 }
1156 tmp = (struct r600_resource_texture*)view->texture;
1157 rbuffer = &tmp->resource;
1158 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1159 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1160 rstate->nbo = 2;
1161 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1162 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1163 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1164 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1165
1166 /* FIXME properly handle first level != 0 */
1167 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1168 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1169 S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
1170 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1171 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1172 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1173 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1174 S_038004_DATA_FORMAT(format);
1175 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
1176 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1177 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1178 S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1179 S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1180 S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1181 S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1182 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1183 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1184 S_038010_REQUEST_SIZE(1) |
1185 S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
1186 S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
1187 S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
1188 S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
1189 S_038010_FORCE_DEGAMMA(desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB ? 1 : 0) |
1190 S_038010_BASE_LEVEL(view->first_level);
1191 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1192 S_038014_LAST_LEVEL(view->last_level) |
1193 S_038014_BASE_ARRAY(0) |
1194 S_038014_LAST_ARRAY(0);
1195 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1196 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1197 if (radeon_state_pm4(rstate)) {
1198 radeon_state_decref(rstate);
1199 return NULL;
1200 }
1201 return rstate;
1202 }
1203
1204 static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
1205 {
1206 struct r600_screen *rscreen = rctx->screen;
1207 struct radeon_state *rstate;
1208 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1209 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1210 uint32_t color_control, target_mask, shader_mask;
1211 int i;
1212
1213 target_mask = 0;
1214 shader_mask = 0;
1215 color_control = S_028808_PER_MRT_BLEND(1);
1216
1217 for (i = 0; i < nr_cbufs; i++) {
1218 shader_mask |= 0xf << i;
1219 }
1220
1221 if (pbs->logicop_enable) {
1222 color_control |= (pbs->logicop_func) << 16;
1223 } else
1224 color_control |= (0xcc << 16);
1225
1226 for (i = 0; i < 8; i++) {
1227 if (pbs->rt[i].blend_enable) {
1228 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1229 }
1230 target_mask |= (pbs->rt[i].colormask << (4 * i));
1231
1232 }
1233 rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
1234 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1235 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1236 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1237 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1238 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1239 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1240 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1241 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1242 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1243 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1244 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1245 if (radeon_state_pm4(rstate)) {
1246 radeon_state_decref(rstate);
1247 return NULL;
1248 }
1249 return rstate;
1250 }
1251
1252 int r600_context_hw_states(struct r600_context *rctx)
1253 {
1254 unsigned i;
1255 int r;
1256 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1257
1258 /* free previous TODO determine what need to be updated, what
1259 * doesn't
1260 */
1261 //radeon_state_decref(rctx->hw_states.config);
1262 rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
1263 rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
1264 rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
1265 rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
1266 rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
1267 rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
1268 rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
1269 for (i = 0; i < 8; i++) {
1270 rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
1271 }
1272 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1273 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1274 rctx->hw_states.ps_resource[i] = NULL;
1275 }
1276 rctx->hw_states.ps_nresource = 0;
1277 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1278 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1279 rctx->hw_states.ps_sampler[i] = NULL;
1280 }
1281 rctx->hw_states.ps_nsampler = 0;
1282
1283 /* build new states */
1284 rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1285 rctx->hw_states.scissor = r600_scissor(rctx);
1286 rctx->hw_states.dsa = r600_dsa(rctx);
1287 rctx->hw_states.blend = r600_blend(rctx);
1288 rctx->hw_states.viewport = r600_viewport(rctx);
1289 for (i = 0; i < nr_cbufs; i++) {
1290 rctx->hw_states.cb[i] = r600_cb(rctx, i);
1291 }
1292 rctx->hw_states.db = r600_db(rctx);
1293 rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
1294
1295 for (i = 0; i < rctx->ps_nsampler; i++) {
1296 if (rctx->ps_sampler[i]) {
1297 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1298 &rctx->ps_sampler[i]->state.sampler,
1299 R600_PS_SAMPLER + i);
1300 }
1301 }
1302 rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1303 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1304 if (rctx->ps_sampler_view[i]) {
1305 rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1306 &rctx->ps_sampler_view[i]->state.sampler_view,
1307 R600_PS_RESOURCE + i);
1308 }
1309 }
1310 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1311
1312 /* bind states */
1313 r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1314 if (r)
1315 return r;
1316 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1317 if (r)
1318 return r;
1319 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1320 if (r)
1321 return r;
1322 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1323 if (r)
1324 return r;
1325 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1326 if (r)
1327 return r;
1328 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1329 if (r)
1330 return r;
1331 for (i = 0; i < nr_cbufs; i++) {
1332 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
1333 if (r)
1334 return r;
1335 }
1336 r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1337 if (r)
1338 return r;
1339 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1340 if (r)
1341 return r;
1342 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1343 if (rctx->hw_states.ps_resource[i]) {
1344 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1345 if (r)
1346 return r;
1347 }
1348 }
1349 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1350 if (rctx->hw_states.ps_sampler[i]) {
1351 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1352 if (r)
1353 return r;
1354 }
1355 }
1356 return 0;
1357 }