1 #include <minix/drivers.h>
2 #include <minix/blockdriver.h>
3 #include <minix/drvlib.h>
5 #define VERBOSE 0 /* display identify messages during boot */
6 #define VERBOSE_DMA 0 /* display DMA debugging information */
8 #define ATAPI_DEBUG 0 /* To debug ATAPI code. */
10 /* I/O Ports used by winchester disk controllers. */
12 /* Read and write registers */
13 #define REG_CMD_BASE0 0x1F0 /* command base register of controller 0 */
14 #define REG_CMD_BASE1 0x170 /* command base register of controller 1 */
15 #define REG_CTL_BASE0 0x3F6 /* control base register of controller 0 */
16 #define REG_CTL_BASE1 0x376 /* control base register of controller 1 */
18 #define PCI_CTL_OFF 2 /* Offset of control registers from BAR2 */
19 #define PCI_DMA_2ND_OFF 8 /* Offset of DMA registers from BAR4 for
23 #define REG_DATA 0 /* data register (offset from the base reg.) */
24 #define REG_PRECOMP 1 /* start of write precompensation */
25 #define REG_COUNT 2 /* sectors to transfer */
26 #define REG_SECTOR 3 /* sector number */
27 #define REG_CYL_LO 4 /* low byte of cylinder number */
28 #define REG_CYL_HI 5 /* high byte of cylinder number */
29 #define REG_LDH 6 /* lba, drive and head */
30 #define LDH_DEFAULT 0xA0 /* ECC enable, 512 bytes per sector */
31 #define LDH_LBA 0x40 /* Use LBA addressing */
32 #define LDH_DEV 0x10 /* Drive 1 iff set */
33 #define ldh_init(drive) (LDH_DEFAULT | ((drive) << 4))
35 /* Read only registers */
36 #define REG_STATUS 7 /* status */
37 #define STATUS_BSY 0x80 /* controller busy */
38 #define STATUS_RDY 0x40 /* drive ready */
39 #define STATUS_WF 0x20 /* write fault */
40 #define STATUS_SC 0x10 /* seek complete (obsolete) */
41 #define STATUS_DRQ 0x08 /* data transfer request */
42 #define STATUS_CRD 0x04 /* corrected data */
43 #define STATUS_IDX 0x02 /* index pulse */
44 #define STATUS_ERR 0x01 /* error */
45 #define STATUS_ADMBSY 0x100 /* administratively busy (software) */
46 #define REG_ERROR 1 /* error code */
47 #define ERROR_BB 0x80 /* bad block */
48 #define ERROR_ECC 0x40 /* bad ecc bytes */
49 #define ERROR_ID 0x10 /* id not found */
50 #define ERROR_AC 0x04 /* aborted command */
51 #define ERROR_TK 0x02 /* track zero error */
52 #define ERROR_DM 0x01 /* no data address mark */
54 /* Write only registers */
55 #define REG_COMMAND 7 /* command */
56 #define CMD_IDLE 0x00 /* for w_command: drive idle */
57 #define CMD_RECALIBRATE 0x10 /* recalibrate drive */
58 #define CMD_READ 0x20 /* read data */
59 #define CMD_READ_EXT 0x24 /* read data (LBA48 addressed) */
60 #define CMD_READ_DMA_EXT 0x25 /* read data using DMA (w/ LBA48) */
61 #define CMD_WRITE 0x30 /* write data */
62 #define CMD_WRITE_EXT 0x34 /* write data (LBA48 addressed) */
63 #define CMD_WRITE_DMA_EXT 0x35 /* write data using DMA (w/ LBA48) */
64 #define CMD_READVERIFY 0x40 /* read verify */
65 #define CMD_FORMAT 0x50 /* format track */
66 #define CMD_SEEK 0x70 /* seek cylinder */
67 #define CMD_DIAG 0x90 /* execute device diagnostics */
68 #define CMD_SPECIFY 0x91 /* specify parameters */
69 #define CMD_READ_DMA 0xC8 /* read data using DMA */
70 #define CMD_WRITE_DMA 0xCA /* write data using DMA */
71 #define CMD_FLUSH_CACHE 0xE7 /* flush the write cache */
72 #define ATA_IDENTIFY 0xEC /* identify drive */
73 /* #define REG_CTL 0x206 */ /* control register */
74 #define REG_CTL 0 /* control register */
75 #define CTL_NORETRY 0x80 /* disable access retry */
76 #define CTL_NOECC 0x40 /* disable ecc retry */
77 #define CTL_EIGHTHEADS 0x08 /* more than eight heads */
78 #define CTL_RESET 0x04 /* reset controller */
79 #define CTL_INTDISABLE 0x02 /* disable interrupts */
80 #define REG_CTL_ALTSTAT 0 /* alternate status register */
83 #define ID_GENERAL 0x00 /* General configuration information */
84 #define ID_GEN_NOT_ATA 0x8000 /* Not an ATA device */
85 #define ID_CAPABILITIES 0x31 /* Capabilities (49)*/
86 #define ID_CAP_LBA 0x0200 /* LBA supported */
87 #define ID_CAP_DMA 0x0100 /* DMA supported */
88 #define ID_FIELD_VALIDITY 0x35 /* Field Validity (53) */
89 #define ID_FV_88 0x04 /* Word 88 is valid (UDMA) */
90 #define ID_MULTIWORD_DMA 0x3f /* Multiword DMA (63) */
91 #define ID_MWDMA_2_SEL 0x0400 /* Mode 2 is selected */
92 #define ID_MWDMA_1_SEL 0x0200 /* Mode 1 is selected */
93 #define ID_MWDMA_0_SEL 0x0100 /* Mode 0 is selected */
94 #define ID_MWDMA_2_SUP 0x0004 /* Mode 2 is supported */
95 #define ID_MWDMA_1_SUP 0x0002 /* Mode 1 is supported */
96 #define ID_MWDMA_0_SUP 0x0001 /* Mode 0 is supported */
97 #define ID_CSS 0x53 /* Command Sets Supported (83) */
98 #define ID_CSS_LBA48 0x0400
99 #define ID_ULTRA_DMA 0x58 /* Ultra DMA (88) */
100 #define ID_UDMA_5_SEL 0x2000 /* Mode 5 is selected */
101 #define ID_UDMA_4_SEL 0x1000 /* Mode 4 is selected */
102 #define ID_UDMA_3_SEL 0x0800 /* Mode 3 is selected */
103 #define ID_UDMA_2_SEL 0x0400 /* Mode 2 is selected */
104 #define ID_UDMA_1_SEL 0x0200 /* Mode 1 is selected */
105 #define ID_UDMA_0_SEL 0x0100 /* Mode 0 is selected */
106 #define ID_UDMA_5_SUP 0x0020 /* Mode 5 is supported */
107 #define ID_UDMA_4_SUP 0x0010 /* Mode 4 is supported */
108 #define ID_UDMA_3_SUP 0x0008 /* Mode 3 is supported */
109 #define ID_UDMA_2_SUP 0x0004 /* Mode 2 is supported */
110 #define ID_UDMA_1_SUP 0x0002 /* Mode 1 is supported */
111 #define ID_UDMA_0_SUP 0x0001 /* Mode 0 is supported */
114 #define DMA_COMMAND 0 /* Command register */
115 #define DMA_CMD_WRITE 0x08 /* PCI bus master writes */
116 #define DMA_CMD_START 0x01 /* Start Bus Master */
117 #define DMA_STATUS 2 /* Status register */
118 #define DMA_ST_D1_DMACAP 0x40 /* Drive 1 is DMA capable */
119 #define DMA_ST_D0_DMACAP 0x20 /* Drive 0 is DMA capable */
120 #define DMA_ST_INT 0x04 /* Interrupt */
121 #define DMA_ST_ERROR 0x02 /* Error */
122 #define DMA_ST_BM_ACTIVE 0x01 /* Bus Master IDE Active */
123 #define DMA_PRDTP 4 /* PRD Table Pointer */
125 /* Check for the presence of LBA48 only on drives that are 'big'. */
126 #define LBA48_CHECK_SIZE 0x0f000000
127 #define LBA_MAX_SIZE 0x0fffffff /* Highest sector size for
131 #define ERROR_SENSE 0xF0 /* sense key mask */
132 #define SENSE_NONE 0x00 /* no sense key */
133 #define SENSE_RECERR 0x10 /* recovered error */
134 #define SENSE_NOTRDY 0x20 /* not ready */
135 #define SENSE_MEDERR 0x30 /* medium error */
136 #define SENSE_HRDERR 0x40 /* hardware error */
137 #define SENSE_ILRQST 0x50 /* illegal request */
138 #define SENSE_UATTN 0x60 /* unit attention */
139 #define SENSE_DPROT 0x70 /* data protect */
140 #define SENSE_ABRT 0xb0 /* aborted command */
141 #define SENSE_MISCOM 0xe0 /* miscompare */
142 #define ERROR_MCR 0x08 /* media change requested */
143 #define ERROR_ABRT 0x04 /* aborted command */
144 #define ERROR_EOM 0x02 /* end of media detected */
145 #define ERROR_ILI 0x01 /* illegal length indication */
146 #define REG_FEAT 1 /* features */
147 #define FEAT_OVERLAP 0x02 /* overlap */
148 #define FEAT_DMA 0x01 /* dma */
149 #define REG_IRR 2 /* interrupt reason register */
150 #define IRR_REL 0x04 /* release */
151 #define IRR_IO 0x02 /* direction for xfer */
152 #define IRR_COD 0x01 /* command or data */
154 #define REG_CNT_LO 4 /* low byte of cylinder number */
155 #define REG_CNT_HI 5 /* high byte of cylinder number */
156 #define REG_DRIVE 6 /* drive select */
158 #define REG_STATUS 7 /* status */
159 #define STATUS_BSY 0x80 /* controller busy */
160 #define STATUS_DRDY 0x40 /* drive ready */
161 #define STATUS_DMADF 0x20 /* dma ready/drive fault */
162 #define STATUS_SRVCDSC 0x10 /* service or dsc */
163 #define STATUS_DRQ 0x08 /* data transfer request */
164 #define STATUS_CORR 0x04 /* correctable error occurred */
165 #define STATUS_CHECK 0x01 /* check error */
167 #define ATAPI_PACKETCMD 0xA0 /* packet command */
168 #define ATAPI_IDENTIFY 0xA1 /* identify drive */
169 #define SCSI_READ10 0x28 /* read from disk */
170 #define SCSI_SENSE 0x03 /* sense request */
172 #define ATAPI_PACKETSIZE 12
173 #define SENSE_PACKETSIZE 18
176 #define ERR (-1) /* general error */
177 #define ERR_BAD_SECTOR (-2) /* block marked bad detected */
179 /* Some controllers don't interrupt, the clock will wake us up. */
180 #define WAKEUP_SECS 32 /* drive may be out for 31 seconds max */
181 #define WAKEUP_TICKS (WAKEUP_SECS*system_hz)
184 #define MAX_DRIVES 4 /* max number of actual drives per instance */
185 #define MAX_DRIVENODES 8 /* number of drive nodes, for node numbering */
186 #define MAX_SECS 256 /* controller can transfer this many sectors */
187 #define MAX_ERRORS 4 /* how often to try rd/wt before quitting */
188 #define NR_MINORS (MAX_DRIVENODES * DEV_PER_DRIVE)
189 #define NR_SUBDEVS (MAX_DRIVENODES * SUB_PER_DRIVE)
190 #define DELAY_USECS 1000 /* controller timeout in microseconds */
191 #define DELAY_TICKS 1 /* controller timeout in ticks */
192 #define DEF_TIMEOUT_USECS 5000000L /* controller timeout in microseconds */
193 #define RECOVERY_USECS 500000 /* controller recovery time in microseconds */
194 #define RECOVERY_TICKS 30 /* controller recovery time in ticks */
195 #define INITIALIZED 0x01 /* drive is initialized */
196 #define DEAF 0x02 /* controller must be reset */
197 #define SMART 0x04 /* drive supports ATA commands */
198 #define ATAPI 0x08 /* it is an ATAPI device */
199 #define IDENTIFIED 0x10 /* w_identify done successfully */
200 #define IGNORING 0x20 /* w_identify failed once */
202 #define NO_DMA_VAR "ata_no_dma"
204 #define ATA_IF_NATIVE0 (1L << 0) /* first channel is in native mode */
205 #define ATA_IF_NATIVE1 (1L << 2) /* second channel is in native mode */
207 extern int sef_cb_lu_prepare(int state
);
208 extern int sef_cb_lu_state_isvalid(int state
, int flags
);
209 extern void sef_cb_lu_state_dump(int state
);
