| blob | df6f331257e63777fb6dd1bab81ae4ba2aa0f183 |
1 /* $NetBSD: sdhcreg.h,v 1.6 2012/03/02 18:20:34 nonaka Exp $ */
2 /* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */
4 /*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
20 #ifndef _SDHCREG_H_
21 #define _SDHCREG_H_
23 /* Host standard register set */
24 #define SDHC_DMA_ADDR 0x00
25 #define SDHC_BLOCK_SIZE 0x04
26 #define SDHC_BLOCK_COUNT 0x06
27 #define SDHC_BLOCK_COUNT_MAX 512
28 #define SDHC_ARGUMENT 0x08
29 #define SDHC_TRANSFER_MODE 0x0c
30 #define SDHC_MULTI_BLOCK_MODE (1<<5)
31 #define SDHC_READ_MODE (1<<4)
32 #define SDHC_AUTO_CMD12_ENABLE (1<<2)
33 #define SDHC_BLOCK_COUNT_ENABLE (1<<1)
34 #define SDHC_DMA_ENABLE (1<<0)
35 #define SDHC_COMMAND 0x0e
36 /* 14-15 reserved */
37 #define SDHC_COMMAND_INDEX_SHIFT 8
38 #define SDHC_COMMAND_INDEX_MASK 0x3f
39 #define SDHC_COMMAND_TYPE_ABORT (3<<6)
40 #define SDHC_COMMAND_TYPE_RESUME (2<<6)
41 #define SDHC_COMMAND_TYPE_SUSPEND (1<<6)
42 #define SDHC_COMMAND_TYPE_NORMAL (0<<6)
43 #define SDHC_DATA_PRESENT_SELECT (1<<5)
44 #define SDHC_INDEX_CHECK_ENABLE (1<<4)
45 #define SDHC_CRC_CHECK_ENABLE (1<<3)
46 /* 2 reserved */
47 #define SDHC_RESP_LEN_48_CHK_BUSY (3<<0)
48 #define SDHC_RESP_LEN_48 (2<<0)
49 #define SDHC_RESP_LEN_136 (1<<0)
50 #define SDHC_NO_RESPONSE (0<<0)
52 #define SDHC_DATA 0x20
53 #define SDHC_PRESENT_STATE 0x24
54 /* 25-31 reserved */
55 #define SDHC_CMD_LINE_SIGNAL_LEVEL (1<<24)
56 #define SDHC_DAT3_LINE_LEVEL (1<<23)
57 #define SDHC_DAT2_LINE_LEVEL (1<<22)
58 #define SDHC_DAT1_LINE_LEVEL (1<<21)
59 #define SDHC_DAT0_LINE_LEVEL (1<<20)
60 #define SDHC_WRITE_PROTECT_SWITCH (1<<19)
61 #define SDHC_CARD_DETECT_PIN_LEVEL (1<<18)
62 #define SDHC_CARD_STATE_STABLE (1<<17)
63 #define SDHC_CARD_INSERTED (1<<16)
64 /* 12-15 reserved */
65 #define SDHC_BUFFER_READ_ENABLE (1<<11)
66 #define SDHC_BUFFER_WRITE_ENABLE (1<<10)
67 #define SDHC_READ_TRANSFER_ACTIVE (1<<9)
68 #define SDHC_WRITE_TRANSFER_ACTIVE (1<<8)
69 /* 3-7 reserved */
70 #define SDHC_DAT_ACTIVE (1<<2)
71 #define SDHC_CMD_INHIBIT_DAT (1<<1)
72 #define SDHC_CMD_INHIBIT_CMD (1<<0)
73 #define SDHC_CMD_INHIBIT_MASK 0x0003
74 #define SDHC_HOST_CTL 0x28
75 #define SDHC_HIGH_SPEED (1<<2)
77 #define SDHC_4BIT_MODE (1<<1)
78 #define SDHC_LED_ON (1<<0)
79 #define SDHC_POWER_CTL 0x29
80 #define SDHC_VOLTAGE_SHIFT 1
81 #define SDHC_VOLTAGE_MASK 0x07
82 #define SDHC_VOLTAGE_3_3V 0x07
83 #define SDHC_VOLTAGE_3_0V 0x06
84 #define SDHC_VOLTAGE_1_8V 0x05
85 #define SDHC_BUS_POWER (1<<0)
86 #define SDHC_BLOCK_GAP_CTL 0x2a
87 #define SDHC_WAKEUP_CTL 0x2b
88 #define SDHC_CLOCK_CTL 0x2c
89 #define SDHC_SDCLK_DIV_SHIFT 8
90 #define SDHC_SDCLK_DIV_MASK 0xff
91 #define SDHC_SDCLK_XDIV_SHIFT 6
92 #define SDHC_SDCLK_XDIV_MASK 0x3
93 #define SDHC_SDCLK_CGM (1<<5)
94 #define SDHC_SDCLK_DVS_SHIFT 4
95 #define SDHC_SDCLK_DVS_MASK 0xf
96 #define SDHC_SDCLK_ENABLE (1<<2)
97 #define SDHC_INTCLK_STABLE (1<<1)
98 #define SDHC_INTCLK_ENABLE (1<<0)
99 #define SDHC_TIMEOUT_CTL 0x2e
100 #define SDHC_TIMEOUT_MAX 0x0e
101 #define SDHC_SOFTWARE_RESET 0x2f
102 #define SDHC_INIT_ACTIVE (1<<3)
103 #define SDHC_RESET_MASK 0x5
104 #define SDHC_RESET_DAT (1<<2)
105 #define SDHC_RESET_CMD (1<<1)
106 #define SDHC_RESET_ALL (1<<0)
107 #define SDHC_NINTR_STATUS 0x30
108 #define SDHC_ERROR_INTERRUPT (1<<15)
109 #define SDHC_CARD_INTERRUPT (1<<8)
110 #define SDHC_CARD_REMOVAL (1<<7)
111 #define SDHC_CARD_INSERTION (1<<6)
112 #define SDHC_BUFFER_READ_READY (1<<5)
113 #define SDHC_BUFFER_WRITE_READY (1<<4)
114 #define SDHC_DMA_INTERRUPT (1<<3)
115 #define SDHC_BLOCK_GAP_EVENT (1<<2)
116 #define SDHC_TRANSFER_COMPLETE (1<<1)
117 #define SDHC_COMMAND_COMPLETE (1<<0)
118 #define SDHC_NINTR_STATUS_MASK 0x81ff
119 #define SDHC_EINTR_STATUS 0x32
120 #define SDHC_DMA_ERROR (1<<12)
121 #define SDHC_AUTO_CMD12_ERROR (1<<8)
122 #define SDHC_CURRENT_LIMIT_ERROR (1<<7)
123 #define SDHC_DATA_END_BIT_ERROR (1<<6)
124 #define SDHC_DATA_CRC_ERROR (1<<5)
125 #define SDHC_DATA_TIMEOUT_ERROR (1<<4)
126 #define SDHC_CMD_INDEX_ERROR (1<<3)
127 #define SDHC_CMD_END_BIT_ERROR (1<<2)
128 #define SDHC_CMD_CRC_ERROR (1<<1)
129 #define SDHC_CMD_TIMEOUT_ERROR (1<<0)
131 #define SDHC_NINTR_STATUS_EN 0x34
132 #define SDHC_EINTR_STATUS_EN 0x36
133 #define SDHC_NINTR_SIGNAL_EN 0x38
134 #define SDHC_NINTR_SIGNAL_MASK 0x01ff
135 #define SDHC_EINTR_SIGNAL_EN 0x3a
137 #define SDHC_CMD12_ERROR_STATUS 0x3c
138 #define SDHC_CAPABILITIES 0x40
139 #define SDHC_VOLTAGE_SUPP_1_8V (1<<26)
140 #define SDHC_VOLTAGE_SUPP_3_0V (1<<25)
141 #define SDHC_VOLTAGE_SUPP_3_3V (1<<24)
142 #define SDHC_DMA_SUPPORT (1<<22)
143 #define SDHC_HIGH_SPEED_SUPP (1<<21)
144 #define SDHC_MAX_BLK_LEN_512 0
145 #define SDHC_MAX_BLK_LEN_1024 1
146 #define SDHC_MAX_BLK_LEN_2048 2
147 #define SDHC_MAX_BLK_LEN_4096 3
148 #define SDHC_MAX_BLK_LEN_SHIFT 16
149 #define SDHC_MAX_BLK_LEN_MASK 0x3
150 #define SDHC_BASE_FREQ_SHIFT 8
151 #define SDHC_BASE_FREQ_MASK 0x3f
153 #define SDHC_TIMEOUT_FREQ_SHIFT 0
154 #define SDHC_TIMEOUT_FREQ_MASK 0x1f
155 #define SDHC_MAX_CAPABILITIES 0x48
156 #define SDHC_HOST_VER 0xFC
157 #define SDHC_VVN_MASK 0x0f
158 #define SDHC_VVN_SHIFT 0x04
159 #define SDHC_SVN_MASK 0x0f
160 #define SDHC_SVN_SHIFT 0x00
161 #define SDHC_SLOT_INTR_STATUS 0xfc
162 #define SDHC_HOST_CTL_VERSION 0xfe
163 #define SDHC_SPEC_VERS_SHIFT 0
164 #define SDHC_SPEC_VERS_MASK 0xff
165 #define SDHC_VENDOR_VERS_SHIFT 8
166 #define SDHC_VENDOR_VERS_MASK 0xff
168 #define SDHC_DMA_SNOOP 0x40
170 /* SDHC_SPEC_VERS */
171 #define SDHC_SPEC_VERS_100 0x00
172 #define SDHC_SPEC_VERS_200 0x01
173 #define SDHC_SPEC_VERS_300 0x02
175 /* SDHC_CAPABILITIES decoding */
176 #define SDHC_BASE_FREQ_KHZ(cap) \
177 ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000)
178 #define SDHC_TIMEOUT_FREQ(cap) \
179 (((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK)
180 #define SDHC_TIMEOUT_FREQ_KHZ(cap) \
181 (((cap) & SDHC_TIMEOUT_FREQ_UNIT) ? \
182 SDHC_TIMEOUT_FREQ(cap) * 1000: \
183 SDHC_TIMEOUT_FREQ(cap))
185 /* SDHC_HOST_CTL_VERSION decoding */
186 #define SDHC_SPEC_VERSION(hcv) \
187 (((hcv) >> SDHC_SPEC_VERS_SHIFT) & SDHC_SPEC_VERS_MASK)
188 #define SDHC_VENDOR_VERSION(hcv) \
189 (((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK)
191 #define SDHC_PRESENT_STATE_BITS \
193 "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC"
194 #define SDHC_NINTR_STATUS_BITS \
196 "\4DMA\3GAP\2XFER\1CMD"
197 #define SDHC_EINTR_STATUS_BITS \
198 "\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT"
199 #define SDHC_CAPABILITIES_BITS \
200 "\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED"