sys/arch/arm/include/arm32/frame.h

   1 /*      $NetBSD: frame.h,v 1.42 2015/04/17 17:28:33 matt Exp $  */
   2
   3 /*
   4  * Copyright (c) 1994-1997 Mark Brinicombe.
   5  * Copyright (c) 1994 Brini.
   6  * All rights reserved.
   7  *
   8  * This code is derived from software written for Brini by Mark Brinicombe
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by Brini.
  21  * 4. The name of the company nor the name of the author may be used to
  22  *    endorse or promote products derived from this software without specific
  23  *    prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  26  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  27  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  29  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  30  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  35  * SUCH DAMAGE.
  36  *
  37  * RiscBSD kernel project
  38  *
  39  * frame.h
  40  *
  41  * Stack frames structures
  42  *
  43  * Created      : 30/09/94
  44  */
  45
  46 #ifndef _ARM32_FRAME_H_
  47 #define _ARM32_FRAME_H_
  48
  49 #include <arm/frame.h>          /* Common ARM stack frames */
  50
  51 #ifndef _LOCORE
  52
  53 /*
  54  * Switch frame.
  55  *
  56  * Should be a multiple of 8 bytes for dumpsys.
  57  */
  58
  59 struct switchframe {
  60         u_int   sf_r4;
  61         u_int   sf_r5;
  62         u_int   sf_r6;
  63         u_int   sf_r7;
  64         u_int   sf_sp;
  65         u_int   sf_pc;
  66 };
  67
  68 /*
  69  * System stack frames.
  70  */
  71
  72 struct clockframe {
  73         struct trapframe cf_tf;
  74 };
  75
  76 /*
  77  * Stack frame. Used during stack traces (db_trace.c)
  78  */
  79 struct frame {
  80         u_int   fr_fp;
  81         u_int   fr_sp;
  82         u_int   fr_lr;
  83         u_int   fr_pc;
  84 };
  85
  86 #ifdef _KERNEL
  87 void validate_trapframe(trapframe_t *, int);
  88 #endif /* _KERNEL */
  89
  90 #else /* _LOCORE */
  91
  92 #include "opt_compat_netbsd.h"
  93 #include "opt_execfmt.h"
  94 #include "opt_multiprocessor.h"
  95 #include "opt_cpuoptions.h"
  96 #include "opt_arm_debug.h"
  97 #include "opt_cputypes.h"
  98
  99 #include <arm/locore.h>
 100
 101 /*
 102  * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
 103  * any pending softints.
 104  */
 105 #ifdef _ARM_ARCH_4T
 106 #define B_CF_CONTROL(rX)                                                ;\
 107         ldr     ip, [rX, #CF_CONTROL]   /* get function addr */         ;\
 108         bx      ip                      /* branch to cpu_control */
 109 #else
 110 #define B_CF_CONTROL(rX)                                                ;\
 111         ldr     pc, [rX, #CF_CONTROL]   /* branch to cpu_control */
 112 #endif
 113 #ifdef _ARM_ARCH_5T
 114 #define BL_CF_CONTROL(rX)                                               ;\
 115         ldr     ip, [rX, #CF_CONTROL]   /* get function addr */         ;\
 116         blx     ip                      /* call cpu_control */
 117 #else
 118 #define BL_CF_CONTROL(rX)                                               ;\
 119         mov     lr, pc                                                  ;\
 120         ldr     pc, [rX, #CF_CONTROL]   /* call cpu_control */
 121 #endif
 122 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
 123 #define DO_PENDING_SOFTINTS                                             \
 124         ldr     r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */    ;\
 125         cmp     r0, #0                  /* Test for 0. */               ;\
 126         bne     10f                     /*   skip softints if != 0 */   ;\
 127         ldr     r0, [r4, #CI_CPL]       /* Get current priority level */;\
 128         ldr     r1, [r4, #CI_SOFTINTS]  /* Get pending softint mask */  ;\
 129         lsrs    r0, r1, r0              /* shift mask by cpl */         ;\
 130         blne    _C_LABEL(dosoftints)    /* dosoftints(void) */          ;\
 131 10:
 132 #else
 133 #define DO_PENDING_SOFTINTS             /* nothing */
 134 #endif
 135
 136 #ifdef _ARM_ARCH_6
 137 #define GET_CPSR(rb)                    /* nothing */
 138 #define CPSID_I(ra,rb)                  cpsid   i
 139 #define CPSIE_I(ra,rb)                  cpsie   i
 140 #else
 141 #define GET_CPSR(rb)                                                    \
 142         mrs     rb, cpsr                /* fetch CPSR */
 143
 144 #define CPSID_I(ra,rb)                                                  \
 145         orr     ra, rb, #(IF32_bits)                                    ;\
 146         msr     cpsr_c, ra              /* Disable interrupts */
 147
 148 #define CPSIE_I(ra,rb)                                                  \
 149         bic     ra, rb, #(IF32_bits)                                    ;\
 150         msr     cpsr_c, ra              /* Restore interrupts */
 151 #endif
 152
 153 #ifdef __HAVE_PREEMPTION
 154 #define DO_CLEAR_ASTPENDING                                             \
 155         mvn     r1, #1                  /* complement of 1 */           ;\
 156         add     r0, r4, #CI_ASTPENDING  /* address of astpending */     ;\
 157         bl      _C_LABEL(atomic_and_uint) /* clear AST */
 158 #else
 159 #define DO_CLEAR_ASTPENDING                                             \
 160         mov     r0, #0                                                  ;\
 161         str     r0, [r4, #CI_ASTPENDING] /* clear AST */
 162 #endif
 163
 164 #define DO_PENDING_AST(lbl)                                             ;\
 165 1:      ldr     r1, [r4, #CI_ASTPENDING] /* Pending AST? */             ;\
 166         tst     r1, #0x00000001                                         ;\
 167         beq     lbl                     /* Nope. Just bail */           ;\
 168         DO_CLEAR_ASTPENDING                                             ;\
 169         CPSIE_I(r5, r5)                 /* Restore interrupts */        ;\
 170         mov     r0, sp                                                  ;\
 171         bl      _C_LABEL(ast)           /* ast(frame) */                ;\
 172         CPSID_I(r0, r5)                 /* Disable interrupts */        ;\
 173         b       1b                      /* test again */
 174
 175 /*
 176  * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
 177  * These are used in order to support dynamic enabling/disabling of
 178  * alignment faults when executing old a.out ARM binaries.
 179  *
 180  * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain
 181  * pointer to the cpu's cpu_info.  DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
 182  * relies on r4 being preserved.
 183  */
 184 #ifdef EXEC_AOUT
 185 #define AST_ALIGNMENT_FAULT_LOCALS                                      \
 186 .Laflt_cpufuncs:                                                        ;\
 187         .word   _C_LABEL(cpufuncs)
 188
 189 /*
 190  * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
 191  * the top of interrupt/exception handlers.
 192  *
 193  * When invoked, r0 *must* contain the value of SPSR on the current
 194  * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
 195  * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
 196  */
 197 #define ENABLE_ALIGNMENT_FAULTS                                         \
 198         and     r7, r0, #(PSR_MODE)     /* Test for USR32 mode */       ;\
 199         cmp     r7, #(PSR_USR32_MODE)                                   ;\
 200         GET_CURCPU(r4)                  /* r4 = cpuinfo */              ;\
 201         bne     1f                      /* Not USR mode skip AFLT */    ;\
 202         ldr     r1, [r4, #CI_CURLWP]    /* get curlwp from cpu_info */  ;\
 203         ldr     r1, [r1, #L_MD_FLAGS]   /* Fetch l_md.md_flags */       ;\
 204         tst     r1, #MDLWP_NOALIGNFLT                                   ;\
 205         beq     1f                      /* AFLTs already enabled */     ;\
 206         ldr     r2, .Laflt_cpufuncs                                     ;\
 207         ldr     r1, [r4, #CI_CTRL]      /* Fetch control register */    ;\
 208         mov     r0, #-1                                                 ;\
 209         BL_CF_CONTROL(r2)               /* Enable alignment faults */   ;\
 210 1:      /* done */
 211
 212 /*
 213  * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
 214  * PULLFRAME at the end of interrupt/exception handlers.  We know that
 215  * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did
 216  * for use.
 217  */
 218 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS                             \
 219         DO_PENDING_SOFTINTS                                             ;\
 220         GET_CPSR(r5)                    /* save CPSR */                 ;\
 221         CPSID_I(r1, r5)                 /* Disable interrupts */        ;\
 222         cmp     r7, #(PSR_USR32_MODE)   /* Returning to USR mode? */    ;\
 223         bne     3f                      /* Nope, get out now */         ;\
 224         DO_PENDING_AST(2f)              /* Pending AST? */              ;\
 225 2:      ldr     r1, [r4, #CI_CURLWP]    /* get curlwp from cpu_info */  ;\
 226         ldr     r0, [r1, #L_MD_FLAGS]   /* get md_flags from lwp */     ;\
 227         tst     r0, #MDLWP_NOALIGNFLT                                   ;\
 228         beq     3f                      /* Keep AFLTs enabled */        ;\
 229         ldr     r1, [r4, #CI_CTRL]      /* Fetch control register */    ;\
 230         ldr     r2, .Laflt_cpufuncs                                     ;\
 231         mov     r0, #-1                                                 ;\
 232         bic     r1, r1, #CPU_CONTROL_AFLT_ENABLE  /* Disable AFLTs */   ;\
 233         BL_CF_CONTROL(r2)               /* Set new CTRL reg value */    ;\
 234 3:      /* done */
 235
 236 #else   /* !EXEC_AOUT */
 237
 238 #define AST_ALIGNMENT_FAULT_LOCALS
 239
 240 #define ENABLE_ALIGNMENT_FAULTS                                         \
 241         and     r7, r0, #(PSR_MODE)     /* Test for USR32 mode */       ;\
 242         GET_CURCPU(r4)                  /* r4 = cpuinfo */
 243
 244
 245 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS                             \
 246         DO_PENDING_SOFTINTS                                             ;\
 247         GET_CPSR(r5)                    /* save CPSR */                 ;\
 248         CPSID_I(r1, r5)                 /* Disable interrupts */        ;\
 249         cmp     r7, #(PSR_USR32_MODE)                                   ;\
 250         bne     2f                      /* Nope, get out now */         ;\
 251         DO_PENDING_AST(2f)              /* Pending AST? */              ;\
 252 2:      /* done */
 253 #endif /* EXEC_AOUT */
 254
 255 #ifndef _ARM_ARCH_6
 256 #ifdef ARM_LOCK_CAS_DEBUG
 257 #define LOCK_CAS_DEBUG_LOCALS                                            \
 258 .L_lock_cas_restart:                                                    ;\
 259         .word   _C_LABEL(_lock_cas_restart)
 260
 261 #if defined(__ARMEB__)
 262 #define LOCK_CAS_DEBUG_COUNT_RESTART                                     \
 263         ble     99f                                                     ;\
 264         ldr     r0, .L_lock_cas_restart                                 ;\
 265         ldmia   r0, {r1-r2}             /* load ev_count */             ;\
 266         adds    r2, r2, #1              /* 64-bit incr (lo) */          ;\
 267         adc     r1, r1, #0              /* 64-bit incr (hi) */          ;\
 268         stmia   r0, {r1-r2}             /* store ev_count */
 269 #else /* __ARMEB__ */
 270 #define LOCK_CAS_DEBUG_COUNT_RESTART                                     \
 271         ble     99f                                                     ;\
 272         ldr     r0, .L_lock_cas_restart                                 ;\
 273         ldmia   r0, {r1-r2}             /* load ev_count */             ;\
 274         adds    r1, r1, #1              /* 64-bit incr (lo) */          ;\
 275         adc     r2, r2, #0              /* 64-bit incr (hi) */          ;\
 276         stmia   r0, {r1-r2}             /* store ev_count */
 277 #endif /* __ARMEB__ */
 278 #else /* ARM_LOCK_CAS_DEBUG */
 279 #define LOCK_CAS_DEBUG_LOCALS           /* nothing */
 280 #define LOCK_CAS_DEBUG_COUNT_RESTART    /* nothing */
 281 #endif /* ARM_LOCK_CAS_DEBUG */
 282
 283 #define LOCK_CAS_CHECK_LOCALS                                            \
 284 .L_lock_cas:                                                            ;\
 285         .word   _C_LABEL(_lock_cas)                                     ;\
 286 .L_lock_cas_end:                                                        ;\
 287         .word   _C_LABEL(_lock_cas_end)                                 ;\
 288 LOCK_CAS_DEBUG_LOCALS
 289
 290 #define LOCK_CAS_CHECK                                                   \
 291         ldr     r0, [sp]                /* get saved PSR */             ;\
 292         and     r0, r0, #(PSR_MODE)     /* check for SVC32 mode */      ;\
 293         cmp     r0, #(PSR_SVC32_MODE)                                   ;\
 294         bne     99f                     /* nope, get out now */         ;\
 295         ldr     r0, [sp, #(TF_PC)]                                      ;\
 296         ldr     r1, .L_lock_cas_end                                     ;\
 297         cmp     r0, r1                                                  ;\
 298         bge     99f                                                     ;\
 299         ldr     r1, .L_lock_cas                                         ;\
 300         cmp     r0, r1                                                  ;\
 301         strgt   r1, [sp, #(TF_PC)]                                      ;\
 302         LOCK_CAS_DEBUG_COUNT_RESTART                                    ;\
 303 99:
 304
 305 #else
 306 #define LOCK_CAS_CHECK                  /* nothing */
 307 #define LOCK_CAS_CHECK_LOCALS           /* nothing */
 308 #endif
 309
 310 /*
 311  * ASM macros for pushing and pulling trapframes from the stack
 312  *
 313  * These macros are used to handle the trapframe structure defined above.
 314  */
 315
 316 /*
 317  * PUSHFRAME - macro to push a trap frame on the stack in the current mode
 318  * Since the current mode is used, the SVC lr field is not defined.
 319  */
 320
 321 #ifdef CPU_SA110
 322 /*
 323  * NOTE: r13 and r14 are stored separately as a work around for the
 324  * SA110 rev 2 STM^ bug
 325  */
 326 #define PUSHUSERREGS                                                       \
 327         stmia   sp, {r0-r12};           /* Push the user mode registers */ \
 328         add     r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \
 329         stmia   r0, {r13-r14}^          /* Push the user mode registers */
 330 #else
 331 #define PUSHUSERREGS                                                       \
 332         stmia   sp, {r0-r14}^           /* Push the user mode registers */
 333 #endif
 334
 335 #define PUSHFRAME                                                          \
 336         str     lr, [sp, #-4]!;         /* Push the return address */      \
 337         sub     sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */     \
 338         PUSHUSERREGS;                   /* Push the user mode registers */ \
 339         mov     r0, r0;                 /* NOP for previous instruction */ \
 340         mrs     r0, spsr;               /* Get the SPSR */                 \
 341         str     r0, [sp, #-TF_R0]!      /* Push the SPSR on the stack */
 342
 343 /*
 344  * Push a minimal trapframe so we can dispatch an interrupt from the
 345  * idle loop.  The only reason the idle loop wakes up is to dispatch
 346  * interrupts so why take the avoid of a full exception when we can do
 347  * something minimal.
 348  */
 349 #define PUSHIDLEFRAME                                                      \
 350         str     lr, [sp, #-4]!;         /* save SVC32 lr */                \
 351         str     r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */      \
 352         str     r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */      \
 353         mrs     r0, cpsr;               /* Get the CPSR */                 \
 354         str     r0, [sp, #(-TF_R4)]!    /* Push the CPSR on the stack */
 355
 356 /*
 357  * Push a trapframe to be used by cpu_switchto
 358  */
 359 #define PUSHSWITCHFRAME(rX)                                             \
 360         mov     ip, sp;                                                 \
 361         sub     sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \
 362         push    {r4-r11};               /* Push the callee saved registers */ \
 363         sub     sp, sp, #TF_R4;         /* reserve rest of trapframe */ \
 364         str     ip, [sp, #TF_SVC_SP];                                   \
 365         str     lr, [sp, #TF_SVC_LR];                                   \
 366         str     lr, [sp, #TF_PC];                                       \
 367         mrs     rX, cpsr;               /* Get the CPSR */              \
 368         str     rX, [sp, #TF_SPSR]      /* save in trapframe */
 369
 370 #define PUSHSWITCHFRAME1                                                   \
 371         mov     ip, sp;                                                    \
 372         sub     sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \
 373         push    {r4-r7};                /* Push some of the callee saved registers */ \
 374         sub     sp, sp, #TF_R4;         /* reserve rest of trapframe */ \
 375         str     ip, [sp, #TF_SVC_SP];                                   \
 376         str     lr, [sp, #TF_SVC_LR];                                   \
 377         str     lr, [sp, #TF_PC]
 378
 379 #if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__
 380 #define PUSHSWITCHFRAME2                                                \
 381         strd    r10, [sp, #TF_R10];     /* save r10 & r11 */            \
 382         strd    r8, [sp, #TF_R8];       /* save r8 & r9 */              \
 383         mrs     r0, cpsr;               /* Get the CPSR */              \
 384         str     r0, [sp, #TF_SPSR]      /* save in trapframe */
 385 #else
 386 #define PUSHSWITCHFRAME2                                                \
 387         add     r0, sp, #TF_R8;         /* get ptr to r8 and above */   \
 388         stmia   r0, {r8-r11};           /* save rest of registers */    \
 389         mrs     r0, cpsr;               /* Get the CPSR */              \
 390         str     r0, [sp, #TF_SPSR]      /* save in trapframe */
 391 #endif
 392
 393 /*
 394  * PULLFRAME - macro to pull a trap frame from the stack in the current mode
 395  * Since the current mode is used, the SVC lr field is ignored.
 396  */
 397
 398 #define PULLFRAME                                                          \
 399         ldr     r0, [sp], #TF_R0;       /* Pop the SPSR from stack */      \
 400         msr     spsr_fsxc, r0;                                             \
 401         ldmia   sp, {r0-r14}^;          /* Restore registers (usr mode) */ \
 402         mov     r0, r0;                 /* NOP for previous instruction */ \
 403         add     sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */     \
 404         ldr     lr, [sp], #0x0004       /* Pop the return address */
 405
 406 #define PULLIDLEFRAME                                                      \
 407         add     sp, sp, #TF_R4;         /* Adjust the stack pointer */     \
 408         ldr     r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */    \
 409         ldr     r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */    \
 410         ldr     lr, [sp], #4            /* Pop the return address */
 411
 412 /*
 413  * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1).
 414  */
 415 #define PULLSWITCHFRAME                                                 \
 416         add     sp, sp, #TF_R4;         /* Adjust the stack pointer */  \
 417         pop     {r4-r11};               /* pop the callee saved registers */ \
 418         add     sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \
 419         ldr     lr, [sp], #4;           /* pop the return address */
 420
 421 /*
 422  * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
 423  * This should only be used if the processor is not currently in SVC32
 424  * mode. The processor mode is switched to SVC mode and the trap frame is
 425  * stored. The SVC lr field is used to store the previous value of
 426  * lr in SVC mode.
 427  *
 428  * NOTE: r13 and r14 are stored separately as a work around for the
 429  * SA110 rev 2 STM^ bug
 430  */
 431
 432 #ifdef _ARM_ARCH_6
 433 #define SET_CPSR_MODE(tmp, mode)        \
 434         cps     #(mode)
 435 #else
 436 #define SET_CPSR_MODE(tmp, mode)        \
 437         mrs     tmp, cpsr;              /* Get the CPSR */                 \
 438         bic     tmp, tmp, #(PSR_MODE);  /* Fix for SVC mode */             \
 439         orr     tmp, tmp, #(mode);                                         \
 440         msr     cpsr_c, tmp             /* Punch into SVC mode */
 441 #endif
 442
 443 #define PUSHFRAMEINSVC                                                     \
 444         stmdb   sp, {r0-r3};            /* Save 4 registers */             \
 445         mov     r0, lr;                 /* Save xxx32 r14 */               \
 446         mov     r1, sp;                 /* Save xxx32 sp */                \
 447         mrs     r3, spsr;               /* Save xxx32 spsr */              \
 448         SET_CPSR_MODE(r2, PSR_SVC32_MODE);                                 \
 449         bic     r2, sp, #7;             /* Align new SVC sp */             \
 450         str     r0, [r2, #-4]!;         /* Push return address */          \
 451         stmdb   r2!, {sp, lr};          /* Push SVC sp, lr */              \
 452         mov     sp, r2;                 /* Keep stack aligned */           \
 453         msr     spsr_fsxc, r3;          /* Restore correct spsr */         \
 454         ldmdb   r1, {r0-r3};            /* Restore 4 regs from xxx mode */ \
 455         sub     sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
 456         PUSHUSERREGS;                   /* Push the user mode registers */ \
 457         mov     r0, r0;                 /* NOP for previous instruction */ \
 458         mrs     r0, spsr;               /* Get the SPSR */                 \
 459         str     r0, [sp, #-TF_R0]!      /* Push the SPSR onto the stack */
 460
 461 /*
 462  * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
 463  * in SVC32 mode and restore the saved processor mode and PC.
 464  * This should be used when the SVC lr register needs to be restored on
 465  * exit.
 466  */
 467
 468 #define PULLFRAMEFROMSVCANDEXIT                                            \
 469         ldr     r0, [sp], #0x0008;      /* Pop the SPSR from stack */      \
 470         msr     spsr_fsxc, r0;          /* restore SPSR */                 \
 471         ldmia   sp, {r0-r14}^;          /* Restore registers (usr mode) */ \
 472         mov     r0, r0;                 /* NOP for previous instruction */ \
 473         add     sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
 474         ldmia   sp, {sp, lr, pc}^       /* Restore lr and exit */
 475
 476 #endif /* _LOCORE */
 477
 478 #endif /* _ARM32_FRAME_H_ */