sys/arch/arm/include/cpufunc_proto.h

   1 /*      cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp      */
   2
   3 /*
   4  * Copyright (c) 1997 Mark Brinicombe.
   5  * Copyright (c) 1997 Causality Limited
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Causality Limited.
  19  * 4. The name of Causality Limited may not be used to endorse or promote
  20  *    products derived from this software without specific prior written
  21  *    permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
  24  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
  27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * RiscBSD kernel project
  36  *
  37  * cpufunc.h
  38  *
  39  * Prototypes for cpu, mmu and tlb related functions.
  40  */
  41
  42 #ifndef _ARM_CPUFUNC_PROTO_H_
  43 #define _ARM_CPUFUNC_PROTO_H_
  44
  45 #ifdef _KERNEL
  46
  47 #include <sys/types.h>
  48 #include <arm/armreg.h>
  49 #include <arm/cpuconf.h>
  50
  51 #if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)
  52 void    arm3_cache_flush        (void);
  53 #endif  /* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */
  54
  55 #ifdef CPU_ARM2
  56 u_int   arm2_id                 (void);
  57 #endif /* CPU_ARM2 */
  58
  59 #ifdef CPU_ARM250
  60 u_int   arm250_id               (void);
  61 #endif
  62
  63 #ifdef CPU_ARM3
  64 u_int   arm3_control            (u_int, u_int);
  65 #endif  /* CPU_ARM3 */
  66
  67 #if defined(CPU_ARM6) || defined(CPU_ARM7)
  68 void    arm67_setttb            (u_int, bool);
  69 void    arm67_tlb_flush         (void);
  70 void    arm67_tlb_purge         (vaddr_t);
  71 void    arm67_cache_flush       (void);
  72 void    arm67_context_switch    (u_int);
  73 #endif  /* CPU_ARM6 || CPU_ARM7 */
  74
  75 #ifdef CPU_ARM6
  76 void    arm6_setup              (char *);
  77 #endif  /* CPU_ARM6 */
  78
  79 #ifdef CPU_ARM7
  80 void    arm7_setup              (char *);
  81 #endif  /* CPU_ARM7 */
  82
  83 #ifdef CPU_ARM7TDMI
  84 int     arm7_dataabt_fixup      (void *);
  85 void    arm7tdmi_setup          (char *);
  86 void    arm7tdmi_setttb         (u_int, bool);
  87 void    arm7tdmi_tlb_flushID    (void);
  88 void    arm7tdmi_tlb_flushID_SE (vaddr_t);
  89 void    arm7tdmi_cache_flushID  (void);
  90 void    arm7tdmi_context_switch (u_int);
  91 #endif /* CPU_ARM7TDMI */
  92
  93 #ifdef CPU_ARM8
  94 void    arm8_setttb             (u_int, bool);
  95 void    arm8_tlb_flushID        (void);
  96 void    arm8_tlb_flushID_SE     (vaddr_t);
  97 void    arm8_cache_flushID      (void);
  98 void    arm8_cache_flushID_E    (u_int);
  99 void    arm8_cache_cleanID      (void);
 100 void    arm8_cache_cleanID_E    (u_int);
 101 void    arm8_cache_purgeID      (void);
 102 void    arm8_cache_purgeID_E    (u_int entry);
 103
 104 void    arm8_cache_syncI        (void);
 105 void    arm8_cache_cleanID_rng  (vaddr_t, vsize_t);
 106 void    arm8_cache_cleanD_rng   (vaddr_t, vsize_t);
 107 void    arm8_cache_purgeID_rng  (vaddr_t, vsize_t);
 108 void    arm8_cache_purgeD_rng   (vaddr_t, vsize_t);
 109 void    arm8_cache_syncI_rng    (vaddr_t, vsize_t);
 110
 111 void    arm8_context_switch     (u_int);
 112
 113 void    arm8_setup              (char *);
 114
 115 u_int   arm8_clock_config       (u_int, u_int);
 116 #endif
 117
 118 #ifdef CPU_FA526
 119 void    fa526_setup             (char *);
 120 void    fa526_setttb            (u_int, bool);
 121 void    fa526_context_switch    (u_int);
 122 void    fa526_cpu_sleep         (int);
 123 void    fa526_tlb_flushI_SE     (vaddr_t);
 124 void    fa526_tlb_flushID_SE    (vaddr_t);
 125 void    fa526_flush_prefetchbuf (void);
 126 void    fa526_flush_brnchtgt_E  (u_int);
 127
 128 void    fa526_icache_sync_all   (void);
 129 void    fa526_icache_sync_range(vaddr_t, vsize_t);
 130 void    fa526_dcache_wbinv_all  (void);
 131 void    fa526_dcache_wbinv_range(vaddr_t, vsize_t);
 132 void    fa526_dcache_inv_range  (vaddr_t, vsize_t);
 133 void    fa526_dcache_wb_range   (vaddr_t, vsize_t);
 134 void    fa526_idcache_wbinv_all(void);
 135 void    fa526_idcache_wbinv_range(vaddr_t, vsize_t);
 136 #endif
 137
 138 #ifdef CPU_SA110
 139 void    sa110_setup             (char *);
 140 void    sa110_context_switch    (u_int);
 141 #endif  /* CPU_SA110 */
 142
 143 #if defined(CPU_SA1100) || defined(CPU_SA1110)
 144 void    sa11x0_drain_readbuf    (void);
 145
 146 void    sa11x0_context_switch   (u_int);
 147 void    sa11x0_cpu_sleep        (int);
 148
 149 void    sa11x0_setup            (char *);
 150 #endif
 151
 152 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
 153 void    sa1_setttb              (u_int, bool);
 154
 155 void    sa1_tlb_flushID_SE      (vaddr_t);
 156
 157 void    sa1_cache_flushID       (void);
 158 void    sa1_cache_flushI        (void);
 159 void    sa1_cache_flushD        (void);
 160 void    sa1_cache_flushD_SE     (vaddr_t);
 161
 162 void    sa1_cache_cleanID       (void);
 163 void    sa1_cache_cleanD        (void);
 164 void    sa1_cache_cleanD_E      (u_int);
 165
 166 void    sa1_cache_purgeID       (void);
 167 void    sa1_cache_purgeID_E     (u_int);
 168 void    sa1_cache_purgeD        (void);
 169 void    sa1_cache_purgeD_E      (u_int);
 170
 171 void    sa1_cache_syncI         (void);
 172 void    sa1_cache_cleanID_rng   (vaddr_t, vsize_t);
 173 void    sa1_cache_cleanD_rng    (vaddr_t, vsize_t);
 174 void    sa1_cache_purgeID_rng   (vaddr_t, vsize_t);
 175 void    sa1_cache_purgeD_rng    (vaddr_t, vsize_t);
 176 void    sa1_cache_syncI_rng     (vaddr_t, vsize_t);
 177
 178 #endif
 179
 180 #ifdef CPU_ARM9
 181 void    arm9_setttb             (u_int, bool);
 182
 183 void    arm9_tlb_flushID_SE     (vaddr_t);
 184
 185 void    arm9_icache_sync_all    (void);
 186 void    arm9_icache_sync_range  (vaddr_t, vsize_t);
 187
 188 void    arm9_dcache_wbinv_all   (void);
 189 void    arm9_dcache_wbinv_range (vaddr_t, vsize_t);
 190 void    arm9_dcache_inv_range   (vaddr_t, vsize_t);
 191 void    arm9_dcache_wb_range    (vaddr_t, vsize_t);
 192
 193 void    arm9_idcache_wbinv_all  (void);
 194 void    arm9_idcache_wbinv_range (vaddr_t, vsize_t);
 195
 196 void    arm9_context_switch     (u_int);
 197
 198 void    arm9_setup              (char *);
 199
 200 extern unsigned arm9_dcache_sets_max;
 201 extern unsigned arm9_dcache_sets_inc;
 202 extern unsigned arm9_dcache_index_max;
 203 extern unsigned arm9_dcache_index_inc;
 204 #endif
 205
 206 #if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA)
 207 void    arm10_tlb_flushID_SE    (vaddr_t);
 208 void    arm10_tlb_flushI_SE     (vaddr_t);
 209
 210 void    arm10_context_switch    (u_int);
 211
 212 void    arm10_setup             (char *);
 213 #endif
 214
 215 #if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA)
 216 void    armv5_ec_setttb                 (u_int, bool);
 217
 218 void    armv5_ec_icache_sync_all        (void);
 219 void    armv5_ec_icache_sync_range      (vaddr_t, vsize_t);
 220
 221 void    armv5_ec_dcache_wbinv_all       (void);
 222 void    armv5_ec_dcache_wbinv_range     (vaddr_t, vsize_t);
 223 void    armv5_ec_dcache_inv_range       (vaddr_t, vsize_t);
 224 void    armv5_ec_dcache_wb_range        (vaddr_t, vsize_t);
 225
 226 void    armv5_ec_idcache_wbinv_all      (void);
 227 void    armv5_ec_idcache_wbinv_range    (vaddr_t, vsize_t);
 228 #endif
 229
 230 #if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE)
 231 void    armv5_setttb            (u_int, bool);
 232
 233 void    armv5_icache_sync_all   (void);
 234 void    armv5_icache_sync_range (vaddr_t, vsize_t);
 235
 236 void    armv5_dcache_wbinv_all  (void);
 237 void    armv5_dcache_wbinv_range (vaddr_t, vsize_t);
 238 void    armv5_dcache_inv_range  (vaddr_t, vsize_t);
 239 void    armv5_dcache_wb_range   (vaddr_t, vsize_t);
 240
 241 void    armv5_idcache_wbinv_all (void);
 242 void    armv5_idcache_wbinv_range (vaddr_t, vsize_t);
 243
 244 extern unsigned armv5_dcache_sets_max;
 245 extern unsigned armv5_dcache_sets_inc;
 246 extern unsigned armv5_dcache_index_max;
 247 extern unsigned armv5_dcache_index_inc;
 248 #endif
 249
 250 #if defined(CPU_ARM11MPCORE)
 251 void    arm11mpcore_setup               (char *);
 252 #endif
 253
 254 #if defined(CPU_ARM11)
 255 #if defined(ARM_MMU_EXTENDED)
 256 void    arm11_setttb            (u_int, tlb_asid_t);
 257 void    arm11_context_switch    (u_int, tlb_asid_t);
 258 #else
 259 void    arm11_setttb            (u_int, bool);
 260 void    arm11_context_switch    (u_int);
 261 #endif
 262
 263 void    arm11_cpu_sleep         (int);
 264 void    arm11_setup             (char *string);
 265 void    arm11_tlb_flushID       (void);
 266 void    arm11_tlb_flushI        (void);
 267 void    arm11_tlb_flushD        (void);
 268 void    arm11_tlb_flushID_SE    (vaddr_t);
 269 void    arm11_tlb_flushI_SE     (vaddr_t);
 270 void    arm11_tlb_flushD_SE     (vaddr_t);
 271
 272 void    armv11_dcache_wbinv_all (void);
 273 void    armv11_idcache_wbinv_all(void);
 274
 275 void    arm11_drain_writebuf    (void);
 276 void    arm11_sleep             (int);
 277
 278 void    armv6_setttb            (u_int, bool);
 279
 280 void    armv6_icache_sync_all   (void);
 281 void    armv6_icache_sync_range (vaddr_t, vsize_t);
 282
 283 void    armv6_dcache_wbinv_all  (void);
 284 void    armv6_dcache_wbinv_range (vaddr_t, vsize_t);
 285 void    armv6_dcache_inv_range  (vaddr_t, vsize_t);
 286 void    armv6_dcache_wb_range   (vaddr_t, vsize_t);
 287
 288 void    armv6_idcache_wbinv_all (void);
 289 void    armv6_idcache_wbinv_range (vaddr_t, vsize_t);
 290 #endif
 291
 292 #if defined(CPU_ARMV7)
 293 #if defined(ARM_MMU_EXTENDED)
 294 void    armv7_setttb(u_int, tlb_asid_t);
 295 void    armv7_context_switch(u_int, tlb_asid_t);
 296 #else
 297 void    armv7_setttb(u_int, bool);
 298 void    armv7_context_switch(u_int);
 299 #endif
 300
 301 void    armv7_icache_sync_range(vaddr_t, vsize_t);
 302 void    armv7_icache_sync_all(void);
 303
 304 void    armv7_dcache_inv_range(vaddr_t, vsize_t);
 305 void    armv7_dcache_wb_range(vaddr_t, vsize_t);
 306 void    armv7_dcache_wbinv_range(vaddr_t, vsize_t);
 307 void    armv7_dcache_wbinv_all(void);
 308
 309 void    armv7_idcache_wbinv_range(vaddr_t, vsize_t);
 310 void    armv7_idcache_wbinv_all(void);
 311
 312 void    armv7_tlb_flushID(void);
 313 void    armv7_tlb_flushI(void);
 314 void    armv7_tlb_flushD(void);
 315
 316 void    armv7_tlb_flushID_SE(vaddr_t);
 317 void    armv7_tlb_flushI_SE(vaddr_t);
 318 void    armv7_tlb_flushD_SE(vaddr_t);
 319
 320 void    armv7_cpu_sleep(int);
 321 void    armv7_drain_writebuf(void);
 322 void    armv7_setup(char *string);
 323 #endif /* CPU_ARMV7 */
 324
 325 #if defined(CPU_PJ4B)
 326 void    pj4b_cpu_sleep(int);
 327 void    pj4bv7_setup(char *string);
 328 void    pj4b_config(void);
 329 void    pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t);
 330 void    pj4b_dcache_cfu_inv_range(vaddr_t, vsize_t);
 331 void    pj4b_dcache_cfu_wb_range(vaddr_t, vsize_t);
 332 void    pj4b_dcache_cfu_wbinv_range(vaddr_t, vsize_t);
 333 #endif /* CPU_PJ4B */
 334
 335 #if defined(CPU_ARM1136) || defined(CPU_ARM1176)
 336 void    arm11x6_idcache_wbinv_all       (void);
 337 void    arm11x6_dcache_wbinv_all        (void);
 338 void    arm11x6_icache_sync_all         (void);
 339 void    arm11x6_flush_prefetchbuf       (void);
 340 void    arm11x6_icache_sync_range       (vaddr_t, vsize_t);
 341 void    arm11x6_idcache_wbinv_range     (vaddr_t, vsize_t);
 342 void    arm11x6_setup                   (char *string);
 343 void    arm11x6_sleep                   (int);  /* no ref. for errata */
 344 #endif
 345 #if defined(CPU_ARM1136)
 346 void    arm1136_sleep_rev0              (int);  /* for errata 336501 */
 347 #endif
 348
 349
 350 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
 351     defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
 352     defined(CPU_FA526) || defined(CPU_XSCALE) || defined(CPU_SHEEVA)
 353
 354 void    armv4_tlb_flushID       (void);
 355 void    armv4_tlb_flushI        (void);
 356 void    armv4_tlb_flushD        (void);
 357 void    armv4_tlb_flushD_SE     (vaddr_t);
 358
 359 void    armv4_drain_writebuf    (void);
 360 #endif
 361
 362 #if defined(CPU_IXP12X0)
 363 void    ixp12x0_drain_readbuf   (void);
 364 void    ixp12x0_context_switch  (u_int);
 365 void    ixp12x0_setup           (char *);
 366 #endif
 367
 368 #if defined(CPU_XSCALE)
 369 void    xscale_cpwait           (void);
 370
 371 void    xscale_cpu_sleep        (int);
 372
 373 u_int   xscale_control          (u_int, u_int);
 374
 375 void    xscale_setttb           (u_int, bool);
 376
 377 void    xscale_tlb_flushID_SE   (vaddr_t);
 378
 379 void    xscale_cache_flushID    (void);
 380 void    xscale_cache_flushI     (void);
 381 void    xscale_cache_flushD     (void);
 382 void    xscale_cache_flushD_SE  (vaddr_t);
 383
 384 void    xscale_cache_cleanID    (void);
 385 void    xscale_cache_cleanD     (void);
 386 void    xscale_cache_cleanD_E   (u_int);
 387
 388 void    xscale_cache_clean_minidata (void);
 389
 390 void    xscale_cache_purgeID    (void);
 391 void    xscale_cache_purgeID_E  (u_int);
 392 void    xscale_cache_purgeD     (void);
 393 void    xscale_cache_purgeD_E   (u_int);
 394
 395 void    xscale_cache_syncI      (void);
 396 void    xscale_cache_cleanID_rng (vaddr_t, vsize_t);
 397 void    xscale_cache_cleanD_rng (vaddr_t, vsize_t);
 398 void    xscale_cache_purgeID_rng (vaddr_t, vsize_t);
 399 void    xscale_cache_purgeD_rng (vaddr_t, vsize_t);
 400 void    xscale_cache_syncI_rng  (vaddr_t, vsize_t);
 401 void    xscale_cache_flushD_rng (vaddr_t, vsize_t);
 402
 403 void    xscale_context_switch   (u_int);
 404
 405 void    xscale_setup            (char *);
 406 #endif  /* CPU_XSCALE */
 407
 408 #if defined(CPU_SHEEVA)
 409 void    sheeva_dcache_wbinv_range (vaddr_t, vsize_t);
 410 void    sheeva_dcache_inv_range (vaddr_t, vsize_t);
 411 void    sheeva_dcache_wb_range  (vaddr_t, vsize_t);
 412 void    sheeva_idcache_wbinv_range (vaddr_t, vsize_t);
 413 void    sheeva_setup(char *);
 414 void    sheeva_cpu_sleep(int);
 415
 416 void    sheeva_sdcache_inv_range(vaddr_t, paddr_t, vsize_t);
 417 void    sheeva_sdcache_wb_range(vaddr_t, paddr_t, vsize_t);
 418 void    sheeva_sdcache_wbinv_range(vaddr_t, paddr_t, vsize_t);
 419 void    sheeva_sdcache_wbinv_all(void);
 420 #endif
 421
 422 #endif /* _KERNEL */
 423
 424 #endif  /* _ARM_CPUFUNC_PROTO_H_ */