drivers/dpeth/3c503.h

   1 /*
   2 **  File:       3c503.h         Dec. 20, 1996
   3 **
   4 **  Author:     Giovanni Falzoni <gfalzoni@inwind.it>
   5 **
   6 **  Interface description for 3Com Etherlink II boards
   7 **
   8 **  $Log$
   9 **  Revision 1.1  2005/06/29 10:16:46  beng
  10 **  Import of dpeth 3c501/3c509b/.. ethernet driver by
  11 **  Giovanni Falzoni <fgalzoni@inwind.it>.
  12 **
  13 **  Revision 2.0  2005/06/26 16:16:46  lsodgf0
  14 **  Initial revision for Minix 3.0.6
  15 */
  16
  17 #define EL2_MEMTEST     0       /* Set to 1 for on board memory test */
  18
  19 #define EL2_GA          0x0400  /* Offset of registers in Gate Array */
  20
  21 /* EtherLink II card */
  22
  23 #define EL2_STARTPG     (EL2_GA+0x00)   /* Start page matching DP_PSTARTPG */
  24 #define EL2_STOPPG      (EL2_GA+0x01)   /* Stop page matching DP_PSTOPPG   */
  25 #define EL2_DRQCNT      (EL2_GA+0x02)   /* DMA burst count                 */
  26 #define EL2_IOBASE      (EL2_GA+0x03)   /* I/O base jumpers (bit coded)    */
  27 #define EL2_MEMBASE     (EL2_GA+0x04)   /* Memory base jumpers (bit coded) */
  28 #define EL2_CFGR        (EL2_GA+0x05)   /* Configuration Register  for GA  */
  29 #define EL2_CNTR        (EL2_GA+0x06)   /* Control(write) and status(read) */
  30 #define EL2_STATUS      (EL2_GA+0x07)
  31 #define EL2_IDCFG       (EL2_GA+0x08)   /* Interrupt/DMA configuration reg */
  32 #define EL2_DMAAH       (EL2_GA+0x09)   /* DMA address register (High byte) */
  33 #define EL2_DMAAL       (EL2_GA+0x0A)   /* DMA address register (Low byte) */
  34 #define EL2_VP2         (EL2_GA+0x0B)   /* Vector pointer - set to         */
  35 #define EL2_VP1         (EL2_GA+0x0C)   /* reset address (0xFFFF:0)  */
  36 #define EL2_VP0         (EL2_GA+0x0D)   /* */
  37 #define EL2_FIFOH       (EL2_GA+0x0E)   /* FIFO for progr. I/O (High byte) */
  38 #define EL2_FIFOL       (EL2_GA+0x0F)   /* FIFO for progr. I/O (Low byte)  */
  39
  40 #define EL2_EA0         0x00    /* Most significant byte of ethernet address */
  41 #define EL2_EA1         0x01
  42 #define EL2_EA2         0x02
  43 #define EL2_EA3         0x03
  44 #define EL2_EA4         0x04
  45 #define EL2_EA5         0x05    /* Least significant byte of ethernet address */
  46
  47 /* Bits in EL2_CNTR register */
  48 #define ECNTR_RESET     0x01    /* Software Reset */
  49 #define ECNTR_THIN      0x02    /* Onboard transceiver enable */
  50 #define ECNTR_AUI       0x00    /* Onboard transceiver disable */
  51 #define ECNTR_SAPROM    0x04    /* Map the station address prom */
  52
  53 /* Bits in EL2_CFGR register */
  54 #define ECFGR_NORM      0x49    /* Enable 8k shared memory, no DMA, TC int */
  55 #define ECFGR_IRQOFF    0xC9    /* As above, disable 8390 IRQ */
  56
  57 /* Shared memory management parameters */
  58 #define EL2_SM_START_PG 0x20    /* First page of TX buffer */
  59 #define EL2_SM_STOP_PG  0x40    /* Last page +1 of RX ring */
  60
  61 /* Physical addresses where an Etherlink board can be configured */
  62 #define EL2_BASE_0C8000 0x0C8000
  63 #define EL2_BASE_0CC000 0x0CC000
  64 #define EL2_BASE_0D8000 0x0D8000
  65 #define EL2_BASE_0DC000 0x0DC000
  66
  67 #define inb_el2(dep,reg) (inb((dep)->de_base_port+(reg)))
  68 #define outb_el2(dep,reg,data) (outb((dep)->de_base_port+(reg),(data)))
  69
  70 /** 3c503.h **/