1 ///* TODO: Rename to MMCH_0_REG_BASE and add the base address for the other items */
2 //#define MMCHS1_REG_BASE 0x48060000
4 //#ifdef AM_DM37x_Multimedia_Device
5 #define MMCHS1_REG_BASE 0x4809C000
6 //#define MMCHS2_REG_BASE 0x480B4000
7 //#define MMCHS3_REG_BASE 0x480AD000
10 #define MMCHS_SD_SYSCONFIG 0x110 /* SD system configuration */
11 #define MMCHS_SD_SYSSTATUS 0x114 /* SD system status */
12 #define MMCHS_SD_CON 0x12c /* Configuration (functional mode,card initialization etc) */
13 #define MMCHS_SD_BLK 0x204 /* Transfer length configuration */
14 #define MMCHS_SD_ARG 0x208 /* Command argument bit 38-8 of command format*/
15 #define MMCHS_SD_CMD 0x20c /* Command and transfer mode */
16 #define MMCHS_SD_RSP10 0x210 /* Command response 0 and 1 */
17 #define MMCHS_SD_RSP32 0x214 /* Command response 2 and 3 */
18 #define MMCHS_SD_RSP54 0x218 /* Command response 4 and 5 */
19 #define MMCHS_SD_RSP76 0x21c /* Command response 6 and 7 */
20 #define MMCHS_SD_DATA 0x220 /* Data register */
21 #define MMCHS_SD_PSTATE 0x224 /* Present state */
22 #define MMCHS_SD_HCTL 0x228 /* Host control(power ,wake-up and transfer) */
23 #define MMCHS_SD_SYSCTL 0x22c /* SD System control (reset,clocks and timeout) */
24 #define MMCHS_SD_STAT 0x230 /* SD Interrupt status */
25 #define MMCHS_SD_IE 0x234 /* SD Interrupt Enable register */
26 #define MMCHS_SD_CAPA 0x240 /* Capabilities of the host controller */
27 #define MMCHS_SD_CUR_CAPA 0x248 /* Current capabilities of the host controller */
29 #define MMCHS_SD_SYSCONFIG_AUTOIDLE (0x1 << 0) /* Internal clock gating strategy */
30 #define MMCHS_SD_SYSCONFIG_AUTOIDLE_DIS (0x0 << 0) /* Clocks are free running */
31 #define MMCHS_SD_SYSCONFIG_AUTOIDLE_EN (0x1 << 0) /* Automatic clock gating strategy */
32 #define MMCHS_SD_SYSCONFIG_SOFTRESET (0x1 << 1) /* Software reset bit writing */
33 #define MMCHS_SD_SYSCONFIG_ENAWAKEUP (0x1 << 2) /* Wake-up feature control */
34 #define MMCHS_SD_SYSCONFIG_ENAWAKEUP_DIS (0x0 << 2) /* Disable wake-up capability */
35 #define MMCHS_SD_SYSCONFIG_ENAWAKEUP_EN (0x1 << 2) /* Enable wake-up capability */
36 #define MMCHS_SD_SYSCONFIG_SIDLEMODE (0x3 << 3) /* Power management */
37 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_UNCONDITIONAL (0x0 << 3) /* Go into idle mode unconditionally upon request */
38 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_IGNORE (0x1 << 3) /* Ignore ILDE requests */
39 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE (0x2 << 3) /* Acknowledge IDLE request switch to wake-up mode */
40 #define MMCHS_SD_SYSCONFIG_SIDLEMODE_SMART_IDLE (0x3 << 3) /* Smart-idle */
41 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY (0x3 << 8) /* Clock activity during wake-up */
42 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_OFF (0x0 << 8) /* Interface and functional clock can be switched off */
43 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_IF (0x1 << 8) /* Only Interface clock (functional can be switched off*/
44 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_FUNC (0x2 << 8) /* Only Functional clock (interface clock can be switched off) */
45 #define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_BOOTH (0x3 << 8) /* Booth the interface and functional clock are maintained */
46 #define MMCHS_SD_SYSCONFIG_STANDBYMODE (0x3 << 12) /* Configuration for standby */
47 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_FORCE_STANDBY (0x0 << 12) /* Force standby mode upon idle request*/
48 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_NO_STANDBY (0x1 << 12) /* Never go into standby mode */
49 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_INTERNAL (0x2 << 12) /* Go into wake-up mode based on internal knowledge */
50 #define MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_SMART (0x3 << 12) /* Go info wake-up mode when possible */
52 #define MMCHS_SD_SYSSTATUS_RESETDONE 0x01
54 #define MMCHS_SD_CON_DW8 (0x1 << 5) /* 8-bit mode MMC select , For SD clear this bit */
55 #define MMCHS_SD_CON_DW8_1BIT (0x0 << 5) /* 1 or 4 bits data width configuration(also set SD_HCTL) */
56 #define MMCHS_SD_CON_DW8_8BITS (0x1 << 5) /* 8 bits data width configuration */
57 #define MMCHS_SD_CON_INIT (0x1 << 1) /* Send initialization stream (all cards) */
58 #define MMCHS_SD_CON_INIT_NOINIT (0x0 << 1) /* Do nothing */
59 #define MMCHS_SD_CON_INIT_INIT (0x1 << 1) /* Send initialization stream */
61 #define MMCHS_SD_BLK_NBLK (0xffffu << 16) /* Block count for the current transfer */
62 #define MMCHS_SD_BLK_BLEN (0xfff << 0) /* Transfer block size */
63 #define MMCHS_SD_BLK_BLEN_NOTRANSFER (0x0 << 0) /* No transfer */
65 #define MMCHS_SD_CMD_INDX (0x3f << 24) /* Command index */
66 #define MMCHS_SD_CMD_INDX_CMD(x) (x << 24) /* MMC command index binary encoded values from 0 to 63 */
68 #define MMCHS_SD_ARG_MASK (0xffffffffu) /* Mask everything */
69 #define MMCHS_SD_ARG_CMD8_VHS (0x1 << (16 - 8)) /* Voltage between 2.7 and 3.6 v*/
70 #define MMCHS_SD_ARG_CMD8_CHECK_PATTERN (0xaa <<(8 - 8)) /* 10101010b pattern */
72 #define MMCHS_SD_CMD_TYPE (0x3 << 22) /* Command type. */
73 #define MMCHS_SD_CMD_TYPE_OTHER (0x0 << 22) /* Other type of commands (like go idle) */
74 #define MMCHS_SD_CMD_TYPE_BUS_SUSPEND (0x1 << 22) /* Upon CMD52 "Bus Suspend" operation */
75 #define MMCHS_SD_CMD_TYPE_FUNCTION_SELECT (0x2 << 22) /* Upon CMD52 "Function Select" operation */
76 #define MMCHS_SD_CMD_TYPE_IOABORT (0x3 << 22) /* Upon CMD12 and CMD21 "I/O Abort */
77 #define MMCHS_SD_CMD_DP (0x1 << 21) /* Data present select */
78 #define MMCHS_SD_CMD_DP_DATA (0x1 << 21) /* Additional data is present on the data lines */
79 #define MMCHS_SD_CMD_DP_NODATA (0x0 << 21) /* No additional data is present on the data lines */
80 #define MMCHS_SD_CMD_CICE (0x1 << 20) /* Command index response check enable */
81 #define MMCHS_SD_CMD_CICE_ENABLE (0x1 << 20) /* Enable index check response */
82 #define MMCHS_SD_CMD_CICE_DISABLE (0x0 << 20) /* Disable index check response */
83 #define MMCHS_SD_CMD_CCCE (0x1 << 19) /* Command CRC7 Check enable on responses*/
84 #define MMCHS_SD_CMD_CCCE_ENABLE (0x1 << 19) /* Enable CRC7 Check on response */
85 #define MMCHS_SD_CMD_CCCE_DISABLE (0x0 << 19) /* Disable CRC7 Check on response */
86 #define MMCHS_SD_CMD_RSP_TYPE (0x3 << 16) /* Response type */
87 #define MMCHS_SD_CMD_RSP_TYPE_NO_RESP (0x0 << 16) /* No response */
88 #define MMCHS_SD_CMD_RSP_TYPE_136B (0x1 << 16) /* Response length 136 bits */
89 #define MMCHS_SD_CMD_RSP_TYPE_48B (0x2 << 16) /* Response length 48 bits */
90 #define MMCHS_SD_CMD_RSP_TYPE_48B_BUSY (0x3 << 16) /* Response length 48 bits with busy after response */
91 #define MMCHS_SD_CMD_MSBS (0x1 << 5) /* Multi/Single block select */
92 #define MMCHS_SD_CMD_MSBS_SINGLE (0x0 << 5) /* Single block mode */
93 #define MMCHS_SD_CMD_MSBS_MULTI (0x0 << 5) /* Multi block mode */
94 #define MMCHS_SD_CMD_DDIR (0x1 << 4) /* Data transfer direction */
95 #define MMCHS_SD_CMD_DDIR_READ (0x1 << 4) /* Data read (card to host) */
96 #define MMCHS_SD_CMD_DDIR_WRITE (0x0 << 4) /* Data write (host to card) */
97 #define MMCHS_SD_CMD_ACEN (0x1 << 2) /* Auto CMD12 Enable */
98 #define MMCHS_SD_CMD_ACEN_DIS (0x0 << 2) /* Auto CMD12 Disable */
99 #define MMCHS_SD_CMD_ACEN_EN (0x1 << 2) /* Auto CMD12 Enable */
100 #define MMCHS_SD_CMD_BCE (0x1 << 1) /* Block Count Enable(for multi block transfer) */
101 #define MMCHS_SD_CMD_BCE_DIS (0x0 << 1) /* Disabled block count for infinite transfer*/
102 #define MMCHS_SD_CMD_BCE_EN (0x1 << 1) /* Enabled for multi block transfer with know amount of blocks */
103 #define MMCHS_SD_CMD_DE (0x1 << 0) /* DMA enable */
104 #define MMCHS_SD_CMD_DE_DIS (0x0 << 0) /* Disable DMA */
105 #define MMCHS_SD_CMD_DE_EN (0x1 << 0) /* Enable DMA */
106 #define MMCHS_SD_CMD_MASK ~(0x1 << 30 | 0x1 << 31 | 0x1 << 18 | 0x1 <<3) /* bits 30 , 31 and 18 are reserved */
108 #define MMCHS_SD_PSTATE_CI (0x1 << 16) /* Card Inserted */
109 #define MMCHS_SD_PSTATE_CI_INSERTED (0x1 << 16) /* Card Inserted is inserted*/
110 #define MMCHS_SD_PSTATE_BRE (0x0 << 11) /* Buffer read enable */
111 #define MMCHS_SD_PSTATE_BRE_DIS (0x0 << 11) /* Read BLEN bytes disabled*/
112 #define MMCHS_SD_PSTATE_BRE_EN (0x1 << 11) /* Read BLEN bytes enabled*/
113 #define MMCHS_SD_PSTATE_BWE (0x0 << 10) /* Buffer Write enable */
114 #define MMCHS_SD_PSTATE_BWE_DIS (0x0 << 10) /* There is no room left in the buffer to write BLEN bytes of data */
115 #define MMCHS_SD_PSTATE_BWE_EN (0x1 << 10) /* There is enough space in the buffer to write BLEN bytes of data*/
117 #define MMCHS_SD_HCTL_DTW (0x1 << 1) /*Data transfer width.(must be set after a successful ACMD6) */
118 #define MMCHS_SD_HCTL_DTW_1BIT (0x0 << 1) /*1 bit transfer with */
119 #define MMCHS_SD_HCTL_DTW_4BIT (0x1 << 1) /*4 bit transfer with */
120 #define MMCHS_SD_HCTL_SDBP (0x1 << 8) /*SD bus power */
121 #define MMCHS_SD_HCTL_SDBP_OFF (0x0 << 8) /*SD Power off (start card detect?) */
122 #define MMCHS_SD_HCTL_SDBP_ON (0x1 << 8) /*SD Power on (start card detect?) */
123 #define MMCHS_SD_HCTL_SDVS (0x7 << 9) /*SD bus voltage select */
124 #define MMCHS_SD_HCTL_SDVS_VS18 (0x5 << 9) /*1.8 V */
125 #define MMCHS_SD_HCTL_SDVS_VS30 (0x6 << 9) /*3.0 V */
126 #define MMCHS_SD_HCTL_SDVS_VS33 (0x7 << 9) /*3.3 V */
127 #define MMCHS_SD_HCTL_IWE (0x1 << 24)/* wake-up event on SD interrupt */
128 #define MMCHS_SD_HCTL_IWE_DIS (0x0 << 24)/* Disable wake-up on SD interrupt */
129 #define MMCHS_SD_HCTL_IWE_EN (0x1 << 24)/* Enable wake-up on SD interrupt */
131 #define MMCHS_SD_SYSCTL_CLKD (0x3ff << 6) /* 10 bits clock frequency select */
132 #define MMCHS_SD_SYSCTL_SRD (0x1 << 26) /* Soft reset for mmc_dat line */
133 #define MMCHS_SD_SYSCTL_SRC (0x1 << 25) /* Soft reset for mmc_cmd line */
134 #define MMCHS_SD_SYSCTL_SRA (0x1 << 24) /* Soft reset all (host controller) */
136 #define MMCHS_SD_SYSCTL_ICE (0x1 << 0) /* Internal clock enable register */
137 #define MMCHS_SD_SYSCTL_ICE_DIS (0x0 << 0) /* Disable internal clock */
138 #define MMCHS_SD_SYSCTL_ICE_EN (0x1 << 0) /* Enable internal clock */
139 #define MMCHS_SD_SYSCTL_ICS (0x1 << 1) /* Internal clock stable register */
140 #define MMCHS_SD_SYSCTL_ICS_UNSTABLE (0x0 << 1) /* Internal clock is unstable */
141 #define MMCHS_SD_SYSCTL_ICS_STABLE (0x1 << 1) /* Internal clock is stable */
142 #define MMCHS_SD_SYSCTL_CEN (0x1 << 2) /* Card lock enable provide clock to the card */
143 #define MMCHS_SD_SYSCTL_CEN_DIS (0x0 << 2) /* Internal clock is unstable */
144 #define MMCHS_SD_SYSCTL_CEN_EN (0x1 << 2) /* Internal clock is stable */
146 #define MMCHS_SD_SYSCTL_DTO (0xf << 16) /* Data timeout counter */
147 #define MMCHS_SD_SYSCTL_DTO_2POW13 (0x0 << 16) /* TCF x 2^13 */
148 #define MMCHS_SD_SYSCTL_DTO_2POW14 (0x1 << 16) /* TCF x 2^14 */
149 #define MMCHS_SD_SYSCTL_DTO_2POW27 (0x3 << 16) /* TCF x 2^27 */
151 #define MMCHS_SD_STAT_ERRI (0x01 << 15) /* Error interrupt */
152 #define MMCHS_SD_STAT_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28)
153 #define MMCHS_SD_STAT_CC (0x1 << 0) /* Command complete status */
154 #define MMCHS_SD_STAT_CC_UNRAISED (0x0 << 0) /* Command not completed */
155 #define MMCHS_SD_STAT_CC_RAISED (0x1 << 0) /* Command completed */
157 #define MMCHS_SD_IE_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28)
159 #define MMCHS_SD_IE_CC_ENABLE (0x1 << 0) /* Command complete interrupt enable */
160 #define MMCHS_SD_IE_CC_ENABLE_ENABLE (0x1 << 0) /* Command complete Interrupts are enabled */
161 #define MMCHS_SD_IE_CC_ENABLE_CLEAR (0x1 << 0) /* Clearing is done by writing a 0x1 */
163 #define MMCHS_SD_IE_TC_ENABLE (0x1 << 1) /* Transfer complete interrupt enable */
164 #define MMCHS_SD_IE_TC_ENABLE_ENABLE (0x1 << 1) /* Transfer complete Interrupts are enabled */
165 #define MMCHS_SD_IE_TC_ENABLE_CLEAR (0x1 << 1) /* Clearing TC is done by writing a 0x1 */
167 #define MMCHS_SD_IE_BRR_ENABLE (0x1 << 5) /* Buffer read ready interrupt */
168 #define MMCHS_SD_IE_BRR_ENABLE_DISABLE (0x0 << 5) /* Buffer read ready interrupt disable */
169 #define MMCHS_SD_IE_BRR_ENABLE_ENABLE (0x1 << 5) /* Buffer read ready interrupt enable */
170 #define MMCHS_SD_IE_BRR_ENABLE_CLEAR (0x1 << 5) /* Buffer read ready interrupt clear */
172 #define MMCHS_SD_IE_BWR_ENABLE (0x1 << 4) /* Buffer write ready interrupt */
173 #define MMCHS_SD_IE_BWR_ENABLE_DISABLE (0x0 << 4) /* Buffer write ready interrupt disable */
174 #define MMCHS_SD_IE_BWR_ENABLE_ENABLE (0x1 << 4) /* Buffer write ready interrupt enable */
175 #define MMCHS_SD_IE_BWR_ENABLE_CLEAR (0x1 << 4) /* Buffer write ready interrupt clear */
177 #define MMCHS_SD_CAPA_VS_MASK (0x7 << 24 ) /* voltage mask */
178 #define MMCHS_SD_CAPA_VS18 (0x01 << 26 ) /* 1.8 volt */
179 #define MMCHS_SD_CAPA_VS30 (0x01 << 25 ) /* 3.0 volt */
180 #define MMCHS_SD_CAPA_VS33 (0x01 << 24 ) /* 3.3 volt */
